`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*
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/*
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In order to read the geometry, we will behave as a master.
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In order to read the geometry, we will behave as a master.
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Performing single Reads Bus cycles should be sufficient.
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Performing single Reads Bus cycles should be sufficient.
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Choosing 32 bit for bus width for simplicity.
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Choosing 32 bit for bus width for simplicity.
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*/
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*/
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module WishBoneMasterUnit
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module WishBoneMasterUnit
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(
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(
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//WB Input signals
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//WB Input signals
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input wire CLK_I,
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input wire CLK_I,
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input wire RST_I,
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input wire RST_I,
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input wire ACK_I,
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input wire ACK_I,
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input wire GNT_I, //granted signal from bus arbiter
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input wire GNT_I, //granted signal from bus arbiter
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input wire [`WB_WIDTH-1:0 ] DAT_I,
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input wire [`WB_WIDTH-1:0 ] DAT_I,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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//WB Output Signals
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//WB Output Signals
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output wire [`WB_WIDTH-1:0 ] ADR_O,
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output wire [`WB_WIDTH-1:0 ] ADR_O,
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output wire WE_O,
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output wire WE_O,
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output wire STB_O,
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output wire STB_O,
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output wire CYC_O,
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output wire CYC_O,
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output wire [1:0] TGC_O,
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output wire [1:0] TGC_O,
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//Signals from inside the GPU
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//Signals from inside the GPU
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input wire iEnable,
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input wire iEnable,
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input wire iBusCyc_Type,
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input wire iBusCyc_Type,
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input wire [`WIDTH-1:0 ] iAddress,
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input wire [`WIDTH-1:0 ] iAddress,
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input wire iAddress_Set,
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input wire iAddress_Set,
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output wire oDataReady,
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output wire oDataReady,
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input wire [`WIDTH-1:0 ] iData,
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input wire [`WIDTH-1:0 ] iData,
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output wire [`WIDTH-1:0 ] oData
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output wire [`WIDTH-1:0 ] oData
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);
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);
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wire wReadOperation;
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wire wReadOperation;
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wire wEnable;
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wire wEnable;
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assign wEnable = iEnable & GNT_I;
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assign wEnable = iEnable & GNT_I;
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//If CYC_O is 1, it means we are requesting bus ownership
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//If CYC_O is 1, it means we are requesting bus ownership
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assign CYC_O = iEnable;
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assign CYC_O = iEnable;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_READ_CYCLE) ? 1 : 0;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_READ_CYCLE) ? 1 : 0;
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assign WE_O = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE && wEnable) ? 1 : 0;
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assign WE_O = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE && wEnable) ? 1 : 0;
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wire wEnable_Delayed;
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wire wEnable_Delayed;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD88
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD88
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Reset(RST_I),
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.Reset(RST_I),
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.Enable(1'b1 ),
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.Enable(1'b1 ),
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.D(wEnable),
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.D(wEnable),
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.Q(wEnable_Delayed)
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.Q(wEnable_Delayed)
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);
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);
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//We only start Strobbing 1 cycle after iEnable and only
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//We only start Strobbing 1 cycle after iEnable and only
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//if iEnable is 1 and if GNT_I is 1 (meaning we own the bus)
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//if iEnable is 1 and if GNT_I is 1 (meaning we own the bus)
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assign STB_O = wEnable_Delayed & ~ACK_I & wEnable;
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assign STB_O = wEnable_Delayed & ~ACK_I & wEnable;
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assign DAT_O = (wReadOperation | ~wEnable ) ? `WB_WIDTH'bz : iData;
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assign DAT_O = (wReadOperation | ~wEnable ) ? `WB_WIDTH'bz : iData;
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wire [`WB_WIDTH-1:0 ] wReadADR_O,wWriteADR_O;
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wire [`WB_WIDTH-1:0 ] wReadADR_O,wWriteADR_O;
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assign ADR_O = ( wReadOperation ) ? wReadADR_O : wWriteADR_O;
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assign ADR_O = ( wReadOperation ) ? wReadADR_O : wWriteADR_O;
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//The ADR_O, it increments with each ACK_I, and it resets
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//The ADR_O, it increments with each ACK_I, and it resets
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//to the value iAddress everytime iAddress_Set is 1.
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//to the value iAddress everytime iAddress_Set is 1.
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UPCOUNTER_POSEDGE # (`WIDTH) WBM_O_READ_ADDRESS
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UPCOUNTER_POSEDGE # (`WIDTH) WBM_O_READ_ADDRESS
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Reset( iAddress_Set ),
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.Reset( iAddress_Set ),
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.Enable((ACK_I & GNT_I) | iAddress_Set),
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.Enable((ACK_I & GNT_I) | iAddress_Set),
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.Initial(iAddress),
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.Initial(iAddress),
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.Q(wReadADR_O)
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.Q(wReadADR_O)
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);
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);
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wire wDelayWE;
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wire wDelayWE;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Reset(RST_I),
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.Reset(RST_I),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(WE_O),
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.D(WE_O),
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.Q(wDelayWE)
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.Q(wDelayWE)
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);
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);
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UPCOUNTER_POSEDGE # (`WIDTH) WBM_O_WRITE_ADDRESS
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UPCOUNTER_POSEDGE # (`WIDTH) WBM_O_WRITE_ADDRESS
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Reset( iAddress_Set ),//RST_I ),
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.Reset( iAddress_Set ),//RST_I ),
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.Enable( (wDelayWE & ACK_I ) | iAddress_Set),
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.Enable( (wDelayWE & ACK_I ) | iAddress_Set),
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.Initial(iAddress),//`WIDTH'b0),
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.Initial(iAddress),//`WIDTH'b0),
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.Q(wWriteADR_O)
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.Q(wWriteADR_O)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD1
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(
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(
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.Clock(ACK_I),
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.Clock(ACK_I),
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.Reset(~wEnable),
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.Reset(~wEnable),
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.Enable(wReadOperation ),
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.Enable(wReadOperation ),
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.D(DAT_I),
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.D(DAT_I),
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.Q(oData)
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.Q(oData)
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);
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);
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wire wDelayDataReady;
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wire wDelayDataReady;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Reset(~wEnable),
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.Reset(~wEnable),
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.Enable(wReadOperation),
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.Enable(wReadOperation),
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.D(ACK_I),
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.D(ACK_I),
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.Q(wDelayDataReady)
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.Q(wDelayDataReady)
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);
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);
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/*
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/*
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always @ (posedge wDelayDataReady)
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always @ (posedge wDelayDataReady)
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begin
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begin
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$display("WBM Got data: %h ",oData);
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$display("WBM Got data: %h ",oData);
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$display("oDataReady = %d",oDataReady );
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$display("oDataReady = %d",oDataReady );
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end
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end
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*/
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*/
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assign oDataReady = wDelayDataReady & wEnable;
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assign oDataReady = wDelayDataReady & wEnable;
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endmodule
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endmodule
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