`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define ADR_IMM 1
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`define ADR_IMM 1
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`define ADR_POINTER 0
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`define ADR_POINTER 0
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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|
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***********************************************************************************/
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***********************************************************************************/
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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module IO_Unit
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module IO_Unit
|
(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire [`DATA_ADDRESS_WIDTH-1:0] iDat_O_Pointer, //Pointer to what we want to send via DAT_O
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input wire [`DATA_ADDRESS_WIDTH-1:0] iDat_O_Pointer, //Pointer to what we want to send via DAT_O
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input wire [`WIDTH-1:0] iAdr_O_Imm, //Value to assign to ADR_O
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input wire [`WIDTH-1:0] iAdr_O_Imm, //Value to assign to ADR_O
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input wire [`DATA_ADDRESS_WIDTH-1:0] iAdr_O_Pointer, //Pointer to value to assing to ADR_O
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input wire [`DATA_ADDRESS_WIDTH-1:0] iAdr_O_Pointer, //Pointer to value to assing to ADR_O
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input wire iAdr_O_Type, //Should we use iAdr_O_Imm or iAdr_O_Pointer
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input wire iAdr_O_Type, //Should we use iAdr_O_Imm or iAdr_O_Pointer
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input wire iAdr_O_Set, //Should we set
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input wire iAdr_O_Set, //Should we set
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input wire iBusCyc_Type, //Bus cycle type: simple read/write, etc.
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input wire iBusCyc_Type, //Bus cycle type: simple read/write, etc.
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input wire iStore, //Should we store read data into MEM
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input wire iStore, //Should we store read data into MEM
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input wire [`DATA_ROW_WIDTH-1:0] iReadDataBus, //MEM Data read bus 1
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input wire [`DATA_ROW_WIDTH-1:0] iReadDataBus, //MEM Data read bus 1
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input wire [`DATA_ROW_WIDTH-1:0] iReadDataBus2, //MEM Data read bus 2
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input wire [`DATA_ROW_WIDTH-1:0] iReadDataBus2, //MEM Data read bus 2
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input wire[`DATA_ADDRESS_WIDTH-1:0] iAdr_DataWriteBack, //Where in MEM we want to store DAT_I
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input wire[`DATA_ADDRESS_WIDTH-1:0] iAdr_DataWriteBack, //Where in MEM we want to store DAT_I
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input wire iWriteBack_Set, //We want to set the Write back Address?
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input wire iWriteBack_Set, //We want to set the Write back Address?
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|
|
|
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress2,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress2,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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output wire oDataWriteEnable,
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output wire oDataWriteEnable,
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output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire oInstructionWriteEnable,
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output wire oInstructionWriteEnable,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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inout wire [`WIDTH-1:0] oData,
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inout wire [`WIDTH-1:0] oData,
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output wire oBusy,
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output wire oBusy,
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output wire oDone,
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output wire oDone,
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//Theia specific interfaces
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//Theia specific interfaces
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input wire MST_I,
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input wire MST_I,
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//Wish Bone Interfaces
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//Wish Bone Interfaces
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output wire [31:0] DAT_O,
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output wire [31:0] DAT_O,
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input wire [31:0] DAT_I,
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input wire [31:0] DAT_I,
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input wire ACK_I,
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input wire ACK_I,
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output wire ACK_O,
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output wire ACK_O,
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output wire [31:0] ADR_O,
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output wire [31:0] ADR_O,
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output wire [31:0] ADR_I,
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output wire [31:0] ADR_I,
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output wire WE_O,
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output wire WE_O,
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input wire WE_I,
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input wire WE_I,
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output wire STB_O,
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output wire STB_O,
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input wire STB_I,
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input wire STB_I,
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output wire CYC_O,
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output wire CYC_O,
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input wire CYC_I,
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input wire CYC_I,
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input wire [1:0] TGA_I,
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input wire [1:0] TGA_I,
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output wire [1:0] TGC_O,
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output wire [1:0] TGC_O,
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input wire GNT_I
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input wire GNT_I
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);
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);
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|
|
|
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement2;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement2;
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wire wMEMToWBM_2__Enable;
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wire wMEMToWBM_2__Enable;
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wire wWBMToMEM2__Done;
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wire wWBMToMEM2__Done;
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wire wWBM_2_WBMToMEM_DataAvailable;
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wire wWBM_2_WBMToMEM_DataAvailable;
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wire [`WIDTH-1:0] wWBM_2_WBMToMEM_Data;
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wire [`WIDTH-1:0] wWBM_2_WBMToMEM_Data;
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wire [`WIDTH-1:0] wWBS_2__WBMToMEM_Frame;
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wire [`WIDTH-1:0] wWBS_2__WBMToMEM_Frame;
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wire wWBMToMEM_2_WBM_Enable;
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wire wWBMToMEM_2_WBM_Enable;
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wire [`WIDTH-1:0] wWBMToMEM_2_WBM_Address;
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wire [`WIDTH-1:0] wWBMToMEM_2_WBM_Address;
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wire wWBMToMEM2__oDataWriteEnable;
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wire wWBMToMEM2__oDataWriteEnable;
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wire wAddrerssSelector2_oDataWriteEnable;
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wire wAddrerssSelector2_oDataWriteEnable;
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wire [`DATA_ROW_WIDTH-1:0] wWBMToMEM2__oDataBus;
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wire [`DATA_ROW_WIDTH-1:0] wWBMToMEM2__oDataBus;
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wire [`DATA_ROW_WIDTH-1:0] wWBSToMEM2__oDataBus;
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wire [`DATA_ROW_WIDTH-1:0] wWBSToMEM2__oDataBus;
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wire wAddressSelector_2__SetAddress;
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wire wAddressSelector_2__SetAddress;
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wire [`WIDTH-1:0] wMEMToWBM_2__Address;
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wire [`WIDTH-1:0] wMEMToWBM_2__Address;
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wire wMEMToWBM_2__Done;
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wire wMEMToWBM_2__Done;
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wire w2WBMToMEM__Enable;
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wire w2WBMToMEM__Enable;
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wire w2WBMToMEM__SetAddress;
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wire w2WBMToMEM__SetAddress;
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wire wWBS_2__WBSToMEM_FrameAvailable;
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wire wWBS_2__WBSToMEM_FrameAvailable;
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wire[`WIDTH-1:0] wWBS_2__WBMToMEM_Address;
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wire[`WIDTH-1:0] wWBS_2__WBMToMEM_Address;
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wire wWBSToMEM2__oDataWriteEnable;
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wire wWBSToMEM2__oDataWriteEnable;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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|
|
|
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assign oBusy = CYC_O;
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assign oBusy = CYC_O;
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wire wReadOperation;
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wire wReadOperation;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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|
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|
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assign wMEMToWBM_2__Address = ( iAdr_O_Type == `ADR_IMM ) ? iAdr_O_Imm : wMEMToWBM2__ReadDataElement;
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assign wMEMToWBM_2__Address = ( iAdr_O_Type == `ADR_IMM ) ? iAdr_O_Imm : wMEMToWBM2__ReadDataElement;
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assign w2WBMToMEM__Enable = ( iAdr_O_Type == `ADR_IMM ) ? iEnable : wMEMToWBM_2__Enable;
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assign w2WBMToMEM__Enable = ( iAdr_O_Type == `ADR_IMM ) ? iEnable : wMEMToWBM_2__Enable;
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//assign oDone = ( (iAdr_O_Type == `ADR_IMM) && !(iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) )
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//assign oDone = ( (iAdr_O_Type == `ADR_IMM) && !(iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) )
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//? wWBMToMEM2__Done : wMEMToWBM_2__Done;
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//? wWBMToMEM2__Done : wMEMToWBM_2__Done;
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|
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//TODO: WHEN ADR_POINTER Then Done is not until we got the 3 values from X,Y,Z in iAdr_O_Pointer
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//TODO: WHEN ADR_POINTER Then Done is not until we got the 3 values from X,Y,Z in iAdr_O_Pointer
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assign oDone = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE || iAdr_O_Type == `ADR_POINTER ) ? wMEMToWBM_2__Done : wWBMToMEM2__Done;
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assign oDone = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE || iAdr_O_Type == `ADR_POINTER ) ? wMEMToWBM_2__Done : wWBMToMEM2__Done;
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|
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assign oDataWriteEnable = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteEnable : (wWBMToMEM2__oDataWriteEnable);// ^ wAddrerssSelector2_oDataWriteEnable);
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assign oDataWriteEnable = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteEnable : (wWBMToMEM2__oDataWriteEnable);// ^ wAddrerssSelector2_oDataWriteEnable);
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assign oDataWriteAddress = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteAddress : wWBMToMEM2__oDataWriteAddress;
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assign oDataWriteAddress = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteAddress : wWBMToMEM2__oDataWriteAddress;
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assign oDataBus = (MST_I == 1'b1) ? wWBSToMEM2__oDataBus : wWBMToMEM2__oDataBus;
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assign oDataBus = (MST_I == 1'b1) ? wWBSToMEM2__oDataBus : wWBMToMEM2__oDataBus;
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|
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|
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wire [`DATA_ADDRESS_WIDTH-1:0] wMEMToWBM2_WBMToMEM_RAMWriteAddr;
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wire [`DATA_ADDRESS_WIDTH-1:0] wMEMToWBM2_WBMToMEM_RAMWriteAddr;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2WBMToMEM_MEMWriteAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2WBMToMEM_MEMWriteAddress;
|
|
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assign w2WBMToMEM_MEMWriteAddress = ( iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wMEMToWBM2_WBMToMEM_RAMWriteAddr;
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assign w2WBMToMEM_MEMWriteAddress = ( iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wMEMToWBM2_WBMToMEM_RAMWriteAddr;
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|
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wire w2MEMToWBM_BusOperationComplete;
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wire w2MEMToWBM_BusOperationComplete;
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assign w2MEMToWBM_BusOperationComplete = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? ACK_I : wWBMToMEM2__Done;
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assign w2MEMToWBM_BusOperationComplete = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? ACK_I : wWBMToMEM2__Done;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2MEMToWBM_DataPointer;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2MEMToWBM_DataPointer;
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assign w2MEMToWBM_DataPointer = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? iDat_O_Pointer : iAdr_O_Pointer;
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assign w2MEMToWBM_DataPointer = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? iDat_O_Pointer : iAdr_O_Pointer;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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MEM2WBMUnitB MEMToWBM
|
MEM2WBMUnitB MEMToWBM
|
(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iEnable( iEnable & (~iAdr_O_Type | iBusCyc_Type) ),
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.iEnable( iEnable & (~iAdr_O_Type | iBusCyc_Type) ),
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.iMEMDataPointer( w2MEMToWBM_DataPointer ),
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.iMEMDataPointer( w2MEMToWBM_DataPointer ),
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.iMEMDataPointer2( iAdr_O_Pointer ),
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.iMEMDataPointer2( iAdr_O_Pointer ),
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.iReadDataBus( iReadDataBus ), //3 Elements comming from DMEM
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.iReadDataBus( iReadDataBus ), //3 Elements comming from DMEM
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.iReadDataBus2( iReadDataBus2 ),
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.iReadDataBus2( iReadDataBus2 ),
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.oReadDataElement( wMEMToWBM2__ReadDataElement ), //1 out of 3 elements we read
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.oReadDataElement( wMEMToWBM2__ReadDataElement ), //1 out of 3 elements we read
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.oReadDataElement2( wMEMToWBM2__ReadDataElement2 ), //1 out of 3 elements we read
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.oReadDataElement2( wMEMToWBM2__ReadDataElement2 ), //1 out of 3 elements we read
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.oDataReadAddress( oDataReadAddress ),
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.oDataReadAddress( oDataReadAddress ),
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.oDataReadAddress2( oDataReadAddress2 ),
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.oDataReadAddress2( oDataReadAddress2 ),
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.oDataWriteEnable( wAddrerssSelector2_oDataWriteEnable ), //Always zero
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.oDataWriteEnable( wAddrerssSelector2_oDataWriteEnable ), //Always zero
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.oDataAvailable( wMEMToWBM_2__Enable ), //Data from MEM available
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.oDataAvailable( wMEMToWBM_2__Enable ), //Data from MEM available
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.iRequestNextElement( w2MEMToWBM_BusOperationComplete ),
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.iRequestNextElement( w2MEMToWBM_BusOperationComplete ),
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.iDataInitialStorageAddress( iAdr_DataWriteBack ), ////########
|
.iDataInitialStorageAddress( iAdr_DataWriteBack ), ////########
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.oDataWriteAddress( wMEMToWBM2_WBMToMEM_RAMWriteAddr ), ////########
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.oDataWriteAddress( wMEMToWBM2_WBMToMEM_RAMWriteAddr ), ////########
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.oDone( wMEMToWBM_2__Done )
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.oDone( wMEMToWBM_2__Done )
|
);
|
);
|
//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
|
wire [`DATA_ADDRESS_WIDTH-1:0] wTemp1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wTemp1;
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assign wWBMToMEM2__oDataWriteAddress = (iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wTemp1;
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assign wWBMToMEM2__oDataWriteAddress = (iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wTemp1;
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WBM2MEMUnit WBMToMEM
|
WBM2MEMUnit WBMToMEM
|
(
|
(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
|
.iEnable( w2WBMToMEM__Enable & (wReadOperation | MST_I) ), //Don't write stuff to MEM unless is Read bus cycle
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.iEnable( w2WBMToMEM__Enable & (wReadOperation | MST_I) ), //Don't write stuff to MEM unless is Read bus cycle
|
|
|
.iStore( iStore | ~iAdr_O_Type ),
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.iStore( iStore | ~iAdr_O_Type ),
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.iWriteBack_Set( iWriteBack_Set ),
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.iWriteBack_Set( iWriteBack_Set ),
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.iAdr_DataWriteBack(w2WBMToMEM_MEMWriteAddress ),
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.iAdr_DataWriteBack(w2WBMToMEM_MEMWriteAddress ),
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//.iAdr_DataWriteBack( iAdr_DataWriteBack ),
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//.iAdr_DataWriteBack( iAdr_DataWriteBack ),
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.iWBMDataAvailable( wWBM_2_WBMToMEM_DataAvailable ),
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.iWBMDataAvailable( wWBM_2_WBMToMEM_DataAvailable ),
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.iWBMData( wWBM_2_WBMToMEM_Data ),
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.iWBMData( wWBM_2_WBMToMEM_Data ),
|
|
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.oDataBus( wWBMToMEM2__oDataBus ),
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.oDataBus( wWBMToMEM2__oDataBus ),
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.oData( oData ),
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.oData( oData ),
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.oEnableWBM( wWBMToMEM_2_WBM_Enable ),
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.oEnableWBM( wWBMToMEM_2_WBM_Enable ),
|
.oDataWriteAddress( wTemp1 ),///*******************!!!!!!!!!!!!!!
|
.oDataWriteAddress( wTemp1 ),///*******************!!!!!!!!!!!!!!
|
.oDataWriteEnable( wWBMToMEM2__oDataWriteEnable ),
|
.oDataWriteEnable( wWBMToMEM2__oDataWriteEnable ),
|
.oDone( wWBMToMEM2__Done )
|
.oDone( wWBMToMEM2__Done )
|
);
|
);
|
|
|
|
|
|
|
wire [`WIDTH-1:0] wADR_O_InitialAddress;
|
wire [`WIDTH-1:0] wADR_O_InitialAddress;
|
assign wADR_O_InitialAddress = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM2__ReadDataElement2 : wMEMToWBM_2__Address;
|
assign wADR_O_InitialAddress = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM2__ReadDataElement2 : wMEMToWBM_2__Address;
|
wire wIncrement_Address_O;
|
wire wIncrement_Address_O;
|
assign wIncrement_Address_O = iEnable & ACK_I;
|
assign wIncrement_Address_O = iEnable & ACK_I;
|
|
|
|
|
|
|
wire wMEMToWBM2__Done;
|
wire wMEMToWBM2__Done;
|
wire wMEMToWBM2__Trigger;
|
wire wMEMToWBM2__Trigger;
|
wire[`WB_WIDTH-1:0] wMEMToWBM_2_Data;
|
wire[`WB_WIDTH-1:0] wMEMToWBM_2_Data;
|
wire w2MEMToWBM__Trigger;
|
wire w2MEMToWBM__Trigger;
|
wire wWBM2_MEMToWBM_DataWriteDone;
|
wire wWBM2_MEMToWBM_DataWriteDone;
|
|
|
|
|
wire w2WBM_iEnable;
|
wire w2WBM_iEnable;
|
|
|
assign w2WBM_iEnable = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM_2__Enable : iEnable;
|
assign w2WBM_iEnable = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM_2__Enable : iEnable;
|
|
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
wire wSTB_O;
|
wire wSTB_O;
|
|
|
//If the address is a pointer, we need 1 cycle to read the data back from MEM
|
//If the address is a pointer, we need 1 cycle to read the data back from MEM
|
//before we can the set the value into WBM
|
//before we can the set the value into WBM
|
wire wAddress_Set_Delayed;
|
wire wAddress_Set_Delayed;
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_SetDelay
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_SetDelay
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Enable( 1'b1 ),
|
.Enable( 1'b1 ),
|
.D( iAdr_O_Set ),
|
.D( iAdr_O_Set ),
|
.Q( wAddress_Set_Delayed )
|
.Q( wAddress_Set_Delayed )
|
|
|
);
|
);
|
|
|
//If the Addr is IMM then just set it whenever iAdr_O_Set is set, but if we have a pointer, then use
|
//If the Addr is IMM then just set it whenever iAdr_O_Set is set, but if we have a pointer, then use
|
//wAddress_Set_Delayed at the beginning and then wWBMToMEM2__Done
|
//wAddress_Set_Delayed at the beginning and then wWBMToMEM2__Done
|
wire wWBM_iAddress_Set = (iAdr_O_Type == `ADR_POINTER) ? (wAddress_Set_Delayed | wWBMToMEM2__Done) : iAdr_O_Set;
|
wire wWBM_iAddress_Set = (iAdr_O_Type == `ADR_POINTER) ? (wAddress_Set_Delayed | wWBMToMEM2__Done) : iAdr_O_Set;
|
|
|
assign STB_O = wSTB_O & ~oDone;
|
assign STB_O = wSTB_O & ~oDone;
|
|
|
WishBoneMasterUnit WBM
|
WishBoneMasterUnit WBM
|
(
|
(
|
.CLK_I( Clock ),
|
.CLK_I( Clock ),
|
.RST_I( Reset ),
|
.RST_I( Reset ),
|
.DAT_I( DAT_I ),
|
.DAT_I( DAT_I ),
|
.DAT_O( DAT_O ),
|
.DAT_O( DAT_O ),
|
.ACK_I( ACK_I ),
|
.ACK_I( ACK_I ),
|
.ADR_O( ADR_O ),
|
.ADR_O( ADR_O ),
|
.WE_O( WE_O ),
|
.WE_O( WE_O ),
|
.STB_O( wSTB_O ),
|
.STB_O( wSTB_O ),
|
.CYC_O( CYC_O ),
|
.CYC_O( CYC_O ),
|
.TGC_O( TGC_O ),
|
.TGC_O( TGC_O ),
|
.GNT_I( GNT_I ),
|
.GNT_I( GNT_I ),
|
|
|
.iEnable( w2WBM_iEnable ),
|
.iEnable( w2WBM_iEnable ),
|
.iBusCyc_Type( iBusCyc_Type ),
|
.iBusCyc_Type( iBusCyc_Type ),
|
.iAddress_Set( wWBM_iAddress_Set ),
|
.iAddress_Set( wWBM_iAddress_Set ),
|
.iAddress( wADR_O_InitialAddress ),
|
.iAddress( wADR_O_InitialAddress ),
|
.oDataReady( wWBM_2_WBMToMEM_DataAvailable ),
|
.oDataReady( wWBM_2_WBMToMEM_DataAvailable ),
|
.iData( wMEMToWBM2__ReadDataElement ),
|
.iData( wMEMToWBM2__ReadDataElement ),
|
.oData( wWBM_2_WBMToMEM_Data )
|
.oData( wWBM_2_WBMToMEM_Data )
|
);
|
);
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
WishBoneSlaveUnit WBS
|
WishBoneSlaveUnit WBS
|
(
|
(
|
|
|
.CLK_I( Clock ),
|
.CLK_I( Clock ),
|
.RST_I( Reset ),
|
.RST_I( Reset ),
|
.STB_I( STB_I ),
|
.STB_I( STB_I ),
|
.WE_I( WE_I ),
|
.WE_I( WE_I ),
|
.DAT_I( DAT_I ),
|
.DAT_I( DAT_I ),
|
.ADR_I( ADR_I ),
|
.ADR_I( ADR_I ),
|
.TGA_I( TGA_I ),
|
.TGA_I( TGA_I ),
|
.ACK_O( ACK_O ),
|
.ACK_O( ACK_O ),
|
.CYC_I( CYC_I ),
|
.CYC_I( CYC_I ),
|
.MST_I( MST_I ),
|
.MST_I( MST_I ),
|
|
|
.oDataBus( wWBSToMEM2__oDataBus ),
|
.oDataBus( wWBSToMEM2__oDataBus ),
|
.oInstructionBus( oInstructionBus ),
|
.oInstructionBus( oInstructionBus ),
|
.oDataWriteAddress( wWBSToMEM2__oDataWriteAddress ),
|
.oDataWriteAddress( wWBSToMEM2__oDataWriteAddress ),
|
.oDataWriteEnable( wWBSToMEM2__oDataWriteEnable ),
|
.oDataWriteEnable( wWBSToMEM2__oDataWriteEnable ),
|
.oInstructionWriteAddress( oInstructionWriteAddress ),
|
.oInstructionWriteAddress( oInstructionWriteAddress ),
|
.oInstructionWriteEnable( oInstructionWriteEnable )
|
.oInstructionWriteEnable( oInstructionWriteEnable )
|
|
|
|
|
|
|
);
|
);
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
|
|
endmodule
|
endmodule
|
|
|
