`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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module Module_BusArbitrer
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module Module_BusArbitrer
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire [`MAX_CORES-1:0] iRequest,
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input wire [`MAX_CORES-1:0] iRequest,
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output wire [`MAX_CORES-1:0] oGrant,
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output wire [`MAX_CORES-1:0] oGrant,
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output wire [1:0] oBusSelect
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output wire [1:0] oBusSelect
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);
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);
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wire wFFMS_connect;
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wire wFFMS_connect;
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wire wIncRR_pointer;
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wire wIncRR_pointer;
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wire[3:0] wCurrentMasterMask;
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wire[3:0] wCurrentMasterMask;
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reg[3:0] wCurrentBusMaster;
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reg[3:0] wCurrentBusMaster;
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wire wCurrentRequest;
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wire wCurrentRequest;
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//Just one requester can have the bus at a given
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//Just one requester can have the bus at a given
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//point in time, the mask makes sure this happens
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//point in time, the mask makes sure this happens
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assign oGrant[0] = iRequest[0] & wCurrentMasterMask[0];
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assign oGrant[0] = iRequest[0] & wCurrentMasterMask[0];
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assign oGrant[1] = iRequest[1] & wCurrentMasterMask[1];
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assign oGrant[1] = iRequest[1] & wCurrentMasterMask[1];
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assign oGrant[2] = iRequest[2] & wCurrentMasterMask[2];
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assign oGrant[2] = iRequest[2] & wCurrentMasterMask[2];
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assign oGrant[3] = iRequest[3] & wCurrentMasterMask[3];
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assign oGrant[3] = iRequest[3] & wCurrentMasterMask[3];
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//When a requester relinquishes the bus (by negating its [iRequest] signal),
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//When a requester relinquishes the bus (by negating its [iRequest] signal),
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//the switch is turned to the next position
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//the switch is turned to the next position
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//So while iRequest == 1 the ciruclar list will not move
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//So while iRequest == 1 the ciruclar list will not move
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (4) SHL_A
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (4) SHL_A
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Enable( ~wCurrentRequest ),
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.Enable( ~wCurrentRequest ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Initial(4'b1),
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.Initial(4'b1),
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.O( wCurrentMasterMask )
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.O( wCurrentMasterMask )
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);
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);
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assign oBusSelect = wCurrentBusMaster;
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assign oBusSelect = wCurrentBusMaster;
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUXA
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUXA
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(
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(
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.Sel(wCurrentBusMaster[1:0]),
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.Sel(wCurrentBusMaster[1:0]),
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.I1(iRequest[0]),
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.I1(iRequest[0]),
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.I2(iRequest[1]),
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.I2(iRequest[1]),
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.I3(iRequest[2]),
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.I3(iRequest[2]),
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.I4(iRequest[3]),
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.I4(iRequest[3]),
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.O1( wCurrentRequest )
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.O1( wCurrentRequest )
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);
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);
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always @ ( * )
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always @ ( * )
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begin
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begin
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case (wCurrentMasterMask)
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case (wCurrentMasterMask)
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4'b0001: wCurrentBusMaster <= 0;
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4'b0001: wCurrentBusMaster <= 0;
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4'b0010: wCurrentBusMaster <= 1;
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4'b0010: wCurrentBusMaster <= 1;
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4'b0100: wCurrentBusMaster <= 2;
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4'b0100: wCurrentBusMaster <= 2;
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4'b1000: wCurrentBusMaster <= 3;
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4'b1000: wCurrentBusMaster <= 3;
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default: wCurrentBusMaster <= 0;
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default: wCurrentBusMaster <= 0;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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