`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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module THEIA
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module THEIA
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(
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(
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input wire CLK_I, //Input clock
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input wire CLK_I, //Input clock
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input wire RST_I, //Input reset
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input wire RST_I, //Input reset
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//Theia Interfaces
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//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//when this gets asserted (see documentation)
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//Wish Bone Interface
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//Wish Bone Interface
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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input wire ACK_I, //Input ack
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input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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output wire ACK_O, //Output ack
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output wire [`WB_WIDTH-1:0] ADR_O, //Output address
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output wire [`WB_WIDTH-1:0] ADR_O, //Output address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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output wire WE_O, //Output write enable
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output wire WE_O, //Output write enable
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input wire WE_I, //Input write enable
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input wire WE_I, //Input write enable
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output wire STB_O, //Strobe signal, see wishbone documentation
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output wire STB_O, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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output wire CYC_O, //Bus cycle signal, see wishbone documentation
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output wire CYC_O, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] RENDREN_I,
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input wire [`MAX_CORES-1:0] RENDREN_I,
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//Control Register
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//Control Register
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input wire [15:0] CREG_I,
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input wire [15:0] CREG_I,
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output wire DONE_O
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output wire DONE_O
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);
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);
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wire [`MAX_CORES-1:0] wDone;
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wire [`MAX_CORES-1:0] wDone;
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wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
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wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
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wire [`WB_WIDTH-1:0] wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
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wire [`WB_WIDTH-1:0] wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
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wire [`WB_WIDTH-1:0] wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
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wire [`WB_WIDTH-1:0] wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
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wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;
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wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;
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wire [1:0] wBusSelect;
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wire [1:0] wBusSelect;
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//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
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//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
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//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
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//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O,wACK_O;
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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//assign DONE_O = wDone[0];
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//assign DONE_O = wDone[0];
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//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];
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//assign DONE_O = wDone[0] & wDone[1];// & wDone[2];
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// assign wDone[3:1] = 3'b111;
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// assign wDone[3:1] = 3'b111;
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// assign wBusRequest[3:2] = 0;
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// assign wBusRequest[3:2] = 0;
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// assign wSTB_O[3:2] = 0;
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// assign wSTB_O[3:2] = 0;
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// assign wWE_O[3:2] = 0;
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// assign wWE_O[3:2] = 0;
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Module_BusArbitrer ARB1
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Module_BusArbitrer ARB1
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.Reset( RST_I ),
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.iRequest( wBusRequest ),
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.iRequest( wBusRequest ),
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.oGrant( wBusGranted ),
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.oGrant( wBusGranted ),
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.oBusSelect( wBusSelect )
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.oBusSelect( wBusSelect )
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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//The Muxes
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//The Muxes
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//DAT_O Mux
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//DAT_O Mux
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
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(
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(
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.Sel(wBusSelect),
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.Sel(wBusSelect),
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.I1(wDAT_O_0),
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.I1(wDAT_O_0),
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.I2(wDAT_O_1),
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.I2(wDAT_O_1),
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.I3(wDAT_O_2),
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.I3(wDAT_O_2),
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.I4(wDAT_O_3),
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.I4(wDAT_O_3),
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.O1( DAT_O )
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.O1( DAT_O )
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);
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);
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
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(
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(
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.Sel(wBusSelect),
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.Sel(wBusSelect),
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.I1(wADR_O_0),
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.I1(wADR_O_0),
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.I2(wADR_O_1),
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.I2(wADR_O_1),
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.I3(wADR_O_2),
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.I3(wADR_O_2),
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.I4(wADR_O_3),
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.I4(wADR_O_3),
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.O1( ADR_O )
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.O1( ADR_O )
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);
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);
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O
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(
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(
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.Sel(wBusSelect),
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.Sel(wBusSelect),
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.I1(wSTB_O[0]),
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.I1(wSTB_O[0]),
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.I2(wSTB_O[1]),
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.I2(wSTB_O[1]),
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.I3(wSTB_O[2]),
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.I3(wSTB_O[2]),
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.I4(wSTB_O[3]),
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.I4(wSTB_O[3]),
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.O1( STB_O )
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.O1( STB_O )
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);
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);
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O
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(
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(
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.Sel(wBusSelect),
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.Sel(wBusSelect),
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.I1(wWE_O[0]),
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.I1(wWE_O[0]),
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.I2(wWE_O[1]),
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.I2(wWE_O[1]),
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.I3(wWE_O[2]),
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.I3(wWE_O[2]),
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.I4(wWE_O[3]),
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.I4(wWE_O[3]),
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.O1( WE_O )
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.O1( WE_O )
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);
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);
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MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O
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MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O
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(
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(
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.Sel(wBusSelect),
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.Sel(wBusSelect),
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.I1(wTGA_O_0),
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.I1(wTGA_O_0),
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.I2(wTGA_O_1),
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.I2(wTGA_O_1),
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.I3(wTGA_O_2),
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.I3(wTGA_O_2),
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.I4(wTGA_O_3),
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.I4(wTGA_O_3),
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.O1( TGA_O )
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.O1( TGA_O )
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);
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);
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assign ACK_O = (wACK_O[0] | wACK_O[1] | wACK_O[2] | wACK_O[3]);
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assign ACK_O = (wACK_O[0] | wACK_O[1] | wACK_O[2] | wACK_O[3]);
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;
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assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;
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assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;
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assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;
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assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;
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assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;
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assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;
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assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;
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assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;
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assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;
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assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;
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assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;
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assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;
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assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;
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assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;
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assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;
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assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;
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assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;
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assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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THEIACORE THEIA_CORE0
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THEIACORE THEIA_CORE0
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(
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(
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.CLK_I( CLK_I ),
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[0] ),
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.RENDREN_I( RENDREN_I[0] ),
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//Slave signals
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//Slave signals
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.ADR_I( ADR_I ),
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[0] ),
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.STB_I( wSTB_I[0] ),
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//-----------------------------------
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//-----------------------------------
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//This signal behaves in a very funny way...
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//This signal behaves in a very funny way...
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//
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//
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.ACK_I( ACK_I ),
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.ACK_I( ACK_I ),
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//-----------------------------------
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//-----------------------------------
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.CYC_I( wCYC_I[0] ),
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.CYC_I( wCYC_I[0] ),
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.MST_I( wMST_I[0] ),
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.MST_I( wMST_I[0] ),
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.TGA_I( wTGA_I[0] ),
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.TGA_I( wTGA_I[0] ),
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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//Master Signals
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//Master Signals
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.WE_O ( wWE_O[0] ),
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.WE_O ( wWE_O[0] ),
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.STB_O( wSTB_O[0] ),
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.STB_O( wSTB_O[0] ),
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.ACK_O( wACK_O[0] ),
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.ACK_O( wACK_O[0] ),
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.DAT_O( wDAT_O_0 ),
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.DAT_O( wDAT_O_0 ),
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.ADR_O( wADR_O_0 ),
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.ADR_O( wADR_O_0 ),
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.CYC_O( wBusRequest[0] ),
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.CYC_O( wBusRequest[0] ),
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.GNT_I( wBusGranted[0] ),
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.GNT_I( wBusGranted[0] ),
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.TGA_O( wTGA_O_0 ),
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.TGA_O( wTGA_O_0 ),
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`ifdef DEBUG
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`ifdef DEBUG
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.iDebug_CoreID( `MAX_CORES'd0 ),
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.iDebug_CoreID( `MAX_CORES'd0 ),
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`endif
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`endif
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//Other
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//Other
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.DAT_I( DAT_I ),
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.DAT_I( DAT_I ),
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.DONE_O( wDone[0] )
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.DONE_O( wDone[0] )
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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THEIACORE THEIA_CORE1
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THEIACORE THEIA_CORE1
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(
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(
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.CLK_I( CLK_I ),
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[1] ),
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.RENDREN_I( RENDREN_I[1] ),
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//Slave signals
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//Slave signals
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.ADR_I( ADR_I ),
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[1] ),//ok
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.STB_I( wSTB_I[1] ),//ok
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.ACK_I( ACK_I ),
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[1] ),//ok
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.CYC_I( wCYC_I[1] ),//ok
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.MST_I( wMST_I[1] ),//ok
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.MST_I( wMST_I[1] ),//ok
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.TGA_I( wTGA_I[1] ),//ok
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.TGA_I( wTGA_I[1] ),//ok
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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//Master Signals
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//Master Signals
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.WE_O ( wWE_O[1] ),
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.WE_O ( wWE_O[1] ),
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.STB_O( wSTB_O[1] ),
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.STB_O( wSTB_O[1] ),
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.ACK_O( wACK_O[1] ),
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.ACK_O( wACK_O[1] ),
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.DAT_O( wDAT_O_1 ),
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.DAT_O( wDAT_O_1 ),
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.ADR_O( wADR_O_1 ),
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.ADR_O( wADR_O_1 ),
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.CYC_O( wBusRequest[1] ),
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.CYC_O( wBusRequest[1] ),
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.GNT_I( wBusGranted[1] ),
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.GNT_I( wBusGranted[1] ),
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.TGA_O( wTGA_O_1 ),
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.TGA_O( wTGA_O_1 ),
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`ifdef DEBUG
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`ifdef DEBUG
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.iDebug_CoreID( `MAX_CORES'd1 ),
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.iDebug_CoreID( `MAX_CORES'd1 ),
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`endif
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`endif
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//Other
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//Other
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.DAT_I( DAT_I ),
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.DAT_I( DAT_I ),
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.DONE_O( wDone[1] )
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.DONE_O( wDone[1] )
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|
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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THEIACORE THEIA_CORE2
|
THEIACORE THEIA_CORE2
|
(
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(
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.CLK_I( CLK_I ),
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[2] ),
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.RENDREN_I( RENDREN_I[2] ),
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|
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//Slave signals
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//Slave signals
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.ADR_I( ADR_I ),
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[2] ),
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.STB_I( wSTB_I[2] ),
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.ACK_I( ACK_I ),
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[2] ),
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.CYC_I( wCYC_I[2] ),
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.MST_I( wMST_I[2] ),
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.MST_I( wMST_I[2] ),
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.TGA_I( wTGA_I[2] ),
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.TGA_I( wTGA_I[2] ),
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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|
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//Master Signals
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//Master Signals
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.WE_O ( wWE_O[2] ),
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.WE_O ( wWE_O[2] ),
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.STB_O( wSTB_O[2] ),
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.STB_O( wSTB_O[2] ),
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.ACK_O( wACK_O[2] ),
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.ACK_O( wACK_O[2] ),
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.DAT_O( wDAT_O_2 ),
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.DAT_O( wDAT_O_2 ),
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.ADR_O( wADR_O_2 ),
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.ADR_O( wADR_O_2 ),
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.CYC_O( wBusRequest[2] ),
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.CYC_O( wBusRequest[2] ),
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.GNT_I( wBusGranted[2] ),
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.GNT_I( wBusGranted[2] ),
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.TGA_O( wTGA_O_2 ),
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.TGA_O( wTGA_O_2 ),
|
`ifdef DEBUG
|
`ifdef DEBUG
|
.iDebug_CoreID( `MAX_CORES'd2 ),
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.iDebug_CoreID( `MAX_CORES'd2 ),
|
`endif
|
`endif
|
//Other
|
//Other
|
.DAT_I( DAT_I ),
|
.DAT_I( DAT_I ),
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.DONE_O( wDone[2] )
|
.DONE_O( wDone[2] )
|
|
|
);
|
);
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
THEIACORE THEIA_CORE3
|
THEIACORE THEIA_CORE3
|
(
|
(
|
.CLK_I( CLK_I ),
|
.CLK_I( CLK_I ),
|
.RST_I( RST_I ),
|
.RST_I( RST_I ),
|
.RENDREN_I( RENDREN_I[3] ),
|
.RENDREN_I( RENDREN_I[3] ),
|
|
|
//Slave signals
|
//Slave signals
|
.ADR_I( ADR_I ),
|
.ADR_I( ADR_I ),
|
.WE_I( WE_I ),
|
.WE_I( WE_I ),
|
.STB_I( wSTB_I[3] ),
|
.STB_I( wSTB_I[3] ),
|
.ACK_I( ACK_I ),
|
.ACK_I( ACK_I ),
|
.CYC_I( wCYC_I[3] ),
|
.CYC_I( wCYC_I[3] ),
|
.MST_I( wMST_I[3] ),
|
.MST_I( wMST_I[3] ),
|
.TGA_I( wTGA_I[3] ),
|
.TGA_I( wTGA_I[3] ),
|
.CREG_I( CREG_I ),
|
.CREG_I( CREG_I ),
|
|
|
//Master Signals
|
//Master Signals
|
.WE_O ( wWE_O[3] ),
|
.WE_O ( wWE_O[3] ),
|
.STB_O( wSTB_O[3] ),
|
.STB_O( wSTB_O[3] ),
|
.ACK_O( wACK_O[3] ),
|
.ACK_O( wACK_O[3] ),
|
.DAT_O( wDAT_O_3 ),
|
.DAT_O( wDAT_O_3 ),
|
.ADR_O( wADR_O_3 ),
|
.ADR_O( wADR_O_3 ),
|
.CYC_O( wBusRequest[3] ),
|
.CYC_O( wBusRequest[3] ),
|
.GNT_I( wBusGranted[3] ),
|
.GNT_I( wBusGranted[3] ),
|
.TGA_O( wTGA_O_3 ),
|
.TGA_O( wTGA_O_3 ),
|
`ifdef DEBUG
|
`ifdef DEBUG
|
.iDebug_CoreID( `MAX_CORES'd3 ),
|
.iDebug_CoreID( `MAX_CORES'd3 ),
|
`endif
|
`endif
|
//Other
|
//Other
|
.DAT_I( DAT_I ),
|
.DAT_I( DAT_I ),
|
.DONE_O( wDone[3] )
|
.DONE_O( wDone[3] )
|
|
|
);
|
);
|
//----------------------------------------------------------------
|
//----------------------------------------------------------------
|
endmodule
|
endmodule
|
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
|
|
