`ifndef COLLATERALS_V
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`ifndef COLLATERALS_V
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`define COLLATERALS_V
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`define COLLATERALS_V
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|
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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|
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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|
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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|
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***********************************************************************************/
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***********************************************************************************/
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|
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//----------------------------------------------------
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//----------------------------------------------------
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module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
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module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
|
(
|
(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
|
input wire Enable,
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input wire Enable,
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input wire [SIZE-1:0] D,
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input wire [SIZE-1:0] D,
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output reg [SIZE-1:0] Q
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output reg [SIZE-1:0] Q
|
);
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);
|
|
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
begin
|
begin
|
if ( Reset )
|
if ( Reset )
|
Q <= {SIZE{1'b0}};
|
Q <= {SIZE{1'b0}};
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
Q <= D;
|
Q <= D;
|
end
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end
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|
|
end//always
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end//always
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|
|
endmodule
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endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module PULSE
|
module PULSE
|
(
|
(
|
input wire Clock,
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input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire Enable,
|
input wire Enable,
|
input wire D,
|
input wire D,
|
output wire Q
|
output wire Q
|
);
|
);
|
|
|
wire wDelay;
|
wire wDelay;
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
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FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
|
|
|
assign Q = (Enable) ? (D ^ wDelay) & D: 1'b0;
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assign Q = (Enable) ? (D ^ wDelay) & D: 1'b0;
|
|
|
endmodule
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endmodule
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//------------------------------------------------
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//------------------------------------------------
|
module ADDER # (parameter SIZE=`WIDTH)
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module ADDER # (parameter SIZE=`WIDTH)
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(
|
(
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input wire Clock,
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input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iTrigger,
|
input wire iTrigger,
|
input wire [SIZE-1:0] iA,iB,
|
input wire [SIZE-1:0] iA,iB,
|
output wire [SIZE-1:0] oR,
|
output wire [SIZE-1:0] oR,
|
output wire oDone
|
output wire oDone
|
);
|
);
|
wire [SIZE-1:0] wR,wR_Delay;
|
wire [SIZE-1:0] wR,wR_Delay;
|
assign wR = iA + iB;
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assign wR = iA + iB;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
assign oR = wR_Delay;
|
assign oR = wR_Delay;
|
|
|
endmodule
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endmodule
|
//------------------------------------------------
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//------------------------------------------------
|
module OR # (parameter SIZE=`WIDTH)
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module OR # (parameter SIZE=`WIDTH)
|
(
|
(
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input wire Clock,
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input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iTrigger,
|
input wire iTrigger,
|
input wire [SIZE-1:0] iA,iB,
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input wire [SIZE-1:0] iA,iB,
|
output wire [SIZE-1:0] oR,
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output wire [SIZE-1:0] oR,
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output wire oDone
|
output wire oDone
|
);
|
);
|
wire [SIZE-1:0] wR,wR_Delay;
|
wire [SIZE-1:0] wR,wR_Delay;
|
assign wR = iA | iB;
|
assign wR = iA | iB;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
assign oR = wR_Delay;
|
assign oR = wR_Delay;
|
|
|
endmodule
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endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module AND # (parameter SIZE=`WIDTH)
|
module AND # (parameter SIZE=`WIDTH)
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iTrigger,
|
input wire iTrigger,
|
input wire [SIZE-1:0] iA,iB,
|
input wire [SIZE-1:0] iA,iB,
|
output wire [SIZE-1:0] oR,
|
output wire [SIZE-1:0] oR,
|
output wire oDone
|
output wire oDone
|
);
|
);
|
wire [SIZE-1:0] wR,wR_Delay;
|
wire [SIZE-1:0] wR,wR_Delay;
|
assign wR = iA & iB;
|
assign wR = iA & iB;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
|
assign oR = wR_Delay;
|
assign oR = wR_Delay;
|
|
|
endmodule
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endmodule
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//------------------------------------------------
|
//------------------------------------------------
|
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
|
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
|
(
|
(
|
input wire Clock, Reset,
|
input wire Clock, Reset,
|
input wire [SIZE-1:0] Initial,
|
input wire [SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output reg [SIZE-1:0] Q
|
output reg [SIZE-1:0] Q
|
);
|
);
|
|
|
|
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Q <= Initial;
|
Q <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
Q <= Q + 1;
|
Q <= Q + 1;
|
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
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endmodule
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
module DECODER_ONEHOT_2_BINARY
|
|
|
module DECODER_ONEHOT_2_BINARY # (parameter OUTPUT_WIDTH = 6)
|
(
|
(
|
input wire [5:0] iIn,
|
input wire [6:0] iIn,
|
output reg[5:0] oOut
|
output reg[OUTPUT_WIDTH-1:0] oOut
|
);
|
);
|
|
|
always @ (*)
|
always @ (*)
|
begin
|
begin
|
case (iIn)
|
case (iIn)
|
6'b000000: oOut = 0;
|
7'b0000000: oOut = 0;
|
6'b000001: oOut = 1;
|
7'b0000001: oOut = 1;
|
6'b000010: oOut = 2;
|
7'b0000010: oOut = 2;
|
6'b000100: oOut = 3;
|
7'b0000100: oOut = 3;
|
6'b001000: oOut = 4;
|
7'b0001000: oOut = 4;
|
6'b010000: oOut = 5;
|
7'b0010000: oOut = 5;
|
6'b100000: oOut = 6;
|
7'b0100000: oOut = 6;
|
|
7'b1000000: oOut = 7;
|
default:
|
default:
|
oOut = 0;
|
oOut = 0;
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
|
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
|
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
|
(
|
(
|
input wire [SEL_WIDTH-1:0] Sel,
|
input wire [SEL_WIDTH-1:0] Sel,
|
input wire En,
|
input wire En,
|
output wire [OUTPUT_WIDTH-1:0] O
|
output wire [OUTPUT_WIDTH-1:0] O
|
);
|
);
|
|
|
reg[OUTPUT_WIDTH-1:0] shift;
|
reg[OUTPUT_WIDTH-1:0] shift;
|
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
if (~En)
|
if (~En)
|
shift = 1;
|
shift = 1;
|
else
|
else
|
shift = (1 << Sel);
|
shift = (1 << Sel);
|
|
|
|
|
end
|
end
|
|
|
assign O = ( ~En ) ? 0 : shift ;
|
assign O = ( ~En ) ? 0 : shift ;
|
|
|
//assign O = En & (1 << Sel);
|
//assign O = En & (1 << Sel);
|
|
|
endmodule
|
endmodule
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
|
module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
|
(
|
(
|
|
|
input wire [(CHANNELS*WIDTH)-1:0] in_bus,
|
input wire [(CHANNELS*WIDTH)-1:0] in_bus,
|
input wire [SELBITS-1:0] sel,
|
input wire [SELBITS-1:0] sel,
|
|
|
output wire [WIDTH-1:0] out
|
output wire [WIDTH-1:0] out
|
);
|
);
|
|
|
genvar ig;
|
genvar ig;
|
|
|
wire [WIDTH-1:0] input_array [0:CHANNELS-1];
|
wire [WIDTH-1:0] input_array [0:CHANNELS-1];
|
|
|
assign out = input_array[sel];
|
assign out = input_array[sel];
|
|
|
generate
|
generate
|
for(ig=0; ig<CHANNELS; ig=ig+1)
|
for(ig=0; ig<CHANNELS; ig=ig+1)
|
begin: array_assignments
|
begin: array_assignments
|
assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
|
assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
endmodule
|
endmodule
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [1:0] Sel,
|
input wire [1:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,I4,
|
input wire [SIZE-1:0]I1, I2, I3,I4,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
2'b00: O1 = I1;
|
2'b00: O1 = I1;
|
2'b01: O1 = I2;
|
2'b01: O1 = I2;
|
2'b10: O1 = I3;
|
2'b10: O1 = I3;
|
2'b11: O1 = I4;
|
2'b11: O1 = I4;
|
default: O1 = SIZE;
|
default: O1 = SIZE;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
module MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [2:0] Sel,
|
input wire [2:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,I4,I5,I6,I7,I8,
|
input wire [SIZE-1:0]I1, I2, I3,I4,I5,I6,I7,I8,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
3'b000: O1 = I1;
|
3'b000: O1 = I1;
|
3'b001: O1 = I2;
|
3'b001: O1 = I2;
|
3'b010: O1 = I3;
|
3'b010: O1 = I3;
|
3'b011: O1 = I4;
|
3'b011: O1 = I4;
|
3'b100: O1 = I5;
|
3'b100: O1 = I5;
|
3'b101: O1 = I6;
|
3'b101: O1 = I6;
|
3'b110: O1 = I7;
|
3'b110: O1 = I7;
|
3'b111: O1 = I8;
|
3'b111: O1 = I8;
|
default: O1 = SIZE;
|
default: O1 = SIZE;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
|
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
begin
|
begin
|
if (tmp[SIZE-1])
|
if (tmp[SIZE-1])
|
begin
|
begin
|
tmp <= Initial;
|
tmp <= Initial;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [2:0] Sel,
|
input wire [2:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
3'b001: O1 = I1;
|
3'b001: O1 = I1;
|
3'b010: O1 = I2;
|
3'b010: O1 = I2;
|
3'b100: O1 = I3;
|
3'b100: O1 = I3;
|
default: O1 = SIZE;
|
default: O1 = SIZE;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_3SEL_EN # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_3SEL_EN # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [1:0] SEL,
|
input wire [1:0] SEL,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire EN,
|
input wire EN,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
if (EN)
|
if (EN)
|
begin
|
begin
|
case (SEL)
|
case (SEL)
|
|
|
2'b00: O1 = I1;
|
2'b00: O1 = I1;
|
2'b01: O1 = I2;
|
2'b01: O1 = I2;
|
2'b10: O1 = I3;
|
2'b10: O1 = I3;
|
default: O1 = SIZE;
|
default: O1 = SIZE;
|
|
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
begin
|
begin
|
O1 = I1;
|
O1 = I1;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_4SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_4SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [2:0] Sel,
|
input wire [2:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3, I4,
|
input wire [SIZE-1:0]I1, I2, I3, I4,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
4'b0001: O1 = I1;
|
4'b0001: O1 = I1;
|
4'b0010: O1 = I2;
|
4'b0010: O1 = I2;
|
4'b0100: O1 = I3;
|
4'b0100: O1 = I3;
|
4'b1000: O1 = I4;
|
4'b1000: O1 = I4;
|
default: O1 = SIZE;
|
default: O1 = SIZE;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
//------------------------------------------------
|
//------------------------------------------------
|
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset || tmp[SIZE-1])
|
if (Reset || tmp[SIZE-1])
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
/*
|
/*
|
Sorry forgot how this flop is called.
|
Sorry forgot how this flop is called.
|
Any way Truth table is this
|
Any way Truth table is this
|
|
|
Q S Q_next R
|
Q S Q_next R
|
0 0 0 0
|
0 0 0 0
|
0 1 1 0
|
0 1 1 0
|
1 0 1 0
|
1 0 1 0
|
1 1 1 0
|
1 1 1 0
|
X X 0 1
|
X X 0 1
|
|
|
The idea is that it toggles from 0 to 1 when S = 1, but if it
|
The idea is that it toggles from 0 to 1 when S = 1, but if it
|
gets another S = 1, it keeps the output to 1.
|
gets another S = 1, it keeps the output to 1.
|
*/
|
*/
|
module FFToggleOnce_1Bit
|
module FFToggleOnce_1Bit
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire Enable,
|
input wire Enable,
|
input wire S,
|
input wire S,
|
output reg Q
|
output reg Q
|
|
|
);
|
);
|
|
|
|
|
reg Q_next;
|
reg Q_next;
|
|
|
always @ (negedge Clock)
|
always @ (negedge Clock)
|
begin
|
begin
|
Q <= Q_next;
|
Q <= Q_next;
|
end
|
end
|
|
|
always @ ( posedge Clock )
|
always @ ( posedge Clock )
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Q_next <= 0;
|
Q_next <= 0;
|
else if (Enable)
|
else if (Enable)
|
Q_next <= (S && !Q) || Q;
|
Q_next <= (S && !Q) || Q;
|
else
|
else
|
Q_next <= Q;
|
Q_next <= Q;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
|
|
module FFD32_POSEDGE
|
module FFD32_POSEDGE
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire[31:0] D,
|
input wire[31:0] D,
|
output reg[31:0] Q
|
output reg[31:0] Q
|
);
|
);
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
Q <= D;
|
Q <= D;
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_96bits_2SEL
|
module MUXFULLPARALELL_96bits_2SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire [95:0]I1, I2,
|
input wire [95:0]I1, I2,
|
output reg [95:0] O1
|
output reg [95:0] O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
1'b0: O1 = I1;
|
1'b0: O1 = I1;
|
1'b1: O1 = I2;
|
1'b1: O1 = I2;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_16bits_2SEL
|
module MUXFULLPARALELL_16bits_2SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire [15:0]I1, I2,
|
input wire [15:0]I1, I2,
|
output reg [15:0] O1
|
output reg [15:0] O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
1'b0: O1 = I1;
|
1'b0: O1 = I1;
|
1'b1: O1 = I2;
|
1'b1: O1 = I2;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
module FFT1
|
module FFT1
|
(
|
(
|
input wire D,
|
input wire D,
|
input wire Clock,
|
input wire Clock,
|
input wire Reset ,
|
input wire Reset ,
|
output reg Q
|
output reg Q
|
);
|
);
|
|
|
always @ ( posedge Clock or posedge Reset )
|
always @ ( posedge Clock or posedge Reset )
|
begin
|
begin
|
|
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Q <= 1'b0;
|
Q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (D)
|
if (D)
|
Q <= ! Q;
|
Q <= ! Q;
|
end
|
end
|
|
|
end//always
|
end//always
|
|
|
endmodule
|
endmodule
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
/*
|
/*
|
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
|
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
wr_cs , // Write chip select
|
wr_cs , // Write chip select
|
rd_cs , // Read chipe select
|
rd_cs , // Read chipe select
|
input wire iData,
|
input wire iData,
|
input wire iReadEnable,
|
input wire iReadEnable,
|
input wire[SIZE-1:0] iWriteEnable,
|
input wire[SIZE-1:0] iWriteEnable,
|
output reg[SIZE-1:0] oData,
|
output reg[SIZE-1:0] oData,
|
output wire oEmpy,
|
output wire oEmpy,
|
output wire oFull
|
output wire oFull
|
);
|
);
|
|
|
// FIFO constants
|
// FIFO constants
|
parameter DATA_WIDTH = 8;
|
parameter DATA_WIDTH = 8;
|
parameter ADDR_WIDTH = 8;
|
parameter ADDR_WIDTH = 8;
|
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
|
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
|
// Port Declarations
|
// Port Declarations
|
input clk ;
|
input clk ;
|
input rst ;
|
input rst ;
|
input wr_cs ;
|
input wr_cs ;
|
input rd_cs ;
|
input rd_cs ;
|
input rd_en ;
|
input rd_en ;
|
input wr_en ;
|
input wr_en ;
|
input [DATA_WIDTH-1:0] data_in ;
|
input [DATA_WIDTH-1:0] data_in ;
|
output full ;
|
output full ;
|
output empty ;
|
output empty ;
|
output [DATA_WIDTH-1:0] data_out ;
|
output [DATA_WIDTH-1:0] data_out ;
|
|
|
//-----------Internal variables-------------------
|
//-----------Internal variables-------------------
|
reg [ADDR_WIDTH-1:0] wr_pointer;
|
reg [ADDR_WIDTH-1:0] wr_pointer;
|
reg [ADDR_WIDTH-1:0] rd_pointer;
|
reg [ADDR_WIDTH-1:0] rd_pointer;
|
reg [ADDR_WIDTH :0] status_cnt;
|
reg [ADDR_WIDTH :0] status_cnt;
|
reg [DATA_WIDTH-1:0] data_out ;
|
reg [DATA_WIDTH-1:0] data_out ;
|
wire [DATA_WIDTH-1:0] data_ram ;
|
wire [DATA_WIDTH-1:0] data_ram ;
|
|
|
//-----------Variable assignments---------------
|
//-----------Variable assignments---------------
|
assign full = (status_cnt == (RAM_DEPTH-1));
|
assign full = (status_cnt == (RAM_DEPTH-1));
|
assign empty = (status_cnt == 0);
|
assign empty = (status_cnt == 0);
|
|
|
//-----------Code Start---------------------------
|
//-----------Code Start---------------------------
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin : WRITE_POINTER
|
begin : WRITE_POINTER
|
if (rst) begin
|
if (rst) begin
|
wr_pointer <= 0;
|
wr_pointer <= 0;
|
end else if (wr_cs && wr_en ) begin
|
end else if (wr_cs && wr_en ) begin
|
wr_pointer <= wr_pointer + 1;
|
wr_pointer <= wr_pointer + 1;
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin : READ_POINTER
|
begin : READ_POINTER
|
if (rst) begin
|
if (rst) begin
|
rd_pointer <= 0;
|
rd_pointer <= 0;
|
end else if (rd_cs && rd_en ) begin
|
end else if (rd_cs && rd_en ) begin
|
rd_pointer <= rd_pointer + 1;
|
rd_pointer <= rd_pointer + 1;
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin : READ_DATA
|
begin : READ_DATA
|
if (rst) begin
|
if (rst) begin
|
data_out <= 0;
|
data_out <= 0;
|
end else if (rd_cs && rd_en ) begin
|
end else if (rd_cs && rd_en ) begin
|
data_out <= data_ram;
|
data_out <= data_ram;
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin : STATUS_COUNTER
|
begin : STATUS_COUNTER
|
if (rst) begin
|
if (rst) begin
|
status_cnt <= 0;
|
status_cnt <= 0;
|
// Read but no write.
|
// Read but no write.
|
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
|
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
|
&& (status_cnt != 0)) begin
|
&& (status_cnt != 0)) begin
|
status_cnt <= status_cnt - 1;
|
status_cnt <= status_cnt - 1;
|
// Write but no read.
|
// Write but no read.
|
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
|
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
|
&& (status_cnt != RAM_DEPTH)) begin
|
&& (status_cnt != RAM_DEPTH)) begin
|
status_cnt <= status_cnt + 1;
|
status_cnt <= status_cnt + 1;
|
end
|
end
|
end
|
end
|
|
|
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
|
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
|
.address_0 (wr_pointer) , // address_0 input
|
.address_0 (wr_pointer) , // address_0 input
|
.data_0 (data_in) , // data_0 bi-directional
|
.data_0 (data_in) , // data_0 bi-directional
|
.cs_0 (wr_cs) , // chip select
|
.cs_0 (wr_cs) , // chip select
|
.we_0 (wr_en) , // write enable
|
.we_0 (wr_en) , // write enable
|
.oe_0 (1'b0) , // output enable
|
.oe_0 (1'b0) , // output enable
|
.address_1 (rd_pointer) , // address_q input
|
.address_1 (rd_pointer) , // address_q input
|
.data_1 (data_ram) , // data_1 bi-directional
|
.data_1 (data_ram) , // data_1 bi-directional
|
.cs_1 (rd_cs) , // chip select
|
.cs_1 (rd_cs) , // chip select
|
.we_1 (1'b0) , // Read enable
|
.we_1 (1'b0) , // Read enable
|
.oe_1 (rd_en) // output enable
|
.oe_1 (rd_en) // output enable
|
);
|
);
|
|
|
endmodule
|
endmodule
|
*/
|
*/
|
|
|
|
|
module sync_fifo #( parameter DATA_WIDTH = 8, parameter DEPTH = 8 )
|
module sync_fifo #( parameter DATA_WIDTH = 8, parameter DEPTH = 8 )
|
(
|
(
|
|
|
input wire [DATA_WIDTH-1:0] din,
|
input wire [DATA_WIDTH-1:0] din,
|
input wire wr_en,
|
input wire wr_en,
|
input wire rd_en,
|
input wire rd_en,
|
output wire[DATA_WIDTH-1:0] dout,
|
output wire[DATA_WIDTH-1:0] dout,
|
output reg full,
|
output reg full,
|
output reg empty,
|
output reg empty,
|
input wire clk,
|
input wire clk,
|
input wire reset
|
input wire reset
|
|
|
);
|
);
|
|
|
|
|
parameter ADDR_WIDTH = $clog2(DEPTH);
|
parameter ADDR_WIDTH = $clog2(DEPTH);
|
|
|
reg [ADDR_WIDTH : 0] rd_ptr; // note MSB is not really address
|
reg [ADDR_WIDTH : 0] rd_ptr; // note MSB is not really address
|
reg [ADDR_WIDTH : 0] wr_ptr; // note MSB is not really address
|
reg [ADDR_WIDTH : 0] wr_ptr; // note MSB is not really address
|
wire [ADDR_WIDTH-1 : 0] wr_loc;
|
wire [ADDR_WIDTH-1 : 0] wr_loc;
|
wire [ADDR_WIDTH-1 : 0] rd_loc;
|
wire [ADDR_WIDTH-1 : 0] rd_loc;
|
reg [DATA_WIDTH-1 : 0] mem[DEPTH-1 : 0];
|
reg [DATA_WIDTH-1 : 0] mem[DEPTH-1 : 0];
|
|
|
|
|
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
|
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
|
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
|
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
if(reset) begin
|
if(reset) begin
|
wr_ptr <= 'h0;
|
wr_ptr <= 'h0;
|
rd_ptr <= 'h0;
|
rd_ptr <= 'h0;
|
end // end if
|
end // end if
|
|
|
else begin
|
else begin
|
if(wr_en & (~full))begin
|
if(wr_en & (~full))begin
|
wr_ptr <= wr_ptr+1;
|
wr_ptr <= wr_ptr+1;
|
end
|
end
|
if(rd_en & (~empty))
|
if(rd_en & (~empty))
|
rd_ptr <= rd_ptr+1;
|
rd_ptr <= rd_ptr+1;
|
end //end else
|
end //end else
|
|
|
end//end always
|
end//end always
|
|
|
|
|
|
|
//empty if all the bits of rd_ptr and wr_ptr are the same.
|
//empty if all the bits of rd_ptr and wr_ptr are the same.
|
|
|
//full if all bits except the MSB are equal and MSB differes
|
//full if all bits except the MSB are equal and MSB differes
|
|
|
always @(rd_ptr or wr_ptr)begin
|
always @(rd_ptr or wr_ptr)begin
|
|
|
//default catch-alls
|
//default catch-alls
|
|
|
empty <= 1'b0;
|
empty <= 1'b0;
|
|
|
full <= 1'b0;
|
full <= 1'b0;
|
|
|
if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
|
if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
|
|
|
if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
|
if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
|
|
|
empty <= 1'b1;
|
empty <= 1'b1;
|
|
|
else
|
else
|
|
|
full <= 1'b1;
|
full <= 1'b1;
|
|
|
end//end if
|
end//end if
|
|
|
end//end always
|
end//end always
|
|
|
|
|
|
|
always @(posedge clk) begin
|
always @(posedge clk) begin
|
|
|
if (wr_en)
|
if (wr_en)
|
|
|
mem[wr_loc] <= din;
|
mem[wr_loc] <= din;
|
|
|
end //end always
|
end //end always
|
|
|
assign dout = mem[rd_loc];//rd_en ? mem[rd_loc]:'h0;
|
assign dout = mem[rd_loc];//rd_en ? mem[rd_loc]:'h0;
|
|
|
endmodule
|
endmodule
|
|
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
|
|
/*
|
/*
|
Synchronous memory blocks have two independent address ports, allowing
|
Synchronous memory blocks have two independent address ports, allowing
|
for operations on two unique addresses simultaneously. A read operation and a write
|
for operations on two unique addresses simultaneously. A read operation and a write
|
operation can share the same port if they share the same address.
|
operation can share the same port if they share the same address.
|
In the synchronous RAM block architecture, there is no priority between the two
|
In the synchronous RAM block architecture, there is no priority between the two
|
ports. Therefore, if you write to the same location on both ports at the same time, the
|
ports. Therefore, if you write to the same location on both ports at the same time, the
|
result is indeterminate in the device architecture.
|
result is indeterminate in the device architecture.
|
When a read and write operation occurs on the same port for
|
When a read and write operation occurs on the same port for
|
the same address, the new data being written to the memory is read. When a read and
|
the same address, the new data being written to the memory is read. When a read and
|
write operation occurs on different ports for the same address, the old data in the
|
write operation occurs on different ports for the same address, the old data in the
|
memory is read. Simultaneous writes to the same location on both ports results in
|
memory is read. Simultaneous writes to the same location on both ports results in
|
indeterminate behavior.
|
indeterminate behavior.
|
|
|
*/
|
*/
|
module RAM_DUAL_READ_DUAL_WRITE_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
|
module RAM_DUAL_READ_DUAL_WRITE_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
|
(
|
(
|
input wire [(DATA_WIDTH-1):0] data_a, data_b,
|
input wire [(DATA_WIDTH-1):0] data_a, data_b,
|
input wire [(ADDR_WIDTH-1):0] addr_a, addr_b,
|
input wire [(ADDR_WIDTH-1):0] addr_a, addr_b,
|
input wire we_a, we_b, clk,
|
input wire we_a, we_b, clk,
|
output reg [(DATA_WIDTH-1):0] q_a, q_b
|
output reg [(DATA_WIDTH-1):0] q_a, q_b
|
);
|
);
|
|
|
|
|
// Declare the RAM variable
|
// Declare the RAM variable
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin // Port A
|
begin // Port A
|
if (we_a)
|
if (we_a)
|
begin
|
begin
|
ram[addr_a] <= data_a;
|
ram[addr_a] <= data_a;
|
q_a <= data_a;
|
q_a <= data_a;
|
end
|
end
|
else
|
else
|
q_a <= ram[addr_a];
|
q_a <= ram[addr_a];
|
end
|
end
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin // Port b
|
begin // Port b
|
if (we_b)
|
if (we_b)
|
begin
|
begin
|
ram[addr_b] <= data_b;
|
ram[addr_b] <= data_b;
|
q_b <= data_b;
|
q_b <= data_b;
|
end
|
end
|
else
|
else
|
q_b <= ram[addr_b];
|
q_b <= ram[addr_b];
|
end
|
end
|
endmodule
|
endmodule
|
|
|
|
|
module RAM_QUAD_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
|
module RAM_QUAD_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
|
(
|
(
|
input wire [(DATA_WIDTH-1):0] data_a, data_b,
|
input wire [(DATA_WIDTH-1):0] data_a, data_b,
|
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
|
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
|
input wire [(ADDR_WIDTH-1):0] raddr_a, raddr_b,
|
input wire [(ADDR_WIDTH-1):0] raddr_a, raddr_b,
|
input wire we_a, we_b, clk,
|
input wire we_a, we_b, clk,
|
output reg [(DATA_WIDTH-1):0] q_a, q_b
|
output reg [(DATA_WIDTH-1):0] q_a, q_b
|
);
|
);
|
|
|
|
|
// Declare the RAM variable
|
// Declare the RAM variable
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin // Port A
|
begin // Port A
|
if (we_a)
|
if (we_a)
|
begin
|
begin
|
ram[waddr_a] <= data_a;
|
ram[waddr_a] <= data_a;
|
q_a <= data_a;
|
q_a <= data_a;
|
end
|
end
|
else
|
else
|
q_a <= ram[waddr_a];
|
q_a <= ram[waddr_a];
|
end
|
end
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin // Port B
|
begin // Port B
|
if (we_b)
|
if (we_b)
|
begin
|
begin
|
ram[waddr_b] <= data_b;
|
ram[waddr_b] <= data_b;
|
q_b <= data_b;
|
q_b <= data_b;
|
end
|
end
|
else
|
else
|
q_b <= ram[waddr_b];
|
q_b <= ram[waddr_b];
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// A four level, round-robin arbiter. This was
|
// A four level, round-robin arbiter. This was
|
// orginally coded by WD Peterson in VHDL.
|
// orginally coded by WD Peterson in VHDL.
|
//----------------------------------------------------
|
//----------------------------------------------------
|
module ROUND_ROBIN_ARBITER (
|
module ROUND_ROBIN_ARBITER (
|
clk,
|
clk,
|
rst,
|
rst,
|
req4,
|
req4,
|
req3,
|
req3,
|
req2,
|
req2,
|
req1,
|
req1,
|
req0,
|
req0,
|
gnt4,
|
gnt4,
|
gnt3,
|
gnt3,
|
gnt2,
|
gnt2,
|
gnt1,
|
gnt1,
|
gnt0
|
gnt0
|
);
|
);
|
// --------------Port Declaration-----------------------
|
// --------------Port Declaration-----------------------
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input req4;
|
input req4;
|
input req3;
|
input req3;
|
input req2;
|
input req2;
|
input req1;
|
input req1;
|
input req0;
|
input req0;
|
output gnt4;
|
output gnt4;
|
output gnt3;
|
output gnt3;
|
output gnt2;
|
output gnt2;
|
output gnt1;
|
output gnt1;
|
output gnt0;
|
output gnt0;
|
|
|
//--------------Internal Registers----------------------
|
//--------------Internal Registers----------------------
|
wire [2:0] gnt ;
|
wire [2:0] gnt ;
|
wire comreq ;
|
wire comreq ;
|
wire beg ;
|
wire beg ;
|
wire [2:0] lgnt ;
|
wire [2:0] lgnt ;
|
wire lcomreq ;
|
wire lcomreq ;
|
reg lgnt0 ;
|
reg lgnt0 ;
|
reg lgnt1 ;
|
reg lgnt1 ;
|
reg lgnt2 ;
|
reg lgnt2 ;
|
reg lgnt3 ;
|
reg lgnt3 ;
|
reg lgnt4 ;
|
reg lgnt4 ;
|
reg lasmask ;
|
reg lasmask ;
|
reg lmask0 ;
|
reg lmask0 ;
|
reg lmask1 ;
|
reg lmask1 ;
|
reg lmask2 ;
|
reg lmask2 ;
|
reg ledge ;
|
reg ledge ;
|
|
|
//--------------Code Starts Here-----------------------
|
//--------------Code Starts Here-----------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (rst) begin
|
if (rst) begin
|
lgnt0 <= 0;
|
lgnt0 <= 0;
|
lgnt1 <= 0;
|
lgnt1 <= 0;
|
lgnt2 <= 0;
|
lgnt2 <= 0;
|
lgnt3 <= 0;
|
lgnt3 <= 0;
|
lgnt4 <= 0;
|
lgnt4 <= 0;
|
end else begin
|
end else begin
|
lgnt0 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & ~req3 & ~req2 & ~req1 & req0)
|
lgnt0 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & ~req3 & ~req2 & ~req1 & req0)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req0)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req0)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req0)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req0)
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req0 )
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req0 )
|
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req0 )
|
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req0 )
|
| ( lcomreq & lgnt0 );
|
| ( lcomreq & lgnt0 );
|
lgnt1 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req1)
|
lgnt1 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req1)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req1 & ~req0)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req1 & ~req0)
|
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req1 & ~req0)
|
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req1 & ~req0)
|
| ( lcomreq & lgnt1);
|
| ( lcomreq & lgnt1);
|
lgnt2 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1)
|
lgnt2 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req2)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req2)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req2 & ~req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req2 & ~req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req2 & ~req1 & ~req0)
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req2 & ~req1 & ~req0)
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1 & ~req0)
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1 & ~req0)
|
| ( lcomreq & lgnt2);
|
| ( lcomreq & lgnt2);
|
lgnt3 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1)
|
lgnt3 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & req3 & ~req2)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & req3 & ~req2)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & req3)
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & req3)
|
| (~lcomreq & ~lmask2 & ~lmask2 & lmask1 & lmask0 & req3)
|
| (~lcomreq & ~lmask2 & ~lmask2 & lmask1 & lmask0 & req3)
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1 & ~req0)
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1 & ~req0)
|
| ( lcomreq & lgnt3);
|
| ( lcomreq & lgnt3);
|
lgnt4 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req4 & ~req3 & ~req2 & ~req1 & ~req0)
|
lgnt4 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req4 & ~req3 & ~req2 & ~req1 & ~req0)
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req4 & ~req3 & ~req2 & ~req1 )
|
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req4 & ~req3 & ~req2 & ~req1 )
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & req4 & ~req3 & ~req2 )
|
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & req4 & ~req3 & ~req2 )
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & req4 & ~req3 )
|
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & req4 & ~req3 )
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req4 )
|
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req4 )
|
| ( lcomreq & lgnt3);
|
| ( lcomreq & lgnt3);
|
end
|
end
|
|
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// lasmask state machine.
|
// lasmask state machine.
|
//----------------------------------------------------
|
//----------------------------------------------------
|
assign beg = (req4 | req3 | req2 | req1 | req0) & ~lcomreq;
|
assign beg = (req4 | req3 | req2 | req1 | req0) & ~lcomreq;
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
lasmask <= (beg & ~ledge & ~lasmask);
|
lasmask <= (beg & ~ledge & ~lasmask);
|
ledge <= (beg & ~ledge & lasmask)
|
ledge <= (beg & ~ledge & lasmask)
|
| (beg & ledge & ~lasmask);
|
| (beg & ledge & ~lasmask);
|
end
|
end
|
|
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// comreq logic.
|
// comreq logic.
|
//----------------------------------------------------
|
//----------------------------------------------------
|
assign lcomreq =
|
assign lcomreq =
|
( req4 & lgnt4 )
|
( req4 & lgnt4 )
|
| ( req3 & lgnt3 )
|
| ( req3 & lgnt3 )
|
| ( req2 & lgnt2 )
|
| ( req2 & lgnt2 )
|
| ( req1 & lgnt1 )
|
| ( req1 & lgnt1 )
|
| ( req0 & lgnt0 );
|
| ( req0 & lgnt0 );
|
|
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// Encoder logic.
|
// Encoder logic.
|
//----------------------------------------------------
|
//----------------------------------------------------
|
assign lgnt = {lgnt4,(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
|
assign lgnt = {lgnt4,(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
|
|
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// lmask register.
|
// lmask register.
|
//----------------------------------------------------
|
//----------------------------------------------------
|
always @ (posedge clk )
|
always @ (posedge clk )
|
if( rst ) begin
|
if( rst ) begin
|
lmask2 <= 0;
|
lmask2 <= 0;
|
lmask1 <= 0;
|
lmask1 <= 0;
|
lmask0 <= 0;
|
lmask0 <= 0;
|
end else if(lasmask) begin
|
end else if(lasmask) begin
|
lmask2 <= lgnt[2];
|
lmask2 <= lgnt[2];
|
lmask1 <= lgnt[1];
|
lmask1 <= lgnt[1];
|
lmask0 <= lgnt[0];
|
lmask0 <= lgnt[0];
|
end else begin
|
end else begin
|
lmask2 <= lmask2;
|
lmask2 <= lmask2;
|
lmask1 <= lmask1;
|
lmask1 <= lmask1;
|
lmask0 <= lmask0;
|
lmask0 <= lmask0;
|
end
|
end
|
|
|
assign comreq = lcomreq;
|
assign comreq = lcomreq;
|
assign gnt = lgnt;
|
assign gnt = lgnt;
|
//----------------------------------------------------
|
//----------------------------------------------------
|
// Drive the outputs
|
// Drive the outputs
|
//----------------------------------------------------
|
//----------------------------------------------------
|
assign gnt4 = lgnt4;
|
assign gnt4 = lgnt4;
|
assign gnt3 = lgnt3;
|
assign gnt3 = lgnt3;
|
assign gnt2 = lgnt2;
|
assign gnt2 = lgnt2;
|
assign gnt1 = lgnt1;
|
assign gnt1 = lgnt1;
|
assign gnt0 = lgnt0;
|
assign gnt0 = lgnt0;
|
|
|
endmodule
|
endmodule
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
module ROUND_ROBIN_5_ENTRIES
|
module ROUND_ROBIN_5_ENTRIES
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iRequest0,
|
input wire iRequest0,
|
input wire iRequest1,
|
input wire iRequest1,
|
input wire iRequest2,
|
input wire iRequest2,
|
input wire iRequest3,
|
input wire iRequest3,
|
input wire iRequest4,
|
input wire iRequest4,
|
output wire oGrant0,
|
output wire oGrant0,
|
output wire oGrant1,
|
output wire oGrant1,
|
output wire oGrant2,
|
output wire oGrant2,
|
output wire oGrant3,
|
output wire oGrant3,
|
output wire oGrant4,
|
output wire oGrant4,
|
output wire oPriorityGrant
|
output wire oPriorityGrant
|
|
|
);
|
);
|
wire wMaks2,wMaks1,wMaks0;
|
wire wMaks2,wMaks1,wMaks0;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
|
|
|
assign wGrant0 =
|
assign wGrant0 =
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 )
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|
|
|
|
assign wGrant1 =
|
assign wGrant1 =
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4)
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0) ;
|
|
|
assign wGrant2 =
|
assign wGrant2 =
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant3 =
|
assign wGrant3 =
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant4 =
|
assign wGrant4 =
|
( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
|
|
assign oPriorityGrant = wGrant0;
|
assign oPriorityGrant = wGrant0;
|
|
wire wGrant1_Pre, wGrant2_Pre, wGrant3_Pre, wGrant4_Pre;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
( Clock, Reset, 1'b1 , wGrant1, wGrant1_Pre ); //If priority grant comes this cycle then we are having troubles...
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
( Clock, Reset, 1'b1 , wGrant2, wGrant2_Pre );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
( Clock, Reset, 1'b1 , wGrant3, wGrant3_Pre );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
( Clock, Reset, 1'b1 , wGrant4, wGrant4_Pre );
|
|
|
|
|
|
|
|
assign oGrant1 = wGrant1_Pre & ~oPriorityGrant;
|
|
assign oGrant2 = wGrant2_Pre & ~oPriorityGrant;
|
|
assign oGrant3 = wGrant3_Pre & ~oPriorityGrant;
|
|
assign oGrant4 = wGrant4_Pre & ~oPriorityGrant;
|
|
|
reg [4:0] rCurrentState, rNextState;
|
reg [4:0] rCurrentState, rNextState;
|
//Next states logic and Reset sequence
|
//Next states logic and Reset sequence
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
|
|
if (Reset )
|
if (Reset )
|
rCurrentState <= 0;
|
rCurrentState <= 0;
|
else
|
else
|
rCurrentState <= rNextState;
|
rCurrentState <= rNextState;
|
|
|
end
|
end
|
reg[2:0] rMask;
|
reg[2:0] rMask;
|
|
|
assign wMaks0 = rMask[0];
|
assign wMaks0 = rMask[0];
|
assign wMaks1 = rMask[1];
|
assign wMaks1 = rMask[1];
|
assign wMaks2 = rMask[2];
|
assign wMaks2 = rMask[2];
|
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (rCurrentState)
|
case (rCurrentState)
|
//--------------------------------------
|
//--------------------------------------
|
0:
|
0: //Mask for grant 0
|
begin
|
begin
|
rMask = 3'd0;
|
rMask = 3'd0;
|
rNextState = 1;
|
rNextState = 1;
|
end
|
end
|
1:
|
1: //Mask for grant 1
|
begin
|
begin
|
rMask = 3'd1;
|
rMask = 3'd1;
|
rNextState = 2;
|
rNextState = 2;
|
end
|
end
|
2:
|
2:
|
begin
|
begin
|
rMask = 3'd2;
|
rMask = 3'd2;
|
rNextState = 3;
|
rNextState = 3;
|
end
|
end
|
3:
|
3:
|
begin
|
begin
|
rMask = 3'd3;
|
rMask = 3'd3;
|
rNextState = 4;
|
rNextState = 4;
|
end
|
end
|
4:
|
4:
|
begin
|
begin
|
rMask = 3'd4;
|
rMask = 3'd4;
|
rNextState = 0;
|
rNextState = 0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
/*
|
/*
|
UPCOUNTER_POSEDGE # (3) UP1
|
UPCOUNTER_POSEDGE # (3) UP1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Initial( 3'b0 ),
|
.Initial( 3'b0 ),
|
.Enable( 1'b1 ),
|
.Enable( 1'b1 ),
|
.Q({wMaks2,wMaks1,wMaks0})
|
.Q({wMaks2,wMaks1,wMaks0})
|
);
|
);
|
*/
|
*/
|
|
|
|
|
endmodule
|
endmodule
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
module ROUND_ROBIN_6_ENTRIES
|
module ROUND_ROBIN_6_ENTRIES
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iRequest0,
|
input wire iRequest0,
|
input wire iRequest1,
|
input wire iRequest1,
|
input wire iRequest2,
|
input wire iRequest2,
|
input wire iRequest3,
|
input wire iRequest3,
|
input wire iRequest4,
|
input wire iRequest4,
|
input wire iRequest5,
|
input wire iRequest5,
|
output wire oGrant0,
|
output wire oGrant0,
|
output wire oGrant1,
|
output wire oGrant1,
|
output wire oGrant2,
|
output wire oGrant2,
|
output wire oGrant3,
|
output wire oGrant3,
|
output wire oGrant4,
|
output wire oGrant4,
|
output wire oGrant5,
|
output wire oGrant5,
|
output wire oPriorityGrant
|
output wire oPriorityGrant
|
|
|
);
|
);
|
wire wMaks2,wMaks1,wMaks0;
|
wire wMaks2,wMaks1,wMaks0;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
|
|
|
assign wGrant0 =
|
assign wGrant0 =
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 )
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|
|
|
|
assign wGrant1 =
|
assign wGrant1 =
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5)
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
|
|
|
assign wGrant2 =
|
assign wGrant2 =
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|
(wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant3 =
|
assign wGrant3 =
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant4 =
|
assign wGrant4 =
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant5 =
|
assign wGrant5 =
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|
( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
|
|
assign oPriorityGrant = wGrant0;
|
assign oPriorityGrant = wGrant0;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
|
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
|
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
|
|
|
|
|
reg [4:0] rCurrentState, rNextState;
|
reg [4:0] rCurrentState, rNextState;
|
//Next states logic and Reset sequence
|
//Next states logic and Reset sequence
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
|
|
if (Reset )
|
if (Reset )
|
rCurrentState <= 0;
|
rCurrentState <= 0;
|
else
|
else
|
rCurrentState <= rNextState;
|
rCurrentState <= rNextState;
|
|
|
end
|
end
|
reg[2:0] rMask;
|
reg[2:0] rMask;
|
|
|
assign wMaks0 = rMask[0];
|
assign wMaks0 = rMask[0];
|
assign wMaks1 = rMask[1];
|
assign wMaks1 = rMask[1];
|
assign wMaks2 = rMask[2];
|
assign wMaks2 = rMask[2];
|
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (rCurrentState)
|
case (rCurrentState)
|
//--------------------------------------
|
//--------------------------------------
|
0:
|
0:
|
begin
|
begin
|
rMask = 3'd0;
|
rMask = 3'd0;
|
rNextState = 1;
|
rNextState = 1;
|
end
|
end
|
1:
|
1:
|
begin
|
begin
|
rMask = 3'd1;
|
rMask = 3'd1;
|
rNextState = 2;
|
rNextState = 2;
|
end
|
end
|
2:
|
2:
|
begin
|
begin
|
rMask = 3'd2;
|
rMask = 3'd2;
|
rNextState = 3;
|
rNextState = 3;
|
end
|
end
|
3:
|
3:
|
begin
|
begin
|
rMask = 3'd3;
|
rMask = 3'd3;
|
rNextState = 4;
|
rNextState = 4;
|
end
|
end
|
4:
|
4:
|
begin
|
begin
|
rMask = 3'd4;
|
rMask = 3'd4;
|
rNextState = 5;
|
rNextState = 5;
|
end
|
end
|
5:
|
5:
|
begin
|
begin
|
rMask = 3'd5;
|
rMask = 3'd5;
|
rNextState = 0;
|
rNextState = 0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
/*
|
/*
|
UPCOUNTER_POSEDGE # (3) UP1
|
UPCOUNTER_POSEDGE # (3) UP1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Initial( 3'b0 ),
|
.Initial( 3'b0 ),
|
.Enable( 1'b1 ),
|
.Enable( 1'b1 ),
|
.Q({wMaks2,wMaks1,wMaks0})
|
.Q({wMaks2,wMaks1,wMaks0})
|
);
|
);
|
*/
|
*/
|
|
|
|
|
endmodule
|
endmodule
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
module ROUND_ROBIN_7_ENTRIES
|
module ROUND_ROBIN_7_ENTRIES
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire iRequest0,
|
input wire iRequest0,
|
input wire iRequest1,
|
input wire iRequest1,
|
input wire iRequest2,
|
input wire iRequest2,
|
input wire iRequest3,
|
input wire iRequest3,
|
input wire iRequest4,
|
input wire iRequest4,
|
input wire iRequest5,
|
input wire iRequest5,
|
input wire iRequest6,
|
input wire iRequest6,
|
output wire oGrant0,
|
output wire oGrant0,
|
output wire oGrant1,
|
output wire oGrant1,
|
output wire oGrant2,
|
output wire oGrant2,
|
output wire oGrant3,
|
output wire oGrant3,
|
output wire oGrant4,
|
output wire oGrant4,
|
output wire oGrant5,
|
output wire oGrant5,
|
output wire oGrant6,
|
output wire oGrant6,
|
output wire oPriorityGrant
|
output wire oPriorityGrant
|
|
|
);
|
);
|
wire wMaks2,wMaks1,wMaks0;
|
wire wMaks2,wMaks1,wMaks0;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
|
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
|
|
|
assign wGrant0 =
|
assign wGrant0 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 )
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
|
|
|
|
|
assign wGrant1 =
|
assign wGrant1 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6)
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6)
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
|
|
|
assign wGrant2 =
|
assign wGrant2 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant3 =
|
assign wGrant3 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant4 =
|
assign wGrant4 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
assign wGrant5 =
|
assign wGrant5 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
|
|
|
assign wGrant6 =
|
assign wGrant6 =
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest6 )
|
( wMaks2 & wMaks1 & ~wMaks0 & iRequest6 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 )
|
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
|
|
|
|
|
assign oPriorityGrant = wGrant0;
|
assign oPriorityGrant = wGrant0;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
|
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
|
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD6
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD6
|
( Clock, Reset, 1'b1 , wGrant6, oGrant6 );
|
( Clock, Reset, 1'b1 , wGrant6, oGrant6 );
|
|
|
|
|
reg [4:0] rCurrentState, rNextState;
|
reg [4:0] rCurrentState, rNextState;
|
//Next states logic and Reset sequence
|
//Next states logic and Reset sequence
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
|
|
if (Reset )
|
if (Reset )
|
rCurrentState <= 0;
|
rCurrentState <= 0;
|
else
|
else
|
rCurrentState <= rNextState;
|
rCurrentState <= rNextState;
|
|
|
end
|
end
|
reg[2:0] rMask;
|
reg[2:0] rMask;
|
|
|
assign wMaks0 = rMask[0];
|
assign wMaks0 = rMask[0];
|
assign wMaks1 = rMask[1];
|
assign wMaks1 = rMask[1];
|
assign wMaks2 = rMask[2];
|
assign wMaks2 = rMask[2];
|
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (rCurrentState)
|
case (rCurrentState)
|
//--------------------------------------
|
//--------------------------------------
|
0:
|
0:
|
begin
|
begin
|
rMask = 3'd0;
|
rMask = 3'd0;
|
rNextState = 1;
|
rNextState = 1;
|
end
|
end
|
1:
|
1:
|
begin
|
begin
|
rMask = 3'd1;
|
rMask = 3'd1;
|
rNextState = 2;
|
rNextState = 2;
|
end
|
end
|
2:
|
2:
|
begin
|
begin
|
rMask = 3'd2;
|
rMask = 3'd2;
|
rNextState = 3;
|
rNextState = 3;
|
end
|
end
|
3:
|
3:
|
begin
|
begin
|
rMask = 3'd3;
|
rMask = 3'd3;
|
rNextState = 4;
|
rNextState = 4;
|
end
|
end
|
4:
|
4:
|
begin
|
begin
|
rMask = 3'd4;
|
rMask = 3'd4;
|
rNextState = 5;
|
rNextState = 5;
|
end
|
end
|
5:
|
5:
|
begin
|
begin
|
rMask = 3'd5;
|
rMask = 3'd5;
|
rNextState = 6;
|
rNextState = 6;
|
end
|
end
|
6:
|
6:
|
begin
|
begin
|
rMask = 3'd6;
|
rMask = 3'd6;
|
rNextState = 0;
|
rNextState = 0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
