`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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//`define ADDRESSING_MODES_DISABLED 1
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//`define ADDRESSING_MODES_DISABLED 1
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//`define NO_STALL_ON_BRANCH_DEPS 1
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//`define NO_STALL_ON_BRANCH_DEPS 1
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`define II_STATE_AFTER_RESET 0
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`define II_STATE_AFTER_RESET 0
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`define II_FETCH_INSTRUCTION 1
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`define II_FETCH_INSTRUCTION 1
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`define II_ISSUE_REQUEST_WITH_DATA_FWD 2
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`define II_ISSUE_REQUEST_WITH_DATA_FWD 2
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`define II_ISSUE_REQUEST 3
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`define II_ISSUE_REQUEST 3
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`define II_FIFO_UPDATE 4
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`define II_FIFO_UPDATE 4
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`define II_ISSUE_BRANCH_OPERATION 5
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`define II_ISSUE_BRANCH_OPERATION 5
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`define II_UPDATE_PC_BRANCH_OPERATION 6
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`define II_UPDATE_PC_BRANCH_OPERATION 6
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`define TAGMEM_OWNER_ISSUE 1'b0
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`define TAGMEM_OWNER_ISSUE 1'b0
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`define TAGMEM_OWNER_FIFO 1'b1
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`define TAGMEM_OWNER_FIFO 1'b1
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module InstructionIssue
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module InstructionIssue
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction0, //Instruction fetched from IM
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction0, //Instruction fetched from IM
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction1, //Branch taken instruction prefetch
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction1, //Branch taken instruction prefetch
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input wire [`DATA_ROW_WIDTH-1:0] iSourceData0, //Source0 value from RF
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input wire [`DATA_ROW_WIDTH-1:0] iSourceData0, //Source0 value from RF
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input wire [`DATA_ROW_WIDTH-1:0] iSourceData1, //Source1 value from RF
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input wire [`DATA_ROW_WIDTH-1:0] iSourceData1, //Source1 value from RF
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input wire [`NUMBER_OF_RSVR_STATIONS-1:0] iRStationBusy,
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input wire [`NUMBER_OF_RSVR_STATIONS-1:0] iRStationBusy,
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input wire [`COMMIT_PACKET_SIZE-1:0] iResultBcast, //Contains DST and RsId from last commited operation
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input wire [`COMMIT_PACKET_SIZE-1:0] iResultBcast, //Contains DST and RsId from last commited operation
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input wire iSignFlag,
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input wire iSignFlag,
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input wire iZeroFlag,
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input wire iZeroFlag,
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input wire iMtEnabled,
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input wire iMtEnabled,
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input wire iIgnoreResultBcast,
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input wire iIgnoreResultBcast,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oSourceAddress0,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oSourceAddress0,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oSourceAddress1,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oSourceAddress1,
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output wire [`ISSUE_PACKET_SIZE-1:0] oIssueBcast,
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output wire [`ISSUE_PACKET_SIZE-1:0] oIssueBcast,
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input wire [`DATA_ADDRESS_WIDTH -1:0] iFrameOffset,iIndexRegister,
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input wire [`DATA_ADDRESS_WIDTH -1:0] iFrameOffset,iIndexRegister,
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input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iCodeOffset,
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input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iCodeOffset,
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output wire [`INSTRUCTION_ADDR_WIDTH -1:0] oIP0,
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output wire [`INSTRUCTION_ADDR_WIDTH -1:0] oIP0,
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output wire [`INSTRUCTION_ADDR_WIDTH -1:0] oIP1
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output wire [`INSTRUCTION_ADDR_WIDTH -1:0] oIP1
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);
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);
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parameter SB_ENTRY_WIDTH = 4;
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parameter SB_ENTRY_WIDTH = 4;
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wire[SB_ENTRY_WIDTH-1:0] wSource0_Station; //Reservation Station that is currently calculationg Source0, zero means none
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wire[SB_ENTRY_WIDTH-1:0] wSource0_Station; //Reservation Station that is currently calculationg Source0, zero means none
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wire[SB_ENTRY_WIDTH-1:0] wSource1_Station; //Reservation Station that is currently calculationg Source1, zero means none
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wire[SB_ENTRY_WIDTH-1:0] wSource1_Station; //Reservation Station that is currently calculationg Source1, zero means none
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wire[SB_ENTRY_WIDTH-1:0] wSource0_RsSb;
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wire[SB_ENTRY_WIDTH-1:0] wSource0_RsSb;
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wire[`DATA_ADDRESS_WIDTH-1:0] wSBWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wSBWriteAddress;
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wire [SB_ENTRY_WIDTH-1:0] wSBWriteData;
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wire [SB_ENTRY_WIDTH-1:0] wSBWriteData;
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wire wStall;
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wire wStall;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData0;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData0;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData1;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData1;
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wire wFIFO_ReadEnable;
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wire wFIFO_ReadEnable;
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wire [`DATA_ADDRESS_WIDTH-1:0] wFIFO_Dst;
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wire [`DATA_ADDRESS_WIDTH-1:0] wFIFO_Dst;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIssue_Dst;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIssue_Dst;
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wire [`DATA_ADDRESS_WIDTH-1:0] wSource0Addr_Displaced,wSourceAddress0_Imm,wSource0Addr_Displaced_plus_Index;
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wire [`DATA_ADDRESS_WIDTH-1:0] wSource0Addr_Displaced,wSourceAddress0_Imm,wSource0Addr_Displaced_plus_Index;
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wire [`DATA_ADDRESS_WIDTH-1:0] wSource1Addr_Displaced,wSourceAddress1_Imm,wSource1Addr_Displaced_plus_Index;
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wire [`DATA_ADDRESS_WIDTH-1:0] wSource1Addr_Displaced,wSourceAddress1_Imm,wSource1Addr_Displaced_plus_Index;
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wire wSBWriteEnable;
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wire wSBWriteEnable;
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wire[`DATA_ROW_WIDTH-1:0] wSignedSourceData0;
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wire[`DATA_ROW_WIDTH-1:0] wSignedSourceData0;
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wire[`DATA_ROW_WIDTH-1:0] wSignedSourceData1;
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wire[`DATA_ROW_WIDTH-1:0] wSignedSourceData1;
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wire[`DATA_ROW_WIDTH-1:0] wSwizzledSourceData0;
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wire[`DATA_ROW_WIDTH-1:0] wSwizzledSourceData0;
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wire[`DATA_ROW_WIDTH-1:0] wSwizzledSourceData1;
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wire[`DATA_ROW_WIDTH-1:0] wSwizzledSourceData1;
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wire [`DATA_ROW_WIDTH-1:0] wResultData;
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wire [`DATA_ROW_WIDTH-1:0] wResultData;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData1Temp;
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wire [`DATA_ROW_WIDTH-1:0] wSourceData1Temp;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData0;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData0;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData1;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData1;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData0_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData0_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData1_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wScaledSourceData1_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wUnscaleSourceData0_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wUnscaleSourceData0_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wUnscaleSourceData1_Pre;
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wire [`DATA_ROW_WIDTH-1:0] wUnscaleSourceData1_Pre;
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wire [6:0] wOp;
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wire [6:0] wOp;
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wire wBranchTaken;
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wire wBranchTaken;
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wire wCommitBusInputFifo_Empty;
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wire wCommitBusInputFifo_Empty;
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wire wCommitBusDataAvailabe;
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wire wCommitBusDataAvailabe;
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wire wReservationStationBusy;
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wire wReservationStationBusy;
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wire [`COMMIT_PACKET_SIZE-1:0] wResultFifoData;
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wire [`COMMIT_PACKET_SIZE-1:0] wResultFifoData;
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reg rTagMemoryWE,rTagMemOwner,rIssueNow,rIncrementPC,rPopFifo,rBypassFifo,rUseForwardedData;
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reg rTagMemoryWE,rTagMemOwner,rIssueNow,rIncrementPC,rPopFifo,rBypassFifo,rUseForwardedData;
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reg rSetPCBranchTaken;
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reg rSetPCBranchTaken;
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wire wBranchWithDependency;
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wire wBranchWithDependency;
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wire wIO_Operation_TMWRITE;
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wire wMtHasOnceMoreTimeSlot,wEnabled_Delay;
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wire wMtHasOnceMoreTimeSlot,wEnabled_Delay;
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wire wIO_Operation;
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wire wIO_Operation;
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assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
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assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
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assign wIO_Operation_TMWRITE = wIO_Operation && (iInstruction0[`INST_SCOP_RNG] == `IO_OPERATION_OMWRITE);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD123
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD123
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( Clock, Reset, 1'b1 , iEnable , wEnabled_Delay );
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( Clock, Reset, 1'b1 , iEnable , wEnabled_Delay );
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assign wMtHasOnceMoreTimeSlot = ~wEnabled_Delay;
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assign wMtHasOnceMoreTimeSlot = ~wEnabled_Delay;
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assign wStall = iInstruction0[`INST_EOF_RNG];
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assign wStall = iInstruction0[`INST_EOF_RNG];
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reg [4:0] rCurrentState, rNextState;
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reg [4:0] rCurrentState, rNextState;
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//Next states logic and Reset sequence
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//Next states logic and Reset sequence
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always @(posedge Clock )
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always @(posedge Clock )
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begin
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begin
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if (Reset )
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if (Reset )
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rCurrentState <= `II_STATE_AFTER_RESET;
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rCurrentState <= `II_STATE_AFTER_RESET;
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else
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else
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rCurrentState <= rNextState;
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rCurrentState <= rNextState;
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end
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end
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always @ ( * )
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always @ ( * )
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begin
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begin
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case (rCurrentState)
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case (rCurrentState)
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//--------------------------------------
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//--------------------------------------
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`II_STATE_AFTER_RESET:
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`II_STATE_AFTER_RESET:
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begin
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begin
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rTagMemoryWE = 1'b0;
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rTagMemoryWE = 1'b0;
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rTagMemOwner = 1'b0;
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rTagMemOwner = 1'b0;
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rIssueNow = 1'b0;
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rIssueNow = 1'b0;
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rIncrementPC = 1'b0;
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rIncrementPC = 1'b0;
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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rUseForwardedData = 1'b0;
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rUseForwardedData = 1'b0;
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rSetPCBranchTaken = 1'b0;
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rSetPCBranchTaken = 1'b0;
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rNextState = `II_FETCH_INSTRUCTION;
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rNextState = `II_FETCH_INSTRUCTION;
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end
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end
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//--------------------------------------
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//--------------------------------------
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/*The PC will be incremented except for the scenario where we need to wait
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/*The PC will be incremented except for the scenario where we need to wait
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for reservation stations to become available. If we increment the PC, then the
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for reservation stations to become available. If we increment the PC, then the
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value of PC will get update the next clock cycle, and another clock cycle
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value of PC will get update the next clock cycle, and another clock cycle
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after that the instruction will get updated.
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after that the instruction will get updated.
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1- If there is data waiting on the commit bus input port this cycle,
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1- If there is data waiting on the commit bus input port this cycle,
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then do not queue this data into the FIFO but instead set
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then do not queue this data into the input FIFO but instead set
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set the score board write enable to 1, set the wSBWriteAddress
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set the score board write enable to 1, set the wSBWriteAddress
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to the CommitPacket Destination range and update the score board
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to the CommitPacket Destination range and update the score board
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bit to zero, so than in the next state the score board bit associated
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bit to zero, so than in the next state the score board bit associated
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to the commit data has been updated.
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to the commit data has been updated.
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2 - If there is no data waiting on the commit bus this clock cycle, but there
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2 - If there is no data waiting on the commit bus this clock cycle, but there
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is data that has been queued into the input FIFO, then go to a state where this
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is data that has been queued into the input FIFO, then go to a state where this
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data status on the scoreboard gets updated.
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data status on the scoreboard gets updated.
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3 - If there are no available reservation stations left to handle this
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3 - If there are no available reservation stations left to handle this
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instruction (structural hazard) then just stay in these same state to wait for
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instruction (structural hazard) then just stay in these same state to wait for
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a reservation station to become availabe.
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a reservation station to become availabe.
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*/
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*/
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`II_FETCH_INSTRUCTION:
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`II_FETCH_INSTRUCTION:
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begin
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begin
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rTagMemoryWE = wCommitBusDataAvailabe;
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rTagMemoryWE = wCommitBusDataAvailabe;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rIssueNow = 1'b0;
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rIssueNow = 1'b0;
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rIncrementPC = (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT] & wCommitBusInputFifo_Empty) | (~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT] & wCommitBusDataAvailabe));
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rIncrementPC = (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT] & wCommitBusInputFifo_Empty) | (~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT] & wCommitBusDataAvailabe));
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rBypassFifo = wCommitBusDataAvailabe; //Write iCommitBus data directly into tag mem
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rBypassFifo = wCommitBusDataAvailabe; //Write iCommitBus data directly into tag mem
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rUseForwardedData = 1'b0;
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rUseForwardedData = 1'b0;
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rSetPCBranchTaken = 1'b0;
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rSetPCBranchTaken = 1'b0;
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if (wCommitBusDataAvailabe & ~wReservationStationBusy /**/& (iMtEnabled & wMtHasOnceMoreTimeSlot | ~iMtEnabled)/**/)
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if (wCommitBusDataAvailabe & ~wReservationStationBusy /**/& (iMtEnabled & wMtHasOnceMoreTimeSlot | ~iMtEnabled)/**/)
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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else if (~wCommitBusInputFifo_Empty)
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else if (~wCommitBusInputFifo_Empty)
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rNextState = `II_FIFO_UPDATE;
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rNextState = `II_FIFO_UPDATE;
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else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot))
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else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot) /*| wIOWrite_Waiting_for_OMRead*/ )
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rNextState = `II_FETCH_INSTRUCTION;
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rNextState = `II_FETCH_INSTRUCTION;
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else
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else
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rNextState = `II_ISSUE_REQUEST;
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rNextState = `II_ISSUE_REQUEST;
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end
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end
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//--------------------------------------
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//--------------------------------------
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//TODO: If the reservation station is Busy (static hazard)
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//TODO: If the reservation station is Busy (static hazard)
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//Then we shall stall the machine...
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//Then we shall stall the machine...
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`II_ISSUE_REQUEST:
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`II_ISSUE_REQUEST:
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begin
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begin
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rIssueNow = iEnable;
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rIssueNow = iEnable;
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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rUseForwardedData = 1'b0;
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rUseForwardedData = 1'b0;
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rSetPCBranchTaken = 1'b0;
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rSetPCBranchTaken = 1'b0;
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if (~iEnable & ~wCommitBusInputFifo_Empty)
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if (~iEnable & ~wCommitBusInputFifo_Empty)
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rNextState = `II_FIFO_UPDATE;
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rNextState = `II_FIFO_UPDATE;
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else if (~iEnable & wCommitBusInputFifo_Empty)
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else if (~iEnable & wCommitBusInputFifo_Empty)
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rNextState = `II_ISSUE_REQUEST;///////////////////
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rNextState = `II_ISSUE_REQUEST;///////////////////
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else
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else
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if (iInstruction0[`INST_BRANCH_BIT])
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if (iInstruction0[`INST_BRANCH_BIT])
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rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
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rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
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else
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else
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rNextState = `II_FETCH_INSTRUCTION;
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rNextState = `II_FETCH_INSTRUCTION;
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end
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end
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//--------------------------------------
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//--------------------------------------
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/*
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/*
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Here the instruction remains the same as in the
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Here the instruction remains the same as in the
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previous clock cycle.
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previous clock cycle.
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*/
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*/
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`II_ISSUE_REQUEST_WITH_DATA_FWD:
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`II_ISSUE_REQUEST_WITH_DATA_FWD:
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begin
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begin
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
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rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rTagMemOwner = `TAGMEM_OWNER_ISSUE;
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rIssueNow = iEnable;
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rIssueNow = iEnable;
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
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rPopFifo = 1'b1;
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rPopFifo = 1'b1;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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rUseForwardedData = 1'b1;
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rUseForwardedData = 1'b1;
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rSetPCBranchTaken = 1'b0;//wBranchTaken;
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rSetPCBranchTaken = 1'b0;//wBranchTaken;
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if (~iEnable & ~wCommitBusInputFifo_Empty)
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if (~iEnable & ~wCommitBusInputFifo_Empty)
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rNextState = `II_FIFO_UPDATE;
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rNextState = `II_FIFO_UPDATE;
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else if (~iEnable & wCommitBusInputFifo_Empty)
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else if (~iEnable & wCommitBusInputFifo_Empty)
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
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else
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else
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if (iInstruction0[`INST_BRANCH_BIT])
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if (iInstruction0[`INST_BRANCH_BIT])
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rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
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rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
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else
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else
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rNextState = `II_FETCH_INSTRUCTION;
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rNextState = `II_FETCH_INSTRUCTION;
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end
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end
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//--------------------------------------
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//--------------------------------------
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`II_FIFO_UPDATE:
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`II_FIFO_UPDATE:
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begin
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begin
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rTagMemoryWE = 1'b1;
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rTagMemoryWE = 1'b1;
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rTagMemOwner = `TAGMEM_OWNER_FIFO;
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rTagMemOwner = `TAGMEM_OWNER_FIFO;
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rIssueNow = 1'b0;
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rIssueNow = 1'b0;
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rIncrementPC = (iMtEnabled & wMtHasOnceMoreTimeSlot /*| ~iMtEnabled*/) & ~wBranchWithDependency & (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT]));//1'b0;
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rIncrementPC = (iMtEnabled & wMtHasOnceMoreTimeSlot /*| ~iMtEnabled*/) & ~wBranchWithDependency & (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT]));//1'b0;
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rPopFifo = 1'b1;
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rPopFifo = 1'b1;
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rBypassFifo = 1'b0;
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rBypassFifo = 1'b0;
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rUseForwardedData = 1'b0;
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rUseForwardedData = 1'b0;
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rSetPCBranchTaken = 1'b0;
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rSetPCBranchTaken = 1'b0;
|
|
|
if (wBranchWithDependency & ~iMtEnabled)
|
if (wBranchWithDependency & ~iMtEnabled)
|
rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
|
rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
|
else if ((~iMtEnabled | (iMtEnabled & wMtHasOnceMoreTimeSlot)) & ~wBranchWithDependency & (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT])))
|
else if ((~iMtEnabled | (iMtEnabled & wMtHasOnceMoreTimeSlot)) & ~wBranchWithDependency & (( ~wReservationStationBusy & ~iInstruction0[`INST_BRANCH_BIT])))
|
rNextState = `II_ISSUE_REQUEST;
|
rNextState = `II_ISSUE_REQUEST;
|
else
|
else
|
rNextState = `II_FETCH_INSTRUCTION;
|
rNextState = `II_FETCH_INSTRUCTION;
|
end
|
end
|
//--------------------------------------
|
//--------------------------------------
|
//FIXME: You are assuming that the branch takes 1 cycle.
|
//FIXME: You are assuming that the branch takes 1 cycle.
|
//This may noy always be the case..
|
//This may noy always be the case..
|
`II_UPDATE_PC_BRANCH_OPERATION:
|
`II_UPDATE_PC_BRANCH_OPERATION:
|
begin
|
begin
|
rTagMemoryWE = 1'b0;
|
rTagMemoryWE = 1'b0;
|
rTagMemOwner = `TAGMEM_OWNER_FIFO;
|
rTagMemOwner = `TAGMEM_OWNER_FIFO;
|
rIssueNow = 1'b0;
|
rIssueNow = 1'b0;
|
rIncrementPC = 1'b0;
|
rIncrementPC = 1'b0;
|
rPopFifo = 1'b1;
|
rPopFifo = 1'b1;
|
rBypassFifo = 1'b0;
|
rBypassFifo = 1'b0;
|
rUseForwardedData = 1'b0;
|
rUseForwardedData = 1'b0;
|
rSetPCBranchTaken = wBranchTaken;
|
rSetPCBranchTaken = wBranchTaken;
|
|
|
`ifdef NO_STALL_ON_BRANCH_DEPS
|
`ifdef NO_STALL_ON_BRANCH_DEPS
|
rNextState = `II_FETCH_INSTRUCTION;
|
rNextState = `II_FETCH_INSTRUCTION;
|
`else
|
`else
|
if (~wBranchWithDependency)
|
if (~wBranchWithDependency)
|
rNextState = `II_FETCH_INSTRUCTION;
|
rNextState = `II_FETCH_INSTRUCTION;
|
else if (~wCommitBusInputFifo_Empty)
|
else if (~wCommitBusInputFifo_Empty)
|
rNextState = `II_FIFO_UPDATE;
|
rNextState = `II_FIFO_UPDATE;
|
else
|
else
|
rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
|
rNextState = `II_UPDATE_PC_BRANCH_OPERATION;
|
`endif
|
`endif
|
|
|
|
|
end
|
end
|
//--------------------------------------
|
//--------------------------------------
|
default:
|
default:
|
begin
|
begin
|
rTagMemOwner = `TAGMEM_OWNER_ISSUE;
|
rTagMemOwner = `TAGMEM_OWNER_ISSUE;
|
rTagMemoryWE = 1'b0;
|
rTagMemoryWE = 1'b0;
|
rIssueNow = 1'b0;
|
rIssueNow = 1'b0;
|
rIncrementPC = 1'b0;
|
rIncrementPC = 1'b0;
|
rPopFifo = 1'b0;
|
rPopFifo = 1'b0;
|
rBypassFifo = 1'b0;
|
rBypassFifo = 1'b0;
|
rUseForwardedData = 1'b0;
|
rUseForwardedData = 1'b0;
|
rSetPCBranchTaken = 1'b0;
|
rSetPCBranchTaken = 1'b0;
|
|
|
rNextState = `II_STATE_AFTER_RESET;
|
rNextState = `II_STATE_AFTER_RESET;
|
end
|
end
|
//--------------------------------------
|
//--------------------------------------
|
endcase
|
endcase
|
|
|
|
|
end
|
end
|
|
|
wire [2:0] wInstructionBranchSelection;
|
wire [2:0] wInstructionBranchSelection;
|
assign wInstructionBranchSelection = iInstruction0[`INST_BRANCH_OP_RNG];
|
assign wInstructionBranchSelection = iInstruction0[`INST_BRANCH_OP_RNG];
|
wire wCommitFromPendingStation;
|
wire wCommitFromPendingStation;
|
assign wCommitFromPendingStation = (iResultBcast[`COMMIT_RSID_RNG] == wReservationStation) ? 1'b1 : 1'b0;
|
assign wCommitFromPendingStation = (iResultBcast[`COMMIT_RSID_RNG] == wReservationStation) ? 1'b1 : 1'b0;
|
|
|
assign wBranchTaken =
|
assign wBranchTaken =
|
wCommitFromPendingStation &
|
wCommitFromPendingStation &
|
iInstruction0[`INST_BRANCH_BIT] &
|
iInstruction0[`INST_BRANCH_BIT] &
|
(
|
(
|
~wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] | //inconditional BRANCH
|
~wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] | //inconditional BRANCH
|
~wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & iZeroFlag | //==
|
~wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & iZeroFlag | //==
|
~wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & ~iZeroFlag | //!=
|
~wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & ~iZeroFlag | //!=
|
~wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & iSignFlag | //<
|
~wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & iSignFlag | //<
|
wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & (~iSignFlag & ~iZeroFlag)| //>
|
wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & (~iSignFlag & ~iZeroFlag)| //>
|
wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & (iSignFlag | iZeroFlag) | //<=
|
wInstructionBranchSelection[2] & ~wInstructionBranchSelection[1] & wInstructionBranchSelection[0] & (iSignFlag | iZeroFlag) | //<=
|
wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & (~iSignFlag | iZeroFlag) //>=
|
wInstructionBranchSelection[2] & wInstructionBranchSelection[1] & ~wInstructionBranchSelection[0] & (~iSignFlag | iZeroFlag) //>=
|
);
|
);
|
|
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Latched;
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Latched;
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `COMMIT_PACKET_SIZE ) ICOMMIT_BYPASS_FFD
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `COMMIT_PACKET_SIZE ) ICOMMIT_BYPASS_FFD
|
( Clock, Reset, 1'b1 ,iResultBcast , wCommitData_Latched );
|
( Clock, Reset, 1'b1 ,iResultBcast , wCommitData_Latched );
|
|
|
|
|
//The Reservation Station scoreboard
|
//The Reservation Station scoreboard
|
wire [SB_ENTRY_WIDTH-1:0] wSBDataPort0;
|
wire [SB_ENTRY_WIDTH-1:0] wSBDataPort0;
|
wire [SB_ENTRY_WIDTH-1:0] wSBDataPort1;
|
wire [SB_ENTRY_WIDTH-1:0] wSBDataPort1;
|
wire[3:0] wReservationStation;
|
wire[3:0] wReservationStation;
|
|
|
`ifdef ADDRESSING_MODES_DISABLED
|
`ifdef ADDRESSING_MODES_DISABLED
|
|
|
|
//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
|
|
//or the SB can be updated by the value comming from the wResultFifoData
|
assign wSBWriteAddress
|
assign wSBWriteAddress
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:iInstruction0[`INST_DST_RNG])
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:iInstruction0[`INST_DST_RNG])
|
: wResultFifoData[`COMMIT_DST_RNG];
|
: wResultFifoData[`COMMIT_DST_RNG];
|
|
|
`else
|
`else
|
|
//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
|
|
//or the SB can be updated by the value comming from the wResultFifoData
|
assign wSBWriteAddress
|
assign wSBWriteAddress
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:wDestinationIndex)
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:wDestinationIndex)
|
: wResultFifoData[`COMMIT_DST_RNG];
|
: wResultFifoData[`COMMIT_DST_RNG];
|
`endif
|
`endif
|
|
|
assign wSBWriteData
|
assign wSBWriteData
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?1'b0:wReservationStation) : 4'b0;
|
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?1'b0:wReservationStation) : 4'b0;
|
|
|
wire wTagMemoryWE;
|
wire wTagMemoryWE;
|
assign wTagMemoryWE = rTagMemoryWE;//(rTagMemoryWE && (iInstruction0[`INST_CODE_RNG] != `OPERATION_OUT)); //Dont store dependencies for IO operations
|
assign wTagMemoryWE = rTagMemoryWE;//(rTagMemoryWE && (iInstruction0[`INST_CODE_RNG] != `OPERATION_OUT)); //Dont store dependencies for IO operations
|
|
|
RAM_DUAL_READ_PORT # ( SB_ENTRY_WIDTH, `DATA_ADDRESS_WIDTH ) SB
|
RAM_DUAL_READ_PORT # ( SB_ENTRY_WIDTH, `DATA_ADDRESS_WIDTH ) SB
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( wTagMemoryWE ),
|
.iWriteEnable( wTagMemoryWE ),
|
.iReadAddress0( oSourceAddress0 ),
|
.iReadAddress0( oSourceAddress0 ),
|
.iReadAddress1( oSourceAddress1 ),
|
.iReadAddress1( oSourceAddress1 ),
|
.iWriteAddress( wSBWriteAddress ),
|
.iWriteAddress( wSBWriteAddress ),
|
.iDataIn( wSBWriteData ),
|
.iDataIn( wSBWriteData ),
|
.oDataOut0( wSBDataPort0 ),
|
.oDataOut0( wSBDataPort0 ),
|
.oDataOut1( wSBDataPort1 )
|
.oDataOut1( wSBDataPort1 )
|
);
|
);
|
|
|
|
|
wire [`INSTRUCTION_ADDR_WIDTH-1:0] wPCInitialValue;
|
wire [`INSTRUCTION_ADDR_WIDTH-1:0] wPCInitialValue;
|
wire [`INSTRUCTION_ADDR_WIDTH-1:0] wPCInitialTmp;
|
wire [`INSTRUCTION_ADDR_WIDTH-1:0] wPCInitialTmp;
|
assign wPCInitialTmp = (iInstruction0[`INST_IMM])? wSourceData0[`SRC_RET_ADDR_RNG] : {2'b0,iInstruction0[`INST_DST_RNG]};
|
assign wPCInitialTmp = (iInstruction0[`INST_IMM])? wSourceData0[`SRC_RET_ADDR_RNG] : {2'b0,iInstruction0[`INST_DST_RNG]};
|
|
|
|
|
|
|
assign wPCInitialValue = (rSetPCBranchTaken & ~Reset) ? wPCInitialTmp : iCodeOffset;
|
assign wPCInitialValue = (rSetPCBranchTaken & ~Reset) ? wPCInitialTmp : iCodeOffset;
|
|
|
|
|
|
|
//The program counter
|
//The program counter
|
UPCOUNTER_POSEDGE # (`INSTRUCTION_ADDR_WIDTH ) PC
|
UPCOUNTER_POSEDGE # (`INSTRUCTION_ADDR_WIDTH ) PC
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset | rSetPCBranchTaken ),
|
.Reset( Reset | rSetPCBranchTaken ),
|
.Enable( rIncrementPC & ~wStall ),
|
.Enable( rIncrementPC & ~wStall ),
|
.Initial( wPCInitialValue ),
|
.Initial( wPCInitialValue ),
|
.Q( oIP0 )
|
.Q( oIP0 )
|
);
|
);
|
|
|
assign oIP1 = iInstruction0[`INST_DST_RNG];
|
assign oIP1 = iInstruction0[`INST_DST_RNG];
|
|
|
|
|
`ifdef ADDRESSING_MODES_DISABLED
|
`ifdef ADDRESSING_MODES_DISABLED
|
assign oSourceAddress1 = iInstruction0[`INST_SCR1_ADDR_RNG];
|
assign oSourceAddress1 = iInstruction0[`INST_SCR1_ADDR_RNG];
|
|
|
|
|
`else
|
`else
|
|
|
assign oSourceAddress1 = (iInstruction0[`INST_IMM]) ? wSourceAddress1_Imm :
|
assign oSourceAddress1 = (iInstruction0[`INST_IMM]) ? wSourceAddress1_Imm :
|
((iInstruction0[`INST_SRC1_DISPLACED]) ? wSource1Addr_Displaced: iInstruction0[`INST_SCR1_ADDR_RNG]);
|
((iInstruction0[`INST_SRC1_DISPLACED]) ? wSource1Addr_Displaced: iInstruction0[`INST_SCR1_ADDR_RNG]);
|
|
|
assign wSource1Addr_Displaced = iInstruction0[`INST_SCR1_ADDR_RNG] + iFrameOffset;
|
assign wSource1Addr_Displaced = iInstruction0[`INST_SCR1_ADDR_RNG] + iFrameOffset;
|
assign wSource1Addr_Displaced_plus_Index = wSource1Addr_Displaced + iIndexRegister;
|
assign wSource1Addr_Displaced_plus_Index = wSource1Addr_Displaced + iIndexRegister;
|
|
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) SRC1ADDRMUX
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) SRC1ADDRMUX
|
(
|
(
|
.Sel(iInstruction0[`INST_ADDRMODE_RNG]),
|
.Sel(iInstruction0[`INST_ADDRMODE_RNG]),
|
.I1(`DATA_ADDRESS_WIDTH'b0),
|
.I1(`DATA_ADDRESS_WIDTH'b0),
|
.I2(`DATA_ADDRESS_WIDTH'b0),
|
.I2(`DATA_ADDRESS_WIDTH'b0),
|
.I3(iInstruction0[`INST_SCR1_ADDR_RNG]),
|
.I3(iInstruction0[`INST_SCR1_ADDR_RNG]),
|
.I4(iInstruction0[`INST_SCR1_ADDR_RNG]),
|
.I4(iInstruction0[`INST_SCR1_ADDR_RNG]),
|
.I5(`DATA_ADDRESS_WIDTH'b0),
|
.I5(`DATA_ADDRESS_WIDTH'b0),
|
.I6(`DATA_ADDRESS_WIDTH'b0),
|
.I6(`DATA_ADDRESS_WIDTH'b0),
|
.I7(wSource1Addr_Displaced_plus_Index),
|
.I7(wSource1Addr_Displaced_plus_Index),
|
.I8(wSource1Addr_Displaced_plus_Index),
|
.I8(wSource1Addr_Displaced_plus_Index),
|
.O1(wSourceAddress1_Imm)
|
.O1(wSourceAddress1_Imm)
|
);
|
);
|
`endif
|
`endif
|
|
|
|
|
`ifdef ADDRESSING_MODES_DISABLED
|
`ifdef ADDRESSING_MODES_DISABLED
|
assign oSourceAddress0 = (iInstruction0[`INST_IMM] ) ? iInstruction0[`INST_DST_RNG] : iInstruction0[`INST_SRC0_ADDR_RNG];
|
assign oSourceAddress0 = (iInstruction0[`INST_IMM] ) ? iInstruction0[`INST_DST_RNG] : iInstruction0[`INST_SRC0_ADDR_RNG];
|
`else
|
`else
|
|
|
assign oSourceAddress0 = (iInstruction0[`INST_IMM]) ? wSourceAddress0_Imm :
|
assign oSourceAddress0 = (iInstruction0[`INST_IMM]) ? wSourceAddress0_Imm :
|
((iInstruction0[`INST_SRC0_DISPLACED]) ? wSource0Addr_Displaced: iInstruction0[`INST_SRC0_ADDR_RNG]);
|
((iInstruction0[`INST_SRC0_DISPLACED]) ? wSource0Addr_Displaced: iInstruction0[`INST_SRC0_ADDR_RNG]);
|
|
|
assign wSource0Addr_Displaced = iInstruction0[`INST_SRC0_ADDR_RNG] + iFrameOffset;
|
assign wSource0Addr_Displaced = iInstruction0[`INST_SRC0_ADDR_RNG] + iFrameOffset;
|
assign wSource0Addr_Displaced_plus_Index = wSource0Addr_Displaced + iIndexRegister;
|
assign wSource0Addr_Displaced_plus_Index = wSource0Addr_Displaced + iIndexRegister;
|
|
|
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) SRC0ADDRMUX
|
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) SRC0ADDRMUX
|
(
|
(
|
.Sel({iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.Sel({iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.I1(iInstruction0[`INST_DST_RNG]),
|
.I1(iInstruction0[`INST_DST_RNG]),
|
.I2(iInstruction0[`INST_DST_RNG]),
|
.I2(iInstruction0[`INST_DST_RNG]),
|
.I3(wSource0Addr_Displaced_plus_Index),
|
.I3(wSource0Addr_Displaced_plus_Index),
|
.I4(wSource0Addr_Displaced),
|
.I4(wSource0Addr_Displaced),
|
.O1(wSourceAddress0_Imm)
|
.O1(wSourceAddress0_Imm)
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
|
|
assign wCommitBusDataAvailabe = ((iResultBcast[`COMMIT_RSID_RNG] != `OPERATION_NOP) && (~iIgnoreResultBcast));
|
assign wCommitBusDataAvailabe = ((iResultBcast[`COMMIT_RSID_RNG] != `OPERATION_NOP) && (~iIgnoreResultBcast));
|
|
|
|
|
sync_fifo # (`COMMIT_PACKET_SIZE,2 ) RESULT_IN_FIFO
|
sync_fifo # (`COMMIT_PACKET_SIZE,2 ) RESULT_IN_FIFO
|
(
|
(
|
.clk( Clock ),
|
.clk( Clock ),
|
.reset( Reset ),
|
.reset( Reset ),
|
.din( iResultBcast ),
|
.din( iResultBcast ),
|
.wr_en( wCommitBusDataAvailabe ),
|
.wr_en( wCommitBusDataAvailabe ),
|
.rd_en( rPopFifo ),
|
.rd_en( rPopFifo ),
|
.dout( wResultFifoData ),
|
.dout( wResultFifoData ),
|
.empty( wCommitBusInputFifo_Empty )
|
.empty( wCommitBusInputFifo_Empty )
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
//Source 1 for IMM values is really DST
|
//Source 1 for IMM values is really DST
|
|
|
//Reservation station for SRC0 when handling IMM values is zero
|
//Reservation station for SRC0 when handling IMM values is zero
|
|
|
wire wSB0FromInCommit,wSB0ForwardDetected;
|
wire wSB0FromInCommit,wSB0ForwardDetected;
|
wire wSB1FromInCommit,wSB1ForwardDetected;
|
wire wSB1FromInCommit,wSB1ForwardDetected;
|
|
|
assign wSB0FromInCommit = 1'b0;//(rIssueNow && (iResultBcast[`COMMIT_DST_RNG] == oSourceAddress0)) ? 1'b1 : 1'b0;
|
assign wSB0FromInCommit = 1'b0;//(rIssueNow && (iResultBcast[`COMMIT_DST_RNG] == oSourceAddress0)) ? 1'b1 : 1'b0;
|
assign wSB1FromInCommit = 1'b0;//(rIssueNow && (iResultBcast[`COMMIT_DST_RNG] == oSourceAddress1)) ? 1'b1 : 1'b0;
|
assign wSB1FromInCommit = 1'b0;//(rIssueNow && (iResultBcast[`COMMIT_DST_RNG] == oSourceAddress1)) ? 1'b1 : 1'b0;
|
|
|
`ifdef ADDRESSING_MODES_DISABLED
|
`ifdef ADDRESSING_MODES_DISABLED
|
wire [`DATA_ADDRESS_WIDTH-1:0] wTmpAddr0;
|
wire [`DATA_ADDRESS_WIDTH-1:0] wTmpAddr0;
|
assign wTmpAddr0 = (iInstruction0[`INST_IMM]) ? iInstruction0[`INST_DST_RNG] : iInstruction0[`INST_SRC0_ADDR_RNG];
|
assign wTmpAddr0 = (iInstruction0[`INST_IMM]) ? iInstruction0[`INST_DST_RNG] : iInstruction0[`INST_SRC0_ADDR_RNG];
|
|
|
assign wSB0ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr0) ) ? 1'b1 : 1'b0;
|
assign wSB0ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr0) ) ? 1'b1 : 1'b0;
|
assign wSB1ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == iInstruction0[`INST_SCR1_ADDR_RNG]) ) ? 1'b1 : 1'b0;
|
assign wSB1ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == iInstruction0[`INST_SCR1_ADDR_RNG]) ) ? 1'b1 : 1'b0;
|
`else
|
`else
|
wire [`DATA_ADDRESS_WIDTH-1:0] wTmpAddr0,wTmpAddr1;
|
wire [`DATA_ADDRESS_WIDTH-1:0] wTmpAddr0,wTmpAddr1;
|
assign wTmpAddr0 = oSourceAddress0;
|
assign wTmpAddr0 = oSourceAddress0;
|
assign wTmpAddr1 = oSourceAddress1;
|
assign wTmpAddr1 = oSourceAddress1;
|
|
|
assign wSB0ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr0) /*&& ( wSource0_Station == iResultBcast[`COMMIT_RSID_RNG])*/ ) ? 1'b1 : 1'b0;
|
assign wSB0ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr0) /*&& ( wSource0_Station == iResultBcast[`COMMIT_RSID_RNG])*/ ) ? 1'b1 : 1'b0;
|
assign wSB1ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr1) /*&& ( wSource1_Station == iResultBcast[`COMMIT_RSID_RNG])*/ ) ? 1'b1 : 1'b0;
|
assign wSB1ForwardDetected = (rUseForwardedData && (wCommitData_Latched[`COMMIT_DST_RNG] == wTmpAddr1) /*&& ( wSource1_Station == iResultBcast[`COMMIT_RSID_RNG])*/ ) ? 1'b1 : 1'b0;
|
`endif
|
`endif
|
|
|
//FIX!!! FIX!!! Use the table to know when dependencies for SRC0 and SRC1 are don't care
|
//FIX!!! FIX!!! Use the table to know when dependencies for SRC0 and SRC1 are don't care
|
//Fix this should not be (iInstruction0[`INST_IMM] & iInstruction0[`INST_DEST_ZERO]) but isntead should use the table
|
//Fix this should not be (iInstruction0[`INST_IMM] & iInstruction0[`INST_DEST_ZERO]) but isntead should use the table
|
assign wSource0_Station = (wSB0FromInCommit | wSB0ForwardDetected | (iInstruction0[`INST_IMM] & iInstruction0[`INST_DEST_ZERO])) ? 4'b0 : wSBDataPort0;
|
assign wSource0_Station = (wSB0FromInCommit | wSB0ForwardDetected | (iInstruction0[`INST_IMM] & iInstruction0[`INST_DEST_ZERO])) ? 4'b0 : wSBDataPort0;
|
assign wSource1_Station = (iInstruction0[`INST_IMM] | wSB1FromInCommit | wSB1ForwardDetected) ? 4'b0: wSBDataPort1;
|
assign wSource1_Station = (iInstruction0[`INST_IMM] | wSB1FromInCommit | wSB1ForwardDetected) ? 4'b0: wSBDataPort1;
|
|
|
|
|
//Handle literal values for IMM. IMM is stored in SRC1.X
|
//Handle literal values for IMM. IMM is stored in SRC1.X
|
|
|
|
|
wire [`DATA_ROW_WIDTH-1:0] wImmValue,wSource1_Temp,wSource0_Temp,wSourceData1_Imm,wSourceData0_Imm;
|
wire [`DATA_ROW_WIDTH-1:0] wImmValue,wSource1_Temp,wSource0_Temp,wSourceData1_Imm,wSourceData0_Imm;
|
assign wImmValue[`X_RNG] = (iInstruction0[`INST_WE_X]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
|
assign wImmValue[`X_RNG] = (iInstruction0[`INST_WE_X]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
|
assign wImmValue[`Y_RNG] = (iInstruction0[`INST_WE_Y]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
|
assign wImmValue[`Y_RNG] = (iInstruction0[`INST_WE_Y]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
|
assign wImmValue[`Z_RNG] = (iInstruction0[`INST_WE_Z]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
|
assign wImmValue[`Z_RNG] = (iInstruction0[`INST_WE_Z]) ? iInstruction0[`INST_IMM_RNG] : `WIDTH'b0;
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|
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|
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assign wSource1_Temp[`X_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_X]) ? iResultBcast[`COMMIT_X_RNG] :
|
assign wSource1_Temp[`X_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_X]) ? iResultBcast[`COMMIT_X_RNG] :
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_X])? wCommitData_Latched[`X_RNG] : iSourceData1[`X_RNG]);
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_X])? wCommitData_Latched[`X_RNG] : iSourceData1[`X_RNG]);
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|
|
assign wSource1_Temp[`Y_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_Y]) ? iResultBcast[`COMMIT_Y_RNG] :
|
assign wSource1_Temp[`Y_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_Y]) ? iResultBcast[`COMMIT_Y_RNG] :
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_Y]) ? wCommitData_Latched[`Y_RNG] : iSourceData1[`Y_RNG]);
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_Y]) ? wCommitData_Latched[`Y_RNG] : iSourceData1[`Y_RNG]);
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|
|
|
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assign wSource1_Temp[`Z_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_Z]) ? iResultBcast[`COMMIT_Z_RNG] :
|
assign wSource1_Temp[`Z_RNG] = (wSB1FromInCommit & iResultBcast[`COMMIT_WE_Z]) ? iResultBcast[`COMMIT_Z_RNG] :
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_Z]) ? wCommitData_Latched[`Z_RNG] : iSourceData1[`Z_RNG]);
|
( (wSB1ForwardDetected & wCommitData_Latched[`COMMIT_WE_Z]) ? wCommitData_Latched[`Z_RNG] : iSourceData1[`Z_RNG]);
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|
|
assign wSource0_Temp[`X_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_X]) ? iResultBcast[`COMMIT_X_RNG]:
|
assign wSource0_Temp[`X_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_X]) ? iResultBcast[`COMMIT_X_RNG]:
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_X] )? wCommitData_Latched[`X_RNG]:iSourceData0[`X_RNG]);
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_X] )? wCommitData_Latched[`X_RNG]:iSourceData0[`X_RNG]);
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|
|
|
|
assign wSource0_Temp[`Y_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_Y]) ? iResultBcast[`COMMIT_Y_RNG]:
|
assign wSource0_Temp[`Y_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_Y]) ? iResultBcast[`COMMIT_Y_RNG]:
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_Y])? wCommitData_Latched[`Y_RNG] : iSourceData0[`Y_RNG]);
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_Y])? wCommitData_Latched[`Y_RNG] : iSourceData0[`Y_RNG]);
|
|
|
assign wSource0_Temp[`Z_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_Z]) ? iResultBcast[`COMMIT_Z_RNG]:
|
assign wSource0_Temp[`Z_RNG] = (wSB0FromInCommit & iResultBcast[`COMMIT_WE_Z]) ? iResultBcast[`COMMIT_Z_RNG]:
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_Z])? wCommitData_Latched[`Z_RNG] : iSourceData0[`Z_RNG]);
|
( (wSB0ForwardDetected & & wCommitData_Latched[`COMMIT_WE_Z])? wCommitData_Latched[`Z_RNG] : iSourceData0[`Z_RNG]);
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|
|
|
|
|
|
//If the data we are looking for just arrived at iResultBcast the use that
|
//If the data we are looking for just arrived at iResultBcast the use that
|
//other wise used the data from the Register file or the Immediate values
|
//other wise used the data from the Register file or the Immediate values
|
//assign wSourceData1 = (iInstruction0[`INST_IMM]) ? wImmValue : wSource1_Temp;
|
//assign wSourceData1 = (iInstruction0[`INST_IMM]) ? wImmValue : wSource1_Temp;
|
//assign wSourceData0 = (iInstruction0[`INST_IMM] && iInstruction0[`INST_DEST_ZERO]) ? `DATA_ROW_WIDTH'd0 : wSource0_Temp;
|
//assign wSourceData0 = (iInstruction0[`INST_IMM] && iInstruction0[`INST_DEST_ZERO]) ? `DATA_ROW_WIDTH'd0 : wSource0_Temp;
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|
|
|
|
assign wSourceData1 = (iInstruction0[`INST_IMM]) ? wSourceData1_Imm : wSource1_Temp;
|
assign wSourceData1 = (iInstruction0[`INST_IMM]) ? wSourceData1_Imm : wSource1_Temp;
|
assign wSourceData0 = (iInstruction0[`INST_IMM]) ? wSourceData0_Imm : wSource0_Temp;
|
assign wSourceData0 = (iInstruction0[`INST_IMM]) ? wSourceData0_Imm : wSource0_Temp;
|
//assign wSourceData0 = (iInstruction0[`INST_IMM] && iInstruction0[`INST_DEST_ZERO]) ? `DATA_ROW_WIDTH'd0 : wSource0_Temp;
|
//assign wSourceData0 = (iInstruction0[`INST_IMM] && iInstruction0[`INST_DEST_ZERO]) ? `DATA_ROW_WIDTH'd0 : wSource0_Temp;
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|
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ROW_WIDTH ) SRC1MUX
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ROW_WIDTH ) SRC1MUX
|
(
|
(
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.I1(wImmValue),
|
.I1(wImmValue),
|
.I2(wImmValue),
|
.I2(wImmValue),
|
.I3(wSource1_Temp),
|
.I3(wSource1_Temp),
|
.I4( `DATA_ROW_WIDTH'b0),
|
.I4( `DATA_ROW_WIDTH'b0),
|
.I5( wImmValue ),
|
.I5( wImmValue ),
|
.I6( wImmValue ),
|
.I6( wImmValue ),
|
.I7( wSource1_Temp ),
|
.I7( wSource1_Temp ),
|
.I8( wSource1_Temp ),
|
.I8( wSource1_Temp ),
|
.O1(wSourceData1_Imm)
|
.O1(wSourceData1_Imm)
|
);
|
);
|
|
|
|
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ROW_WIDTH ) SRC0MUX
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ROW_WIDTH ) SRC0MUX
|
(
|
(
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.I1( wSource0_Temp ),
|
.I1( wSource0_Temp ),
|
.I2( wSource0_Temp ),
|
.I2( wSource0_Temp ),
|
.I3( wSource0_Temp ),
|
.I3( wSource0_Temp ),
|
.I4( wSource0_Temp ),
|
.I4( wSource0_Temp ),
|
.I5( `DATA_ROW_WIDTH'b0 ),
|
.I5( `DATA_ROW_WIDTH'b0 ),
|
.I6( `DATA_ROW_WIDTH'b0 ),
|
.I6( `DATA_ROW_WIDTH'b0 ),
|
.I7( `DATA_ROW_WIDTH'b0 ),
|
.I7( `DATA_ROW_WIDTH'b0 ),
|
.I8( wSource0_Temp ),
|
.I8( wSource0_Temp ),
|
.O1( wSourceData0_Imm )
|
.O1( wSourceData0_Imm )
|
);
|
);
|
|
|
|
|
assign wReservationStationBusy = (~iEnable) |
|
assign wReservationStationBusy = (~iEnable) |
|
(
|
(
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_ADD ) && (iRStationBusy[ 0 ] && iRStationBusy[ 1 ])) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_ADD ) && (iRStationBusy[ 0 ] && iRStationBusy[ 1 ])) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_DIV ) && iRStationBusy[ 2 ]) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_DIV ) && iRStationBusy[ 2 ]) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_MUL ) && iRStationBusy[ 3 ]) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_MUL ) && iRStationBusy[ 3 ]) ||
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_OUT ) && iRStationBusy[ 6 ])
|
((iInstruction0[`INST_CODE_RNG] == `OPERATION_IO ) && iRStationBusy[ 6 ])
|
);
|
);
|
|
|
assign wBranchWithDependency = (iInstruction0[`INST_BRANCH_BIT] && (wSource0_Station != 0 || wSource1_Station != 0));
|
assign wBranchWithDependency = (iInstruction0[`INST_BRANCH_BIT] && (wSource0_Station != 0 || wSource1_Station != 0));
|
|
|
|
|
assign wOp = iInstruction0[`INST_CODE_RNG];
|
assign wOp = iInstruction0[`INST_CODE_RNG];
|
|
//The next equations calculate the reservations stations ID based on the current operation and the availability
|
|
//of the RS's (that is if a given statation is busy choose another suitable 1). To understand this equations
|
|
//please refer to the table TBD in the architecture specification document
|
|
|
assign wReservationStation[0] =
|
assign wReservationStation[0] =
|
(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 0 ]) |
|
(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 0 ]) |
|
(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]) |
|
(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]) |
|
(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]) |
|
(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]) |
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]);
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]);
|
|
|
assign wReservationStation[1] =
|
assign wReservationStation[1] =
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]) |
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]) |
|
(wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[5] ) |
|
(wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[5] ) |
|
(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & iRStationBusy[ 0 ] & ~iRStationBusy[1]) |
|
(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & iRStationBusy[ 0 ] & ~iRStationBusy[1]) |
|
(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]);
|
(~wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 2 ]);
|
|
|
|
|
assign wReservationStation[2] =
|
assign wReservationStation[2] =
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]) |
|
(~wOp[0] & wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 6 ]) |
|
(wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[5]) |
|
(wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[5]) |
|
(wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[3]) |
|
(wOp[0] & wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[3]) |
|
(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]);
|
(~wOp[0] & ~wOp[1] & wOp[2] & ~wOp[3] & ~iRStationBusy[ 4 ]);
|
|
|
assign wReservationStation[3] = 1'b0;
|
assign wReservationStation[3] = 1'b0;
|
|
|
//Sign control logic.
|
//Sign control logic.
|
//Only works for non literal opeations (INST_IMM == 0)
|
//Only works for non literal opeations (INST_IMM == 0)
|
wire [`ISSUE_SRCTAG_SIZE-1:0] wIssueTag0,wIssueTag1;
|
wire [`ISSUE_SRCTAG_SIZE-1:0] wIssueTag0,wIssueTag1;
|
|
|
assign wIssueTag0 = (iInstruction0[`INST_IMM]) ? `ISSUE_SRCTAG_SIZE'b0 : {iInstruction0[`INST_SRC0_SIGN_RNG],iInstruction0[`INST_SRC0_SWZL_RNG] };
|
assign wIssueTag0 = (iInstruction0[`INST_IMM]) ? `ISSUE_SRCTAG_SIZE'b0 : {iInstruction0[`INST_SRC0_SIGN_RNG],iInstruction0[`INST_SRC0_SWZL_RNG] };
|
assign wIssueTag1 = (iInstruction0[`INST_IMM]) ? `ISSUE_SRCTAG_SIZE'b0 : {iInstruction0[`INST_SRC1_SIGN_RNG],iInstruction0[`INST_SCR1_SWZL_RNG] };
|
assign wIssueTag1 = (iInstruction0[`INST_IMM]) ? `ISSUE_SRCTAG_SIZE'b0 : {iInstruction0[`INST_SRC1_SIGN_RNG],iInstruction0[`INST_SCR1_SWZL_RNG] };
|
|
|
wire [`DATA_ADDRESS_WIDTH -1:0] wDestinationIndex;
|
wire [`DATA_ADDRESS_WIDTH -1:0] wDestinationIndex;
|
|
|
|
|
`ifdef ADDRESSING_MODES_DISABLED
|
`ifdef ADDRESSING_MODES_DISABLED
|
assign wDestinationIndex = iInstruction0[`INST_DST_RNG];
|
assign wDestinationIndex = iInstruction0[`INST_DST_RNG];
|
`else
|
`else
|
|
|
wire [`DATA_ADDRESS_WIDTH -1:0] wDestIndexDisplaced,wDestinationIndex_NoIMM,wDestinationIndex_IMM;
|
wire [`DATA_ADDRESS_WIDTH -1:0] wDestIndexDisplaced,wDestinationIndex_NoIMM,wDestinationIndex_IMM;
|
|
|
assign wDestIndexDisplaced = (iInstruction0[`INST_DST_RNG] + iFrameOffset);
|
assign wDestIndexDisplaced = (iInstruction0[`INST_DST_RNG] + iFrameOffset);
|
assign wDestinationIndex_NoIMM = (iInstruction0[`INST_DEST_ZERO]) ? wDestIndexDisplaced : iInstruction0[`INST_DST_RNG];
|
assign wDestinationIndex_NoIMM = (iInstruction0[`INST_DEST_ZERO]) ? wDestIndexDisplaced : iInstruction0[`INST_DST_RNG];
|
|
|
|
wire [`WIDTH-1:0 ] wSource1_X;
|
|
assign wSource1_X = wSource1_Temp[`X_RNG];
|
|
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) DSTMUX
|
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) DSTMUX
|
(
|
(
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.Sel({iInstruction0[`INST_DEST_ZERO],iInstruction0[`INST_SRC1_DISPLACED],iInstruction0[`INST_SRC0_DISPLACED]}),
|
.I1(iInstruction0[`INST_DST_RNG]),
|
.I1(iInstruction0[`INST_DST_RNG]),
|
.I2(wDestIndexDisplaced),
|
.I2(wDestIndexDisplaced),
|
.I3(wDestIndexDisplaced),
|
.I3(wDestIndexDisplaced),
|
.I4(wDestIndexDisplaced + wSource1_Temp[`X_RNG]),
|
.I4(wDestIndexDisplaced + wSource1_X[`DATA_ADDRESS_WIDTH-1:0]),
|
.I5(iInstruction0[`INST_DST_RNG]),
|
.I5(iInstruction0[`INST_DST_RNG]),
|
.I6(wDestIndexDisplaced),
|
.I6(wDestIndexDisplaced),
|
.I7(iInstruction0[`INST_DST_RNG]),
|
.I7(iInstruction0[`INST_DST_RNG]),
|
.I8(wDestIndexDisplaced),
|
.I8(wDestIndexDisplaced),
|
.O1(wDestinationIndex_IMM)
|
.O1(wDestinationIndex_IMM)
|
);
|
);
|
|
|
|
|
assign wDestinationIndex = (iInstruction0[`INST_IMM]) ? wDestinationIndex_IMM : wDestinationIndex_NoIMM;
|
assign wDestinationIndex = (iInstruction0[`INST_IMM]) ? wDestinationIndex_IMM : wDestinationIndex_NoIMM;
|
`endif
|
`endif
|
|
|
assign oIssueBcast = (Reset | ~rIssueNow | wStall ) ? `ISSUE_PACKET_SIZE'b0 :
|
assign oIssueBcast = (Reset | ~rIssueNow | wStall ) ? `ISSUE_PACKET_SIZE'b0 :
|
{
|
{
|
wReservationStation,
|
wReservationStation,
|
wDestinationIndex,
|
wDestinationIndex,
|
iInstruction0[`INST_WE_RNG],
|
iInstruction0[`INST_WE_RNG],
|
iInstruction0[`INST_SCOP_RNG],
|
iInstruction0[`INST_SCOP_RNG],
|
wSource1_Station,
|
wSource1_Station,
|
wIssueTag1,
|
wIssueTag1,
|
wSourceData1,
|
wSourceData1,
|
wSource0_Station,
|
wSource0_Station,
|
wIssueTag0,
|
wIssueTag0,
|
wSourceData0
|
wSourceData0
|
|
|
};
|
};
|
|
|
endmodule
|
endmodule
|
|
|
