`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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module LOGIC_STATION
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module LOGIC_STATION
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [3:0] iId,
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input wire [3:0] iId,
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output wire [`COMMIT_PACKET_SIZE-1:0] oCommitData,
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output wire [`COMMIT_PACKET_SIZE-1:0] oCommitData,
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output wire oCommitResquest,
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output wire oCommitResquest,
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input wire iCommitGranted,
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input wire iCommitGranted,
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output wire oBusy
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output wire oBusy
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);
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);
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wire wExeDone;
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wire wExeDone;
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wire [2:0] wExeDoneTmp;
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wire [2:0] wExeDoneTmp;
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wire wRS1_2_ADD_Trigger;
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wire wRS1_2_ADD_Trigger;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
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wire [`DATA_ROW_WIDTH-1:0] wAND,wOR,wResult;
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wire [`DATA_ROW_WIDTH-1:0] wAND,wOR,wResult;
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wire [`SCALE_SIZE-1:0] wResultSelector_Temp;
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wire [1:0] wResultSelector;
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wire [1:0] wResultSelector;
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ReservationStation_1Cycle RS
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ReservationStation_1Cycle RS
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iIssueBus( iIssueBus ),
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.iIssueBus( iIssueBus ),
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.iCommitBus( iCommitBus ),
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.iCommitBus( iCommitBus ),
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.iMyId( iId ),
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.iMyId( iId ),
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.iExecutionDone( wExeDone ),
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.iExecutionDone( wExeDone ),
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.iResult( wResult ),
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.iResult( wResult ),
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.iCommitGranted( iCommitGranted ),
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.iCommitGranted( iCommitGranted ),
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.oSource1( wRS1_OperandA ),
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.oSource1( wRS1_OperandA ),
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.oSource0( wRS1_OperandB ),
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.oSource0( wRS1_OperandB ),
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.oBusy( oBusy ),
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.oBusy( oBusy ),
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.oTrigger( wRS1_2_ADD_Trigger ),
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.oTrigger( wRS1_2_ADD_Trigger ),
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.oCommitRequest( oCommitResquest ),
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.oCommitRequest( oCommitResquest ),
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.oId( oCommitData[`COMMIT_RSID_RNG] ),
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.oId( oCommitData[`COMMIT_RSID_RNG] ),
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.oWE( oCommitData[`COMMIT_WE_RNG] ),
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.oWE( oCommitData[`COMMIT_WE_RNG] ),
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.oDestination( oCommitData[`COMMIT_DST_RNG] ),
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.oDestination( oCommitData[`COMMIT_DST_RNG] ),
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.oScale(wResultSelector),
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.oScale( wResultSelector_Temp ),
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.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]})
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.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]})
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);
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);
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assign wResultSelector = wResultSelector_Temp[1:0];
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MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
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MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
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(
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(
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.Sel( wResultSelector ),
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.Sel( wResultSelector ),
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.I1( wAND ),
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.I1( wAND ),
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.I2( wOR ),
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.I2( wOR ),
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.I3(`DATA_ROW_WIDTH'b0),
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.I3(`DATA_ROW_WIDTH'b0),
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.I4(`DATA_ROW_WIDTH'b0),
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.I4(`DATA_ROW_WIDTH'b0),
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.O1(wResult)
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.O1(wResult)
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);
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);
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assign wExeDone = wExeDoneTmp[0] & wExeDoneTmp[1] & wExeDoneTmp[2];
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assign wExeDone = wExeDoneTmp[0] & wExeDoneTmp[1] & wExeDoneTmp[2];
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//TODO: For now I am only supporting AND, eventually you will have to use the MOD_ISSUE_SCALE_RNG
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//TODO: For now I am only supporting AND, eventually you will have to use the MOD_ISSUE_SCALE_RNG
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//to select between AND, OR, NOT, etc.
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//to select between AND, OR, NOT, etc.
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AND # (`WIDTH) AND_0
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AND # (`WIDTH) AND_0
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`X_RNG] ),
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.iA( wRS1_OperandA[`X_RNG] ),
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.iB( wRS1_OperandB[`X_RNG] ),
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.iB( wRS1_OperandB[`X_RNG] ),
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.oDone( wExeDoneTmp[0] ),
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.oDone( wExeDoneTmp[0] ),
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.oR( wAND[`X_RNG] )
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.oR( wAND[`X_RNG] )
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);
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);
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AND # (`WIDTH) AND_1
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AND # (`WIDTH) AND_1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`Y_RNG] ),
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.iA( wRS1_OperandA[`Y_RNG] ),
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.iB( wRS1_OperandB[`Y_RNG] ),
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.iB( wRS1_OperandB[`Y_RNG] ),
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.oDone( wExeDoneTmp[1] ),
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.oDone( wExeDoneTmp[1] ),
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.oR( wAND[`Y_RNG] )
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.oR( wAND[`Y_RNG] )
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);
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);
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AND # (`WIDTH) AND_2
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AND # (`WIDTH) AND_2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`Z_RNG] ),
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.iA( wRS1_OperandA[`Z_RNG] ),
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.iB( wRS1_OperandB[`Z_RNG] ),
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.iB( wRS1_OperandB[`Z_RNG] ),
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.oDone( wExeDoneTmp[2] ),
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.oDone( wExeDoneTmp[2] ),
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.oR( wAND[`Z_RNG] )
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.oR( wAND[`Z_RNG] )
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);
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);
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OR # (`WIDTH) OR_0
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OR # (`WIDTH) OR_0
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`X_RNG] ),
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.iA( wRS1_OperandA[`X_RNG] ),
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.iB( wRS1_OperandB[`X_RNG] ),
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.iB( wRS1_OperandB[`X_RNG] ),
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.oDone( wExeDoneTmp[0] ),
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.oDone( wExeDoneTmp[0] ),
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.oR( wOR[`X_RNG] )
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.oR( wOR[`X_RNG] )
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);
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);
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OR # (`WIDTH) OR_1
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OR # (`WIDTH) OR_1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`Y_RNG] ),
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.iA( wRS1_OperandA[`Y_RNG] ),
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.iB( wRS1_OperandB[`Y_RNG] ),
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.iB( wRS1_OperandB[`Y_RNG] ),
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.oDone( wExeDoneTmp[1] ),
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.oDone( wExeDoneTmp[1] ),
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.oR( wOR[`Y_RNG] )
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.oR( wOR[`Y_RNG] )
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);
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);
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OR # (`WIDTH) OR_2
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OR # (`WIDTH) OR_2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iTrigger( wRS1_2_ADD_Trigger ),
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.iA( wRS1_OperandA[`Z_RNG] ),
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.iA( wRS1_OperandA[`Z_RNG] ),
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.iB( wRS1_OperandB[`Z_RNG] ),
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.iB( wRS1_OperandB[`Z_RNG] ),
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.oDone( wExeDoneTmp[2] ),
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.oDone( wExeDoneTmp[2] ),
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.oR( wOR[`Z_RNG] )
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.oR( wOR[`Z_RNG] )
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);
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);
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endmodule
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endmodule
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