`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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//--------------------------------------------------------
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//--------------------------------------------------------
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`define MCU_STATE_AFTER_RESET 0
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`define MCU_STATE_AFTER_RESET 0
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`define MCU_WAIT_FOR_REQUEST 1
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`define MCU_WAIT_FOR_REQUEST 1
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`define MCU_TRANSFER_BLOCK_TO_VPCODEMEM 2
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`define MCU_TRANSFER_BLOCK_TO_VPCODEMEM 2
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`define MCU_TRANSFER_BLOCK_TO_VPDATAMEM 3
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`define MCU_TRANSFER_BLOCK_TO_VPDATAMEM 3
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`define MCU_INC_TRANSFER_BLOCK_ADDR 4
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`define MCU_INC_TRANSFER_BLOCK_ADDR 4
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module MemoryController # (parameter CORE_COUNT=`MAX_CORES )
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module MemoryController # (parameter CORE_COUNT=`MAX_CORES )
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire [`MCU_REQUEST_SIZE-1:0] iRequest,
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input wire [`MCU_REQUEST_SIZE-1:0] iRequest,
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output wire oMEM_ReadRequest,
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output wire oMEM_ReadRequest,
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output wire [`WB_WIDTH-1:0] oMEM_ReadAddress,
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output wire [`WB_WIDTH-1:0] oMEM_ReadAddress,
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input wire [`WB_WIDTH-1:0] iMEM_ReadData, //Data read from Main memory
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input wire [`WB_WIDTH-1:0] iMEM_ReadData, //Data read from Main memory
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output wire oPendingRequests, //Connected to FIFO
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output wire oPendingRequests, //Connected to FIFO
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output wire oFifoFull,
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output wire oFifoFull,
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output wire oFifoEmpty,
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output wire oFifoEmpty,
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input wire iMEM_DataAvailable,
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input wire iMEM_DataAvailable,
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//Wishbone signals
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//Wishbone signals
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire STB_O,
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output wire STB_O,
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output wire [CORE_COUNT-1:0] WE_O,
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output wire [CORE_COUNT-1:0] WE_O,
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output reg [1:0] TAG_O,
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output reg [1:0] TAG_O,
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output reg CYC_O,
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output reg CYC_O,
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output reg MST_O,
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output reg MST_O,
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input wire ACK_I
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input wire ACK_I
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);
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);
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reg rPopFifo;
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reg rPopFifo;
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wire [`MCU_REQUEST_SIZE-1:0] wCurrentRequest;
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wire [`MCU_REQUEST_SIZE-1:0] wCurrentRequest;
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wire wMEM_DataAvailable;
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wire wMEM_DataAvailable;
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reg rIncrementAddress;
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reg rIncrementAddress;
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wire [10:0] wCycCount;
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wire [10:0] wCycCount;
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reg rResetCycCount;
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reg rResetCycCount;
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reg rMEM_ReadRequest;
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reg rMEM_ReadRequest;
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wire w64BisTransmitted,w96BisTransmitted;
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wire w64BisTransmitted,w96BisTransmitted;
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wire wRequestDetected;
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wire wRequestDetected;
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wire[2:0] wStbCount;
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wire[2:0] wStbCount;
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reg rResetStbCount;
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reg rResetStbCount;
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wire wLastBlock;
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wire wLastBlock;
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wire wRequestType;
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wire wRequestType;
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wire wStall; //If ACK is not received afte STB_O wait for ACK
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wire wStall; //If ACK is not received afte STB_O wait for ACK
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assign DAT_O = iMEM_ReadData;
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assign DAT_O = iMEM_ReadData;
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assign wRequestDetected = (iRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG] != 0) ? 1'b1 : 1'b0;
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assign wRequestDetected = (iRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG] != 0) ? 1'b1 : 1'b0;
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assign oMEM_ReadRequest = rMEM_ReadRequest & ~iMEM_DataAvailable ;
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assign oMEM_ReadRequest = rMEM_ReadRequest & ~iMEM_DataAvailable ;
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//assign STB_O = wMEM_DataAvailable;
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//assign STB_O = wMEM_DataAvailable;
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wire wSTB_O;
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wire wSTB_O;
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UPCOUNTER_POSEDGE # (1) STB_O_UP
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UPCOUNTER_POSEDGE # (1) STB_O_UP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | wRequestDetected ),
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.Reset( Reset | wRequestDetected ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Enable( wMEM_DataAvailable | ACK_I ),
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.Enable( wMEM_DataAvailable | ACK_I ),
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.Q( wSTB_O )
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.Q( wSTB_O )
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);
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);
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assign STB_O = (wSTB_O );//| wMEM_DataAvailable);// & ~ACK_I;
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assign STB_O = (wSTB_O );//| wMEM_DataAvailable);// & ~ACK_I;
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assign w64BisTransmitted = (wStbCount == 3'd2) ? 1'b1 : 1'b0;
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assign w64BisTransmitted = (wStbCount == 3'd2) ? 1'b1 : 1'b0;
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assign w96BisTransmitted = (wStbCount == 3'd3) ? 1'b1 : 1'b0;
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assign w96BisTransmitted = (wStbCount == 3'd3) ? 1'b1 : 1'b0;
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assign wLastBlock = (wCycCount == wCurrentRequest[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG]) ? 1'b1 : 1'b0;
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assign wLastBlock = (wCycCount == wCurrentRequest[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG]) ? 1'b1 : 1'b0;
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assign wRequestType = wCurrentRequest[`MCU_COPYMEMBLOCK_TAG_BIT];
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assign wRequestType = wCurrentRequest[`MCU_COPYMEMBLOCK_TAG_BIT];
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UPCOUNTER_POSEDGE # (`WB_WIDTH) OUT_MEM_ADR_UP
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UPCOUNTER_POSEDGE # (`WB_WIDTH) OUT_MEM_ADR_UP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | wRequestDetected ),
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.Reset( Reset | wRequestDetected ),
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.Initial( iRequest[`MCU_COPYMEMBLOCKCMD_SRCOFF_RNG] ),
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.Initial( iRequest[`MCU_COPYMEMBLOCKCMD_SRCOFF_RNG] ),
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.Enable( ACK_I ),
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.Enable( ACK_I ),
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.Q( oMEM_ReadAddress )
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.Q( oMEM_ReadAddress )
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);
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);
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//Incomming requests are stored in the FIFO
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//Incomming requests are stored in the FIFO
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sync_fifo # (`MCU_REQUEST_SIZE,`MCU_FIFO_DEPTH ) IN_FIFO
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sync_fifo # (`MCU_REQUEST_SIZE,`MCU_FIFO_DEPTH ) IN_FIFO
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(
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(
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.clk( Clock ),
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.clk( Clock ),
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.reset( Reset ),
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.reset( Reset ),
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.din( iRequest ),
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.din( iRequest ),
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.wr_en( wRequestDetected ),
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.wr_en( wRequestDetected ),
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.rd_en( rPopFifo ),
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.rd_en( rPopFifo ),
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.dout( wCurrentRequest ),
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.dout( wCurrentRequest ),
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.empty( oFifoEmpty ),
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.empty( oFifoEmpty ),
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.full( oFifoFull )
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.full( oFifoFull )
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);
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);
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PULSE P1
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PULSE P1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( iMEM_DataAvailable ),
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.D( iMEM_DataAvailable ),
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.Q( wMEM_DataAvailable )
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.Q( wMEM_DataAvailable )
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);
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);
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UPCOUNTER_POSEDGE # (11) UP_CYC
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UPCOUNTER_POSEDGE # (11) UP_CYC
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rResetCycCount ),
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.Reset( Reset | rResetCycCount ),
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.Initial( 11'b1 ),
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.Initial( 11'b1 ),
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.Enable( rIncrementAddress ),
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.Enable( rIncrementAddress ),
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.Q( wCycCount )
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.Q( wCycCount )
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);
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);
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wire wStbPulse;
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wire wStbPulse;
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PULSE P2
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PULSE P2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( STB_O ),
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.D( STB_O ),
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.Q( wStbPulse )
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.Q( wStbPulse )
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);
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);
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UPCOUNTER_POSEDGE # (3) UP_STB
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UPCOUNTER_POSEDGE # (3) UP_STB
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rResetStbCount ),
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.Reset( Reset | rResetStbCount ),
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.Initial( 3'b0 ),
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.Initial( 3'b0 ),
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.Enable( wStbPulse ),
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.Enable( wStbPulse ),
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.Q( wStbCount )
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.Q( wStbCount )
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);
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);
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UPCOUNTER_POSEDGE # (`WB_WIDTH) UP_VPADDR
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UPCOUNTER_POSEDGE # (`WB_WIDTH) UP_VPADDR
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | wRequestDetected ),
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.Reset( Reset | wRequestDetected ),
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.Initial( {12'b0,iRequest[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG]} ),
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.Initial( {12'b0,iRequest[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG]} ),
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.Enable( rIncrementAddress ),
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.Enable( rIncrementAddress ),
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.Q( ADR_O )
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.Q( ADR_O )
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);
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);
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wire [`MCU_VPMASK_LEN-1:0] wWE_SelectMask;
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assign wWE_SelectMask = wCurrentRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG];
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SELECT_1_TO_N # ( $clog2(`MAX_CORES), `MAX_CORES ) WESEL
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SELECT_1_TO_N # ( $clog2(`MAX_CORES), `MAX_CORES ) WESEL
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(
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(
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.Sel(wCurrentRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG]),
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.Sel(wWE_SelectMask[$clog2(`MAX_CORES)-1:0]),
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.En( ~oFifoEmpty),
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.En( ~oFifoEmpty),
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.O( WE_O )
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.O( WE_O )
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);
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);
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reg [4:0] rCurrentState, rNextState;
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reg [4:0] rCurrentState, rNextState;
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//Next states logic and Reset sequence
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//Next states logic and Reset sequence
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always @(posedge Clock )
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always @(posedge Clock )
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begin
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begin
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if (Reset )
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if (Reset )
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rCurrentState <= `MCU_STATE_AFTER_RESET;
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rCurrentState <= `MCU_STATE_AFTER_RESET;
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else
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else
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rCurrentState <= rNextState;
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rCurrentState <= rNextState;
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end
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end
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always @ ( * )
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always @ ( * )
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begin
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begin
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case (rCurrentState)
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case (rCurrentState)
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//--------------------------------------
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//--------------------------------------
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`MCU_STATE_AFTER_RESET:
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`MCU_STATE_AFTER_RESET:
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begin
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begin
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rIncrementAddress = 1'b0;
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rIncrementAddress = 1'b0;
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TAG_O = `TAG_NULL;
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TAG_O = `TAG_NULL;
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MST_O = 1'b0;
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MST_O = 1'b0;
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CYC_O = 1'b0;
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CYC_O = 1'b0;
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rResetCycCount = 1'b1;
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rResetCycCount = 1'b1;
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rMEM_ReadRequest = 1'b0;
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rMEM_ReadRequest = 1'b0;
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rResetStbCount = 1'b0;
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rResetStbCount = 1'b0;
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rNextState = `MCU_WAIT_FOR_REQUEST;
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rNextState = `MCU_WAIT_FOR_REQUEST;
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end
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end
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//--------------------------------------
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//--------------------------------------
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/*
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/*
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Wait until a request becomes available
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Wait until a request becomes available
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*/
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*/
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`MCU_WAIT_FOR_REQUEST:
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`MCU_WAIT_FOR_REQUEST:
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begin
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begin
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rIncrementAddress = 1'b0;
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rIncrementAddress = 1'b0;
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TAG_O = `TAG_NULL;
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TAG_O = `TAG_NULL;
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MST_O = 1'b0;
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MST_O = 1'b0;
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CYC_O = 1'b0;
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CYC_O = 1'b0;
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rResetCycCount = 1'b1;
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rResetCycCount = 1'b1;
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rMEM_ReadRequest = 1'b0;
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rMEM_ReadRequest = 1'b0;
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rResetStbCount = 1'b1;
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rResetStbCount = 1'b1;
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if (~oFifoEmpty && wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM)
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if (~oFifoEmpty && wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM)
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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else if (~oFifoEmpty && wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM)
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else if (~oFifoEmpty && wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM)
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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else
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else
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rNextState = `MCU_WAIT_FOR_REQUEST;
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rNextState = `MCU_WAIT_FOR_REQUEST;
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end
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end
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//--------------------------------------
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//--------------------------------------
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//Code MEM is 64 bits
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//Code MEM is 64 bits
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`MCU_TRANSFER_BLOCK_TO_VPCODEMEM:
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`MCU_TRANSFER_BLOCK_TO_VPCODEMEM:
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begin
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begin
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rIncrementAddress = 1'b0;
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rIncrementAddress = 1'b0;
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TAG_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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TAG_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O = 1'b1;
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MST_O = 1'b1;
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CYC_O = 1'b1;
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CYC_O = 1'b1;
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rResetCycCount = 1'b0;
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rResetCycCount = 1'b0;
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rMEM_ReadRequest = ~w64BisTransmitted;
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rMEM_ReadRequest = ~w64BisTransmitted;
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rResetStbCount = 1'b0;
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rResetStbCount = 1'b0;
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if (w64BisTransmitted)
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if (w64BisTransmitted)
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rNextState = `MCU_INC_TRANSFER_BLOCK_ADDR;
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rNextState = `MCU_INC_TRANSFER_BLOCK_ADDR;
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else
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else
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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end
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end
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//--------------------------------------
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//--------------------------------------
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`MCU_TRANSFER_BLOCK_TO_VPDATAMEM:
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`MCU_TRANSFER_BLOCK_TO_VPDATAMEM:
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begin
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begin
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rPopFifo = 1'b0;
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rPopFifo = 1'b0;
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rIncrementAddress = 1'b0;
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rIncrementAddress = 1'b0;
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TAG_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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TAG_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O = 1'b1;
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MST_O = 1'b1;
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CYC_O = 1'b1;
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CYC_O = 1'b1;
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rResetCycCount = 1'b0;
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rResetCycCount = 1'b0;
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rMEM_ReadRequest = ~w96BisTransmitted;
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rMEM_ReadRequest = ~w96BisTransmitted;
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rResetStbCount = 1'b0;
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rResetStbCount = 1'b0;
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if (w96BisTransmitted)
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if (w96BisTransmitted)
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rNextState = `MCU_INC_TRANSFER_BLOCK_ADDR;
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rNextState = `MCU_INC_TRANSFER_BLOCK_ADDR;
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else
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else
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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end
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end
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//--------------------------------------
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//--------------------------------------
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`MCU_INC_TRANSFER_BLOCK_ADDR:
|
`MCU_INC_TRANSFER_BLOCK_ADDR:
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begin
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begin
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rPopFifo = wLastBlock;
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rPopFifo = wLastBlock;
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rIncrementAddress = ~wLastBlock;
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rIncrementAddress = ~wLastBlock;
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TAG_O = `TAG_NULL;
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TAG_O = `TAG_NULL;
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MST_O = 1'b1;
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MST_O = 1'b1;
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CYC_O = 1'b0;
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CYC_O = 1'b0;
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rResetCycCount = 1'b0;
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rResetCycCount = 1'b0;
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rMEM_ReadRequest = 1'b0;
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rMEM_ReadRequest = 1'b0;
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rResetStbCount = 1'b1;
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rResetStbCount = 1'b1;
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if (wLastBlock)
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if (wLastBlock)
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rNextState = `MCU_WAIT_FOR_REQUEST;
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rNextState = `MCU_WAIT_FOR_REQUEST;
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else if (wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM)
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else if (wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM)
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPCODEMEM;
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else if (wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM)
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else if (wRequestType == `MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM)
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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rNextState = `MCU_TRANSFER_BLOCK_TO_VPDATAMEM;
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else
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else
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rNextState = `MCU_WAIT_FOR_REQUEST; //Should never reach this!
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rNextState = `MCU_WAIT_FOR_REQUEST; //Should never reach this!
|
end
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end
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//--------------------------------------
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//--------------------------------------
|
default:
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default:
|
begin
|
begin
|
rPopFifo = 1'b0;
|
rPopFifo = 1'b0;
|
rIncrementAddress = 1'b0;
|
rIncrementAddress = 1'b0;
|
TAG_O = `TAG_NULL;
|
TAG_O = `TAG_NULL;
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MST_O = 1'b0;
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MST_O = 1'b0;
|
CYC_O = 1'b0;
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CYC_O = 1'b0;
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rResetCycCount = 1'b1;
|
rResetCycCount = 1'b1;
|
rMEM_ReadRequest = 1'b0;
|
rMEM_ReadRequest = 1'b0;
|
rResetStbCount = 1'b0;
|
rResetStbCount = 1'b0;
|
|
|
rNextState = `MCU_STATE_AFTER_RESET;
|
rNextState = `MCU_STATE_AFTER_RESET;
|
end
|
end
|
//--------------------------------------
|
//--------------------------------------
|
endcase
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endcase
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end
|
end
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|
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endmodule
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endmodule
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|
|
