`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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//--------------------------------------------------------
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//--------------------------------------------------------
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module THEIA
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module THEIA
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire [31:0] iMemReadData, //Data read from Main memory
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input wire [31:0] iMemReadData, //Data read from Main memory
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input wire iMemDataAvailable,
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input wire iMemDataAvailable,
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output wire [31:0] oMemReadAddress,
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output wire [31:0] oMemReadAddress,
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output wire oMEM_ReadRequest
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output wire oMEM_ReadRequest,
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input wire [`WB_WIDTH-1:0] TMDAT_I,
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input wire [`WB_WIDTH-1:0] TMADR_I,
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input wire TMWE_I,
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input wire [`MAX_TMEM_BANKS-1:0] TMSEL_I
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);
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);
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteAddress;
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteAddress;
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteData;
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wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteData;
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wire [`MAX_CORES-1:0] wMCU_2_VP_InstructionWriteEnable;
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wire [`MAX_CORES-1:0] wMCU_2_VP_InstructionWriteEnable;
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wire [`MCU_TAG_SIZE-1:0] wMCU_2_VP_Tag;
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wire [`MCU_TAG_SIZE-1:0] wMCU_2_VP_Tag;
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wire wMCU_2_VP_STB;
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wire wMCU_2_VP_STB;
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wire wMCU_2_VP_Cyc;
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wire wMCU_2_VP_Cyc;
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wire wMCU_2_VP_Mst;
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wire wMCU_2_VP_Mst;
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wire [`MAX_CORES-1:0] wVP_2_MCU_ACK;
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wire [`MAX_CORES-1:0] wVP_2_MCU_ACK;
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wire wVP_Slave_ACK;
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wire wVP_Slave_ACK;
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wire [`MCU_REQUEST_SIZE-1:0] wCP_2MCU_BlockCopyCommand;
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wire [`MCU_REQUEST_SIZE-1:0] wCP_2MCU_BlockCopyCommand;
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wire[`CBC_BUS_WIDTH-1:0] wCP_VP__ControlCommandBus;
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wire[`CBC_BUS_WIDTH-1:0] wCP_VP__ControlCommandBus;
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wire wMCU_2_CP__FIFOEmpty;
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wire wMCU_2_CP__FIFOEmpty;
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wire wOMem_WE[`MAX_CORES-1:0];
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wire wOMem_WE[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
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//CROSS-BAR wires
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wire [`MAX_TMEM_BANKS-1:0] wTMemWriteEnable;
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wire [(`MAX_TMEM_BANKS*`WB_WIDTH)-1:0] wCrossBarDataRow; //Horizontal grid Buses comming from each bank
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wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarDataCollumn; //Vertical grid buses comming from each core.
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wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarAdressCollumn; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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//
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//
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// The control processor
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// The control processor
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//
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//
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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ControlProcessor CP
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ControlProcessor CP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.oControlBus( wCP_VP__ControlCommandBus ),
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.oControlBus( wCP_VP__ControlCommandBus ),
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.iMCUFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.iMCUFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.oCopyBlockCommand( wCP_2MCU_BlockCopyCommand )
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.oCopyBlockCommand( wCP_2MCU_BlockCopyCommand )
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);
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);
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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//
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//
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// The control processor
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// The control processor
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//
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//
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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assign wVP_Slave_ACK = wVP_2_MCU_ACK[0] | wVP_2_MCU_ACK[1] | wVP_2_MCU_ACK[2] | wVP_2_MCU_ACK[3];
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assign wVP_Slave_ACK = wVP_2_MCU_ACK[0] | wVP_2_MCU_ACK[1] | wVP_2_MCU_ACK[2] | wVP_2_MCU_ACK[3];
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MemoryController #(`MAX_CORES) MCU
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MemoryController #(`MAX_CORES) MCU
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iRequest( wCP_2MCU_BlockCopyCommand ),
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.iRequest( wCP_2MCU_BlockCopyCommand ),
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.oMEM_ReadAddress( oMemReadAddress ),
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.oMEM_ReadAddress( oMemReadAddress ),
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.oMEM_ReadRequest( oMEM_ReadRequest ),
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.oMEM_ReadRequest( oMEM_ReadRequest ),
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.oFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.oFifoEmpty( wMCU_2_CP__FIFOEmpty ),
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.iMEM_ReadData( iMemReadData ),
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.iMEM_ReadData( iMemReadData ),
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.iMEM_DataAvailable( iMemDataAvailable ),
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.iMEM_DataAvailable( iMemDataAvailable ),
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.DAT_O( wMCU_2_VP_InstructionWriteData ),
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.DAT_O( wMCU_2_VP_InstructionWriteData ),
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.ADR_O( wMCU_2_VP_InstructionWriteAddress ),
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.ADR_O( wMCU_2_VP_InstructionWriteAddress ),
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.STB_O( wMCU_2_VP_STB ),
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.STB_O( wMCU_2_VP_STB ),
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.WE_O( wMCU_2_VP_InstructionWriteEnable ),
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.WE_O( wMCU_2_VP_InstructionWriteEnable ),
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.TAG_O( wMCU_2_VP_Tag ),
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.TAG_O( wMCU_2_VP_Tag ),
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.CYC_O( wMCU_2_VP_Cyc ),
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.CYC_O( wMCU_2_VP_Cyc ),
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.MST_O( wMCU_2_VP_Mst ),
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.MST_O( wMCU_2_VP_Mst ),
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.ACK_I( wVP_Slave_ACK )
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.ACK_I( wVP_Slave_ACK )
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);
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);
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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//
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//
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// The vector processors
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// The vector processors
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//
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//
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//////////////////////////////////////////////
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//////////////////////////////////////////////
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genvar i;
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genvar i;
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generate
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generate
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for (i = 0; i < `MAX_CORES; i = i +1)
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for (i = 0; i < `MAX_CORES; i = i +1)
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begin : VPX
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begin : VPX
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VectorProcessor VP
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VectorProcessor VP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iEnable( iEnable ),
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.iEnable( iEnable ),
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.iVPID( i+1 ),
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.iVPID( i+1 ),
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.iCpCommand( wCP_VP__ControlCommandBus ),
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.iCpCommand( wCP_VP__ControlCommandBus ),
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.MCU_STB_I( wMCU_2_VP_STB ),
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.MCU_STB_I( wMCU_2_VP_STB ),
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.MCU_WE_I( wMCU_2_VP_InstructionWriteEnable[i] ),
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.MCU_WE_I( wMCU_2_VP_InstructionWriteEnable[i] ),
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.MCU_DAT_I( wMCU_2_VP_InstructionWriteData ),
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.MCU_DAT_I( wMCU_2_VP_InstructionWriteData ),
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.MCU_ADR_I( wMCU_2_VP_InstructionWriteAddress ),
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.MCU_ADR_I( wMCU_2_VP_InstructionWriteAddress ),
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.MCU_TAG_I( wMCU_2_VP_Tag ),
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.MCU_TAG_I( wMCU_2_VP_Tag ),
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.MCU_ACK_O( wVP_2_MCU_ACK[i] ),
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.MCU_ACK_O( wVP_2_MCU_ACK[i] ),
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.MCU_MST_I( wMCU_2_VP_Mst ),
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.MCU_MST_I( wMCU_2_VP_Mst ),
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.MCU_CYC_I( wMCU_2_VP_Cyc ),
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.MCU_CYC_I( wMCU_2_VP_Cyc ),
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.OMEM_WE( wOMem_WE[i] ),
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.OMEM_WE( wOMem_WE[i] ),
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.OMEM_ADDR( wOMEM_Address[i] ),
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.OMEM_ADDR( wOMEM_Address[i] ),
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.OMEM_DATA( wOMEM_Dat[i] )
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.OMEM_DATA( wOMEM_Dat[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] )
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);
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);
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//////////////////////////////////////////////
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//
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// The OMEM
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//
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//////////////////////////////////////////////
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, `OMEM_SIZE ) OMEM
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, `OMEM_SIZE ) OMEM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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.iReadAddress0( wOMEM_Address[i] )
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.iReadAddress0( wOMEM_Address[i] )
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//.oDataOut0( wOMEM_Dat[i] )
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);
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);
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MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_TMEM_BANKS,`MAX_TMEM_BITS) MUXG1
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(
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.in_bus( wCrossBarDataRow ),
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.sel( wCoreBankSelect[ i ][0+:`MAX_TMEM_BITS] ),
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.out( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] )
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);
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//If there are "n" banks, memory location "X" would reside in bank number X mod n.
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//X mod 2^n == X & (2^n - 1)
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assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
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//Each core has 1 bank request slot
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//be 1 at any given point in time. All bits zero means,
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//we are not requesting to read from any memory bank.
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SELECT_1_TO_N # ( `WIDTH, `MAX_TMEM_BANKS ) READDRQ
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(
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.Sel(wCoreBankSelect[ i]),
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.En(wCORE_2_TMEM__Req[i]),
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.O(wBankReadRequest[i])
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);
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//The address coming from the core is virtual adress, meaning it assumes linear
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//address space, however, since memory is interleaved in a n-way memory we transform
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//virtual adress into physical adress (relative to the bank) like this
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//fadr = vadr / n = vadr >> log2(n)
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assign wCrossBarAdressCollumn[(i*`WB_WIDTH)+:`WB_WIDTH] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
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//Connect the granted signal to Arbiter of the Bank we want to read from
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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end // for
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end // for
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endgenerate
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endgenerate
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL
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(
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.Sel(TMSEL_I),
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.En(TMWE_I),
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.O(wTMemWriteEnable)
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);
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genvar Core,Bank;
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generate
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for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
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begin : BANK
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//The memory bank itself
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
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(
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.Clock( Clock ),
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.iWriteEnable( wTMemWriteEnable[Bank] ),
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.iWriteAddress( TMADR_I ),
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.iDataIn( TMDAT_I ),
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.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
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.oDataOut0( wCrossBarDataRow[(`WB_WIDTH*Bank)+:`WB_WIDTH] ) //Connect to the Row of the grid
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);
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//Arbiter will Round-Robin Cores attempting to read from the same Bank
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//at a given point in time
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wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
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Module_BusArbitrer ARB_TMEM
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
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.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
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.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.D(wBankReadGrantedDelay[Bank]),
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.Q(wBankReadGranted[Bank])
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);
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MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_CORES,`MAX_CORE_BITS) MUXG2
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(
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.in_bus( wCrossBarAdressCollumn ),
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.sel( wCurrentCoreSelected[ Bank ] ),
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.out( wCrossBarAddressRow[ Bank ] )
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);
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end
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endgenerate
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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endmodule
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endmodule
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