`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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`define CONTROL_PROCESSOR_OP_WIDTH 5
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`define CONTROL_PROCESSOR_ADDR_WIDTH 8
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`define CONTROL_PROCESSOR_ADDR_WIDTH 8
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`define CONTROL_PROCESSOR_ISSUE_CMD_RNG 24:0
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`define CONTROL_PROCESSOR_ISSUE_CMD_RNG 24:0
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`define CONTROL_PROCESSOR_INSTRUCTION_WIDTH 32
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`define CONTROL_PROCESSOR_INSTRUCTION_WIDTH 32
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`define CONTROL_PROCESSOR_INST_OP_RNG 31:24
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`define CONTROL_PROCESSOR_INST_OP_RNG 31:24
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`define CONTROL_PROCESSOR_INST_OP_DST_RNG 23:16
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`define CONTROL_PROCESSOR_INST_OP_DST_RNG 23:16
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`define CONTROL_PROCESSOR_INST_OP_SRC1_RNG 15:8
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`define CONTROL_PROCESSOR_INST_OP_SRC1_RNG 15:8
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`define CONTROL_PROCESSOR_INST_OP_SRC0_RNG 7:0
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`define CONTROL_PROCESSOR_INST_OP_SRC0_RNG 7:0
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`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
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`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
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`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
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`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
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`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_OP_SUB `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define CONTROL_PROCESSOR_OP_SUB `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define CONTROL_PROCESSOR_OP_AND `CONTROL_PROCESSOR_OP_WIDTH'd4
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`define CONTROL_PROCESSOR_OP_AND `CONTROL_PROCESSOR_OP_WIDTH'd4
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`define CONTROL_PROCESSOR_OP_OR `CONTROL_PROCESSOR_OP_WIDTH'd5
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`define CONTROL_PROCESSOR_OP_OR `CONTROL_PROCESSOR_OP_WIDTH'd5
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`define CONTROL_PROCESSOR_OP_BRANCH `CONTROL_PROCESSOR_OP_WIDTH'd6
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`define CONTROL_PROCESSOR_OP_BRANCH `CONTROL_PROCESSOR_OP_WIDTH'd6
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`define CONTROL_PROCESSOR_OP_BEQ `CONTROL_PROCESSOR_OP_WIDTH'd7
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`define CONTROL_PROCESSOR_OP_BEQ `CONTROL_PROCESSOR_OP_WIDTH'd7
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`define CONTROL_PROCESSOR_OP_BNE `CONTROL_PROCESSOR_OP_WIDTH'd8
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`define CONTROL_PROCESSOR_OP_BNE `CONTROL_PROCESSOR_OP_WIDTH'd8
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`define CONTROL_PROCESSOR_OP_BG `CONTROL_PROCESSOR_OP_WIDTH'd9
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`define CONTROL_PROCESSOR_OP_BG `CONTROL_PROCESSOR_OP_WIDTH'd9
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`define CONTROL_PROCESSOR_OP_BL `CONTROL_PROCESSOR_OP_WIDTH'd10
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`define CONTROL_PROCESSOR_OP_BL `CONTROL_PROCESSOR_OP_WIDTH'd10
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`define CONTROL_PROCESSOR_OP_BGE `CONTROL_PROCESSOR_OP_WIDTH'd11
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`define CONTROL_PROCESSOR_OP_BGE `CONTROL_PROCESSOR_OP_WIDTH'd11
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`define CONTROL_PROCESSOR_OP_BLE `CONTROL_PROCESSOR_OP_WIDTH'd12
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`define CONTROL_PROCESSOR_OP_BLE `CONTROL_PROCESSOR_OP_WIDTH'd12
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`define CONTROL_PROCESSOR_ASSIGN `CONTROL_PROCESSOR_OP_WIDTH'd13
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`define CONTROL_PROCESSOR_ASSIGN `CONTROL_PROCESSOR_OP_WIDTH'd13
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`define CONTROL_PROCESSOR_OP_COPYBLOCK `CONTROL_PROCESSOR_OP_WIDTH'd14
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`define CONTROL_PROCESSOR_OP_COPYBLOCK `CONTROL_PROCESSOR_OP_WIDTH'd14
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`define CONTROL_PROCESSOR_OP_EXIT `CONTROL_PROCESSOR_OP_WIDTH'd15
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`define CONTROL_PROCESSOR_OP_EXIT `CONTROL_PROCESSOR_OP_WIDTH'd15
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`define CONTROL_PROCESSOR_OP_NOT `CONTROL_PROCESSOR_OP_WIDTH'd16
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`define CONTROL_PROCESSOR_OP_NOT `CONTROL_PROCESSOR_OP_WIDTH'd16
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`define CONTROL_PROCESSOR_OP_SHL `CONTROL_PROCESSOR_OP_WIDTH'd17
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`define CONTROL_PROCESSOR_OP_SHL `CONTROL_PROCESSOR_OP_WIDTH'd17
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`define CONTROL_PROCESSOR_OP_SHR `CONTROL_PROCESSOR_OP_WIDTH'd18
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`define CONTROL_PROCESSOR_OP_SHR `CONTROL_PROCESSOR_OP_WIDTH'd18
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module ControlProcessor
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module ControlProcessor
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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output wire[`CBC_BUS_WIDTH-1:0] oControlBus,
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output wire[`CBC_BUS_WIDTH-1:0] oControlBus,
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input wire iMCUFifoEmpty,
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input wire iMCUFifoEmpty,
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output reg [`MCU_REQUEST_SIZE-1:0] oCopyBlockCommand
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output reg [`MCU_REQUEST_SIZE-1:0] oCopyBlockCommand
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);
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);
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wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wIP,wIP_temp;
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wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wIP,wIP_temp;
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reg rWriteEnable,rBranchTaken;
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reg rWriteEnable,rBranchTaken;
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reg [`CBC_BUS_WIDTH-1:0] rIssueCommand;
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reg [`CBC_BUS_WIDTH-1:0] rIssueCommand;
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wire [`CONTROL_PROCESSOR_INSTRUCTION_WIDTH-1:0] wInstruction;
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wire [`CONTROL_PROCESSOR_INSTRUCTION_WIDTH-1:0] wInstruction;
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wire [`CONTROL_PROCESSOR_OP_WIDTH-1:0] wOperation;
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wire [`CONTROL_PROCESSOR_OP_WIDTH-1:0] wOperation;
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reg [`WIDTH-1:0] rResult;
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reg [`WIDTH-1:0] rResult;
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wire [`WIDTH-1:0] wPrevResult;
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wire [`WIDTH-1:0] wPrevResult;
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wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination;
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wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination,wIPInitialValue;
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wire [`WIDTH-1:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
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wire [`WIDTH-1:0] wSourceData0,wSourceData1,wImmediateValue;
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assign oControlBus = rIssueCommand;
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assign oControlBus = rIssueCommand;
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RAM_SINGLE_READ_PORT # (`CONTROL_PROCESSOR_INSTRUCTION_WIDTH, `CONTROL_PROCESSOR_ADDR_WIDTH, 256) InstructionRam
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RAM_SINGLE_READ_PORT # (`CONTROL_PROCESSOR_INSTRUCTION_WIDTH, `CONTROL_PROCESSOR_ADDR_WIDTH, 256) InstructionRam
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( 1'b0 ),
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.iWriteEnable( 1'b0 ),
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.iReadAddress0( wIP ),
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.iReadAddress0( wIP ),
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.oDataOut0( wInstruction )
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.oDataOut0( wInstruction )
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);
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);
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wire [`WIDTH-1:0] wSourceData0_FromMem,wSourceData1_FromMem,wSourceData0_FromMem_Pre,wSourceData1_FromMem_Pre;
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wire [`WIDTH-1:0] wSourceData0_FromMem,wSourceData1_FromMem,wSourceData0_FromMem_Pre,wSourceData1_FromMem_Pre;
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RAM_DUAL_READ_PORT # (`WIDTH,`CONTROL_PROCESSOR_ADDR_WIDTH) DataRam
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RAM_DUAL_READ_PORT # (`WIDTH,`CONTROL_PROCESSOR_ADDR_WIDTH) DataRam
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( rWriteEnable ),
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.iWriteEnable( rWriteEnable ),
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.iReadAddress0( wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC0_RNG] ),
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.iReadAddress0( wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC0_RNG] ),
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.iReadAddress1( wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC1_RNG] ),
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.iReadAddress1( wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC1_RNG] ),
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.iWriteAddress( wDestination ),
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.iWriteAddress( wDestination ),
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.iDataIn( rResult ),
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.iDataIn( rResult ),
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.oDataOut0( wSourceData0_FromMem_Pre ),
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.oDataOut0( wSourceData0_FromMem_Pre ),
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.oDataOut1( wSourceData1_FromMem_Pre )
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.oDataOut1( wSourceData1_FromMem_Pre )
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);
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);
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wire [`WIDTH-1:0] wSprBlockDestination;
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wire [`WIDTH-1:0] wSprBlockDestination;
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH ) FFD_SPR_COREID
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH ) FFD_SPR_COREID
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(rWriteEnable && (wDestination == `CONTROL_PROCESSOR_REG_BLOCK_DST)),
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.Enable(rWriteEnable && (wDestination == `CONTROL_PROCESSOR_REG_BLOCK_DST)),
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.D(rResult),
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.D(rResult),
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.Q(wSprBlockDestination)
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.Q(wSprBlockDestination)
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);
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);
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assign wSourceData0_FromMem = (wSourceAddr0 == `CONTROL_PROCESSOR_REG_STATUS) ? { 30'b0,iMCUFifoEmpty} : wSourceData0_FromMem_Pre;
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assign wSourceData0_FromMem = (wSourceAddr0 == `CONTROL_PROCESSOR_REG_STATUS) ? { 30'b0,iMCUFifoEmpty} : wSourceData0_FromMem_Pre;
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assign wSourceData1_FromMem = (wSourceAddr1 == `CONTROL_PROCESSOR_REG_STATUS) ? { 30'b0,iMCUFifoEmpty} :wSourceData1_FromMem_Pre;
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assign wSourceData1_FromMem = (wSourceAddr1 == `CONTROL_PROCESSOR_REG_STATUS) ? { 30'b0,iMCUFifoEmpty} :wSourceData1_FromMem_Pre;
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assign wSourceData0 = ( wSourceAddr0 == wPrevDestination ) ? wPrevResult : wSourceData0_FromMem ;
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assign wSourceData0 = ( wSourceAddr0 == wPrevDestination ) ? wPrevResult : wSourceData0_FromMem ;
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assign wSourceData1 = ( wSourceAddr1 == wPrevDestination) ? wPrevResult : wSourceData1_FromMem ;
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assign wSourceData1 = ( wSourceAddr1 == wPrevDestination) ? wPrevResult : wSourceData1_FromMem ;
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assign wIPInitialValue = (Reset) ? `CONTROL_PROCESSOR_ADDR_WIDTH'b0 : wDestination;
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assign wIPInitialValue = (Reset) ? `CONTROL_PROCESSOR_ADDR_WIDTH'b0 : wDestination;
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UPCOUNTER_POSEDGE # (`CONTROL_PROCESSOR_ADDR_WIDTH) IP
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UPCOUNTER_POSEDGE # (`CONTROL_PROCESSOR_ADDR_WIDTH) IP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rBranchTaken ),
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.Reset( Reset | rBranchTaken ),
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.Initial( wIPInitialValue + 1 ),
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.Initial( wIPInitialValue + `CONTROL_PROCESSOR_ADDR_WIDTH'd1 ),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.Q( wIP_temp )
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.Q( wIP_temp )
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);
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);
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assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
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assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_OP_WIDTH ) FFD1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_OP_WIDTH ) FFD1
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_RNG]),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_RNG]),
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.Q(wOperation)
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.Q(wOperation)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD2
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(rResult),
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.D(rResult),
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.Q(wPrevResult)
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.Q(wPrevResult)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD255
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD255
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC0_RNG]),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC0_RNG]),
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.Q(wSourceAddr0)
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.Q(wSourceAddr0)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD3
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD3
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC1_RNG]),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_SRC1_RNG]),
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.Q(wSourceAddr1)
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.Q(wSourceAddr1)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD4
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD4
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_DST_RNG]),
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.D(wInstruction[`CONTROL_PROCESSOR_INST_OP_DST_RNG]),
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.Q(wDestination)
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.Q(wDestination)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD44
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `CONTROL_PROCESSOR_ADDR_WIDTH ) FFD44
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable(1'b1),
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.Enable(1'b1),
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.D(wDestination),
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.D(wDestination),
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.Q(wPrevDestination)
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.Q(wPrevDestination)
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);
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);
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assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
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assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
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always @ ( * )
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always @ ( * )
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begin
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begin
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case (wOperation)
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case (wOperation)
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_COPYBLOCK:
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`CONTROL_PROCESSOR_OP_COPYBLOCK:
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begin
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begin
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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oCopyBlockCommand =
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oCopyBlockCommand =
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{wSprBlockDestination[15:0],wSourceData1,wSourceData0[`MCU_COPYMEMBLOCK_TAG_BIT],wSourceData0[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG],wSourceData0[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG]};
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{wSprBlockDestination[15:0],wSourceData1,wSourceData0[`MCU_COPYMEMBLOCK_TAG_BIT],wSourceData0[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG],wSourceData0[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG]};
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rWriteEnable = 1'b0;
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rWriteEnable = 1'b0;
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rResult = 0;
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rResult = 0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_DELIVER_COMMAND:
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`CONTROL_PROCESSOR_OP_DELIVER_COMMAND:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = {wDestination[7:0],wSourceData1[7:0],wSourceData0[15:0]};
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rIssueCommand = {wDestination[7:0],wSourceData1[7:0],wSourceData0[15:0]};
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rWriteEnable = 1'b0;
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rWriteEnable = 1'b0;
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rResult = 0;
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rResult = 0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_NOP:
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`CONTROL_PROCESSOR_OP_NOP:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b0;
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rWriteEnable = 1'b0;
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rResult = 0;
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rResult = 0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_ADD:
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`CONTROL_PROCESSOR_OP_ADD:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b1;
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rWriteEnable = 1'b1;
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rResult = wSourceData1 + wSourceData0;
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rResult = wSourceData1 + wSourceData0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_SUB:
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`CONTROL_PROCESSOR_OP_SUB:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b1;
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rWriteEnable = 1'b1;
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rResult = wSourceData1 - wSourceData0;
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rResult = wSourceData1 - wSourceData0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_AND:
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`CONTROL_PROCESSOR_OP_AND:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b1;
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rWriteEnable = 1'b1;
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rResult = wSourceData1 & wSourceData0;
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rResult = wSourceData1 & wSourceData0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_SHL:
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`CONTROL_PROCESSOR_OP_SHL:
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begin
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begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b1;
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rWriteEnable = 1'b1;
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rResult = wSourceData1 << wSourceData0;
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rResult = wSourceData1 << wSourceData0;
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end
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end
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//-------------------------------------
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//-------------------------------------
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`CONTROL_PROCESSOR_OP_SHR:
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`CONTROL_PROCESSOR_OP_SHR:
|
begin
|
begin
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rIssueCommand = `CBC_BUS_WIDTH'b0;
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rBranchTaken = 1'b0;
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rBranchTaken = 1'b0;
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rWriteEnable = 1'b1;
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rWriteEnable = 1'b1;
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rResult = wSourceData1 >> wSourceData0;
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rResult = wSourceData1 >> wSourceData0;
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end
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end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_OR:
|
`CONTROL_PROCESSOR_OP_OR:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
rWriteEnable = 1'b1;
|
rWriteEnable = 1'b1;
|
rResult = wSourceData1 | wSourceData0;
|
rResult = wSourceData1 | wSourceData0;
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BLE:
|
`CONTROL_PROCESSOR_OP_BLE:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 <= wSourceData0 )
|
if (wSourceData1 <= wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BL:
|
`CONTROL_PROCESSOR_OP_BL:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 < wSourceData0 )
|
if (wSourceData1 < wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BG:
|
`CONTROL_PROCESSOR_OP_BG:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 > wSourceData0 )
|
if (wSourceData1 > wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BGE:
|
`CONTROL_PROCESSOR_OP_BGE:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 >= wSourceData0 )
|
if (wSourceData1 >= wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BEQ:
|
`CONTROL_PROCESSOR_OP_BEQ:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 == wSourceData0 )
|
if (wSourceData1 == wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BNE:
|
`CONTROL_PROCESSOR_OP_BNE:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
if (wSourceData1 != wSourceData0 )
|
if (wSourceData1 != wSourceData0 )
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
else
|
else
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_OP_BRANCH:
|
`CONTROL_PROCESSOR_OP_BRANCH:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
rBranchTaken = 1'b1;
|
rBranchTaken = 1'b1;
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
`CONTROL_PROCESSOR_ASSIGN:
|
`CONTROL_PROCESSOR_ASSIGN:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b1;
|
rWriteEnable = 1'b1;
|
rResult = wImmediateValue;
|
rResult = wImmediateValue;
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
|
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
default:
|
default:
|
begin
|
begin
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
oCopyBlockCommand = `MCU_REQUEST_SIZE'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rIssueCommand = `CBC_BUS_WIDTH'b0;
|
rWriteEnable = 1'b0;
|
rWriteEnable = 1'b0;
|
rResult = 0;
|
rResult = 0;
|
rBranchTaken = 1'b0;
|
rBranchTaken = 1'b0;
|
end
|
end
|
//-------------------------------------
|
//-------------------------------------
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
