/**********************************************************************************
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/**********************************************************************************
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Theaia, Ray Cast Programable graphic Processing Unit.
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Theaia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*******************************************************************************
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/*******************************************************************************
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Module Description:
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Module Description:
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This module defines constants that are going to be used
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This module defines constants that are going to be used
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all over the code. By now you have may noticed that all
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all over the code. By now you have may noticed that all
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constants are pre-compilation define directives. This is
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constants are pre-compilation define directives. This is
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for simulation perfomance reasons mainly.
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for simulation perfomance reasons mainly.
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*******************************************************************************/
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*******************************************************************************/
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`define THEIA_TOP uut
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`define THEIA_TOP uut
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`define CP_TOP `THEIA_TOP.CP
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`define CP_TOP `THEIA_TOP.CP
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`define VP_TOP `THEIA_TOP.VPX[ CVPID ].VP
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`define VP_TOP `THEIA_TOP.VPX[ CVPID ].VP
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`define CONTROL_PROCESSOR_OP_WIDTH 5
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`define CONTROL_PROCESSOR_OP_WIDTH 8
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`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
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`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
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`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
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`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
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`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_OP_SUB `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define CONTROL_PROCESSOR_OP_SUB `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define CONTROL_PROCESSOR_OP_AND `CONTROL_PROCESSOR_OP_WIDTH'd4
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`define CONTROL_PROCESSOR_OP_AND `CONTROL_PROCESSOR_OP_WIDTH'd4
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`define CONTROL_PROCESSOR_OP_OR `CONTROL_PROCESSOR_OP_WIDTH'd5
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`define CONTROL_PROCESSOR_OP_OR `CONTROL_PROCESSOR_OP_WIDTH'd5
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`define CONTROL_PROCESSOR_OP_BRANCH `CONTROL_PROCESSOR_OP_WIDTH'd6
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`define CONTROL_PROCESSOR_OP_BRANCH `CONTROL_PROCESSOR_OP_WIDTH'd6
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`define CONTROL_PROCESSOR_OP_BEQ `CONTROL_PROCESSOR_OP_WIDTH'd7
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`define CONTROL_PROCESSOR_OP_BEQ `CONTROL_PROCESSOR_OP_WIDTH'd7
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`define CONTROL_PROCESSOR_OP_BNE `CONTROL_PROCESSOR_OP_WIDTH'd8
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`define CONTROL_PROCESSOR_OP_BNE `CONTROL_PROCESSOR_OP_WIDTH'd8
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`define CONTROL_PROCESSOR_OP_BG `CONTROL_PROCESSOR_OP_WIDTH'd9
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`define CONTROL_PROCESSOR_OP_BG `CONTROL_PROCESSOR_OP_WIDTH'd9
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`define CONTROL_PROCESSOR_OP_BL `CONTROL_PROCESSOR_OP_WIDTH'd10
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`define CONTROL_PROCESSOR_OP_BL `CONTROL_PROCESSOR_OP_WIDTH'd10
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`define CONTROL_PROCESSOR_OP_BGE `CONTROL_PROCESSOR_OP_WIDTH'd11
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`define CONTROL_PROCESSOR_OP_BGE `CONTROL_PROCESSOR_OP_WIDTH'd11
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`define CONTROL_PROCESSOR_OP_BLE `CONTROL_PROCESSOR_OP_WIDTH'd12
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`define CONTROL_PROCESSOR_OP_BLE `CONTROL_PROCESSOR_OP_WIDTH'd12
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`define CONTROL_PROCESSOR_ASSIGN `CONTROL_PROCESSOR_OP_WIDTH'd13
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`define CONTROL_PROCESSOR_ASSIGN `CONTROL_PROCESSOR_OP_WIDTH'd13
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`define CONTROL_PROCESSOR_OP_COPYBLOCK `CONTROL_PROCESSOR_OP_WIDTH'd14
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`define CONTROL_PROCESSOR_OP_COPYBLOCK `CONTROL_PROCESSOR_OP_WIDTH'd14
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`define CONTROL_PROCESSOR_OP_EXIT `CONTROL_PROCESSOR_OP_WIDTH'd15
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`define CONTROL_PROCESSOR_OP_EXIT `CONTROL_PROCESSOR_OP_WIDTH'd15
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`define CONTROL_PROCESSOR_OP_NOT `CONTROL_PROCESSOR_OP_WIDTH'd16
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`define CONTROL_PROCESSOR_OP_NOT `CONTROL_PROCESSOR_OP_WIDTH'd16
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`define CONTROL_PROCESSOR_OP_SHL `CONTROL_PROCESSOR_OP_WIDTH'd17
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`define CONTROL_PROCESSOR_OP_SHL `CONTROL_PROCESSOR_OP_WIDTH'd17
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`define CONTROL_PROCESSOR_OP_SHR `CONTROL_PROCESSOR_OP_WIDTH'd18
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`define CONTROL_PROCESSOR_OP_SHR `CONTROL_PROCESSOR_OP_WIDTH'd18
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`define CONTROL_PROCESSOR_REG_STATUS `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_REG_STATUS `CONTROL_PROCESSOR_OP_WIDTH'd2
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`define CONTROL_PROCESSOR_REG_BLOCK_DST `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define CONTROL_PROCESSOR_REG_BLOCK_DST `CONTROL_PROCESSOR_OP_WIDTH'd3
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`define VPID_WIDTH 7
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`define VPID_WIDTH 7
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`define VP_COMMAND_START_MAIN_THREAD 0
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`define VP_COMMAND_START_MAIN_THREAD 0
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`define VP_COMMAND_STOP_MAIN_THREAD 1
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`define VP_COMMAND_STOP_MAIN_THREAD 1
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//`define VERILATOR 1
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//`define VERILATOR 1
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//`define CONTROL_BUS_WIDTH 32
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//`define CONTROL_BUS_WIDTH 32
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`define CBC_BUS_WIDTH 32
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`define CBC_BUS_WIDTH 32
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`define CP_MSG_ARGS_RNG 15:0
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`define CP_MSG_ARGS_RNG 15:0
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`define CP_MSG_OPERATION_RNG 23:16
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`define CP_MSG_OPERATION_RNG 23:16
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`define CP_MSG_DST_RNG 31:24
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`define CP_MSG_DST_RNG 31:24
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`define CP_MSG_BCAST 31
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`define CP_MSG_BCAST 31
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`define OMEM_SIZE 250000
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`define OMEM_SIZE 250000
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`define APR06 1
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`define APR06 1
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`define MCU_REQUEST_SIZE 81 //32 + 32 + 8 + 8
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`define MCU_REQUEST_SIZE 81 //32 + 32 + 8 + 8
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`define MCU_FIFO_DEPTH 8
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`define MCU_FIFO_DEPTH 8
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`define MCU_COPYMEMBLOCKCMD_DSTOFF_RNG 19:0//23:0
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`define MCU_COPYMEMBLOCKCMD_DSTOFF_RNG 19:0//23:0
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`define MCU_COPYMEMBLOCKCMD_BLKLEN_RNG 30:20//31:24
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`define MCU_COPYMEMBLOCKCMD_BLKLEN_RNG 30:20//31:24
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`define MCU_COPYMEMBLOCK_TAG_BIT 31
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`define MCU_COPYMEMBLOCK_TAG_BIT 31
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`define MCU_COPYMEMBLOCKCMD_SRCOFF_RNG 63:32
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`define MCU_COPYMEMBLOCKCMD_SRCOFF_RNG 63:32
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`define MCU_COPYMEMBLOCKCMD_VPMASK_RNG 79:64
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`define MCU_COPYMEMBLOCKCMD_VPMASK_RNG 79:64
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`define MCU_VPMASK_LEN (79-64)
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//`define MCU_REQUEST_TYPE_BIT 80 //See if it is CPBLOCKCOPY or VPCOMMAND
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//`define MCU_REQUEST_TYPE_BIT 80 //See if it is CPBLOCKCOPY or VPCOMMAND
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`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM 1'b1
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`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM 1'b1
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`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM 1'b0
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`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM 1'b0
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`define MCU_TAG_SIZE 2
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`define MCU_TAG_SIZE 2
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`define TAG_NULL 2'b00
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`define TAG_NULL 2'b00
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b10
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b10
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`define TAG_DATA_ADDRESS_TYPE 2'b01
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`define TAG_DATA_ADDRESS_TYPE 2'b01
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`define MAX_THREADS 2
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`define MAX_THREADS 2
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`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
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`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
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`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
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`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
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`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
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`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
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`define MAX_TMEM_BITS 2 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
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`define MAX_TMEM_BITS 2 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
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`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
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`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
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//Defnitions for the input file size (avoid nasty warnings about the size of the file being different from the
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//Defnitions for the input file size (avoid nasty warnings about the size of the file being different from the
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//size of the array which stores the file in verilog
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//size of the array which stores the file in verilog
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`define PARAMS_ARRAY_SIZE 43 //The maximum number of byte in this input file
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`define PARAMS_ARRAY_SIZE 43 //The maximum number of byte in this input file
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`define VERTEX_ARRAY_SIZE 7000 //The maximum number of byte in this input file
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`define VERTEX_ARRAY_SIZE 7000 //The maximum number of byte in this input file
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`define TEXTURE_BUFFER_SIZE 196608 //The maximum number of byte in this input file
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`define TEXTURE_BUFFER_SIZE 196608 //The maximum number of byte in this input file
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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//Verilog provides a `default_nettype none compiler directive. When
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//Verilog provides a `default_nettype none compiler directive. When
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//this directive is set, implicit data types are disabled, which will make any
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//this directive is set, implicit data types are disabled, which will make any
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//undeclared signal name a syntax error.This is very usefull to avoid annoying
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//undeclared signal name a syntax error.This is very usefull to avoid annoying
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//automatic 1 bit long wire declaration where you don't want them to be!
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//automatic 1 bit long wire declaration where you don't want them to be!
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`default_nettype none
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`default_nettype none
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//The clock cycle
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//The clock cycle
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`define CLOCK_CYCLE 5
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`define CLOCK_CYCLE 5
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`define CLOCK_PERIOD 10
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`define CLOCK_PERIOD 10
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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//Defines the Scale. This very important because it sets the fixed point precision.
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//Defines the Scale. This very important because it sets the fixed point precision.
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//The Scale defines the number bits that are used as the decimal part of the number.
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//The Scale defines the number bits that are used as the decimal part of the number.
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//The code has been written in such a way that allows you to change the value of the
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//The code has been written in such a way that allows you to change the value of the
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//Scale, so that it is possible to experiment with different scenarios. SCALE can be
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//Scale, so that it is possible to experiment with different scenarios. SCALE can be
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//no smaller that 1 and no bigger that WIDTH.
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//no smaller that 1 and no bigger that WIDTH.
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`define SCALE 17
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`define SCALE 17
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//The next section defines the length of the registers, buses and other structures,
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//The next section defines the length of the registers, buses and other structures,
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//do not change this valued unless you really know what you are doing (seriously!)
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//do not change this valued unless you really know what you are doing (seriously!)
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`define WIDTH 32
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`define WIDTH 32
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`define WB_WIDTH 32 //width of wish-bone buses
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`define WB_WIDTH 32 //width of wish-bone buses
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`define LONG_WIDTH 64
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`define LONG_WIDTH 64
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`define WB_SIMPLE_READ_CYCLE 0
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`define WB_SIMPLE_READ_CYCLE 0
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`define WB_SIMPLE_WRITE_CYCLE 1
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`define WB_SIMPLE_WRITE_CYCLE 1
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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`define OPERATION_NOP 4'b0000
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`define OPERATION_NOP 4'b0000
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`define OPERATION_ADD 4'b0001
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`define OPERATION_ADD 4'b0001
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`define OPERATION_DIV 4'b0010
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`define OPERATION_DIV 4'b0010
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`define OPERATION_MUL 4'b0011
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`define OPERATION_MUL 4'b0011
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`define OPERATION_SQRT 4'b0100
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`define OPERATION_SQRT 4'b0100
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`define OPERATION_LOGIC 4'b0101
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`define OPERATION_LOGIC 4'b0101
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`define OPERATION_OUT 4'b0110
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`define OPERATION_IO 4'b0110
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`define RS_ADD0 1 //001
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`define RS_ADD0 4'd1 //001
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`define RS_ADD1 2 //010
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`define RS_ADD1 4'd2 //010
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`define RS_DIV 3 //011
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`define RS_DIV 4'd3 //011
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`define RS_MUL 4 //100
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`define RS_MUL 4'd4 //100
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`define RS_SQRT 5 //101
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`define RS_SQRT 4'd5 //101
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`define RS_LOGIC 6 //110
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`define RS_LOGIC 4'd6 //110
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`define RS_IO 7 //111
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`define RS_IO 4'd7 //111
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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//Issue bus packet structure
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//Issue bus packet structure
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`define ISSUE_PACKET_SIZE 237 //The size of the packet
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`define ISSUE_PACKET_SIZE 237 //The size of the packet
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`define ISSUE_SRCTAG_SIZE 9
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`define ISSUE_SRCTAG_SIZE 9
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`define ISSUE_RSID_RNG 236:233 //4 bits
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`define ISSUE_RSID_RNG 236:233 //4 bits
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`define ISSUE_DST_RNG 232:225 //8 bits
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`define ISSUE_DST_RNG 232:225 //8 bits
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`define ISSUE_WE_RNG 224:222 //3 bits
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`define ISSUE_WE_RNG 224:222 //3 bits
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`define ISSUE_SCALE_OP 221
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`define ISSUE_SCALE_OP 221
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`define ISSUE_SCALER 220
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`define ISSUE_SCALER 220
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`define ISSUE_SCALE0 219
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`define ISSUE_SCALE0 219
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`define ISSUE_SCALE1 218
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`define ISSUE_SCALE1 218
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`define SCALE_SIZE 4
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`define SCALE_SIZE 4
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`define ISSUE_SCALE_RNG 221:218 //4 bits
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`define ISSUE_SCALE_RNG 221:218 //4 bits
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`define ISSUE_SRC1RS_RNG 217:214 //4 bits
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`define ISSUE_SRC1RS_RNG 217:214 //4 bits
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`define ISSUE_SIGN1_RNG 213:211 //3 bits
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`define ISSUE_SIGN1_RNG 213:211 //3 bits
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`define ISSUE_SWZZ1_RNG 210:205 //6 bits
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`define ISSUE_SWZZ1_RNG 210:205 //6 bits
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`define ISSUE_SRC1_DATA_RNG 204:109 //96 bits
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`define ISSUE_SRC1_DATA_RNG 204:109 //96 bits
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`define ISSUE_SRC0RS_RNG 108:105 //4 bits
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`define ISSUE_SRC0RS_RNG 108:105 //4 bits
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`define ISSUE_SIGN0_RNG 104:102 //3 bits
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`define ISSUE_SIGN0_RNG 104:102 //3 bits
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`define ISSUE_SWZZ0_RNG 101:96 //6 bits
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`define ISSUE_SWZZ0_RNG 101:96 //6 bits
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`define ISSUE_SRC0_DATA_RNG 95:0 //96 bits
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`define ISSUE_SRC0_DATA_RNG 95:0 //96 bits
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`define ISSUE_SRC1_TAG_RNG 213:205
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`define ISSUE_SRC1_TAG_RNG 213:205
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`define ISSUE_SRC0_TAG_RNG 104:96
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`define ISSUE_SRC0_TAG_RNG 104:96
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`define TAG_SIGNX 8
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`define TAG_SIGNX 8
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`define TAG_SIGNY 7
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`define TAG_SIGNY 7
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`define TAG_SIGNZ 6
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`define TAG_SIGNZ 6
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`define TAG_SWLX_RNG 5:4
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`define TAG_SWLX_RNG 5:4
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`define TAG_SWLY_RNG 3:2
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`define TAG_SWLY_RNG 3:2
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`define TAG_SWLZ_RNG 1:0
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`define TAG_SWLZ_RNG 1:0
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`define MOD_ISSUE_PACKET_SIZE 219
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`define MOD_ISSUE_PACKET_SIZE 219
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`define MOD_ISSUE_RSID_RNG 218:215
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`define MOD_ISSUE_RSID_RNG 218:215
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`define MOD_ISSUE_DST_RNG 214:207
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`define MOD_ISSUE_DST_RNG 214:207
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`define MOD_ISSUE_WE_RNG 206:204
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`define MOD_ISSUE_WE_RNG 206:204
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`define MOD_ISSUE_SCALE_RNG 203:200
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`define MOD_ISSUE_SCALE_RNG 203:200
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`define MOD_ISSUE_SRC1RS_RNG 199:196
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`define MOD_ISSUE_SRC1RS_RNG 199:196
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`define MOD_ISSUE_SRC1_DATA_RNG 195:100
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`define MOD_ISSUE_SRC1_DATA_RNG 195:100
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`define MOD_ISSUE_SRC0RS_RNG 99:96
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`define MOD_ISSUE_SRC0RS_RNG 99:96
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`define MOD_ISSUE_SRC0_DATA_RNG 95:0
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`define MOD_ISSUE_SRC0_DATA_RNG 95:0
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`define MOD_ISSUE_TAG1_RNG 8:0
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`define MOD_ISSUE_TAG1_RNG 8:0
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`define MOD_ISSUE_TAG0_RNG 8:0
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`define MOD_ISSUE_TAG0_RNG 8:0
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`define MOD_ISSUE_SRC_SIZE 87//`DATA_ROW_WIDTH-`ISSUE_SRCTAG_SIZE
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`define MOD_ISSUE_SRC_SIZE 87//`DATA_ROW_WIDTH-`ISSUE_SRCTAG_SIZE
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Commit bus packet structure
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// Commit bus packet structure
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`define COMMIT_PACKET_SIZE 111 // The size of the packet
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`define COMMIT_PACKET_SIZE 111 // The size of the packet
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`define COMMIT_RSID_RNG 110:107 //4 bits
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`define COMMIT_RSID_RNG 110:107 //4 bits
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`define COMMIT_WE_RNG 106:104 //3 bits
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`define COMMIT_WE_RNG 106:104 //3 bits
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`define COMMIT_WE_X 106
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`define COMMIT_WE_X 106
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`define COMMIT_WE_Y 105
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`define COMMIT_WE_Y 105
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`define COMMIT_WE_Z 104
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`define COMMIT_WE_Z 104
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`define COMMIT_DST_RNG 103:96 //8 bits
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`define COMMIT_DST_RNG 103:96 //8 bits
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`define COMMIT_DATA_RNG 95:0 //95 bits
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`define COMMIT_DATA_RNG 95:0 //95 bits
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`define COMMIT_X_RNG 95:64 //32 bits
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`define COMMIT_X_RNG 95:64 //32 bits
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`define COMMIT_Y_RNG 63:32 //32 bits
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`define COMMIT_Y_RNG 63:32 //32 bits
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`define COMMIT_Z_RNG 31:0 //32 bits
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`define COMMIT_Z_RNG 31:0 //32 bits
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`define COMMIT_SIGN_X 95
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`define COMMIT_SIGN_X 95
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`define COMMIT_SIGN_Y 63
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`define COMMIT_SIGN_Y 63
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`define COMMIT_SIGN_Z 31
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`define COMMIT_SIGN_Z 31
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`define MOD_COMMIT_PACKET_SIZE 114
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`define MOD_COMMIT_PACKET_SIZE 114
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`define MOD_SCALE_RNG 113:110
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`define MOD_SCALE_RNG 113:110
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`define MOD_SIGN_RNG 109:106
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`define MOD_SIGN_RNG 109:106
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`define MOD_COMMIT_TAG_RNG 109:100
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`define MOD_COMMIT_TAG_RNG 109:100
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`define MOD_COMMIT_SWZ_RNG 105:100
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`define MOD_COMMIT_SWZ_RNG 105:100
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`define MOD_COMMIT_RSID_RNG 99:96
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`define MOD_COMMIT_RSID_RNG 99:96
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`define MOD_COMMIT_DATA_RNG 95:0 //95 bits
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`define MOD_COMMIT_DATA_RNG 95:0 //95 bits
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`define OP_SIZE 16 //Size of the operation part of the instruction
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`define OP_SIZE 16 //Size of the operation part of the instruction
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`define OP_RNG 63:48 //Range of the operation part of the instruction
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`define OP_RNG 63:48 //Range of the operation part of the instruction
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`define OP_BIT_IMM 15
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`define OP_BIT_IMM 15
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//`define OP_WE_RNG 14:12
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//`define OP_WE_RNG 14:12
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`define OP_BREAK 11
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`define OP_BREAK 11
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`define OP_CODE_RNG 10:0
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`define OP_CODE_RNG 10:0
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Source0 structure
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// Source0 structure
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`define SRC0_SIZE 17
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`define SRC0_SIZE 17
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`define SRC0_RNG 16:0
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`define SRC0_RNG 16:0
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`define SRC0_ADDR_SIZE 8
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`define SRC0_ADDR_SIZE 8
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`define SRC0_SIGN_RNG 16:14
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`define SRC0_SIGN_RNG 16:14
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`define SRC0_SWZX_RNG 13:8
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`define SRC0_SWZX_RNG 13:8
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`define SRC0_ADDR_RNG 7:0
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`define SRC0_ADDR_RNG 7:0
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Source1 structure
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// Source1 structure
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`define SRC1_SIZE 17
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`define SRC1_SIZE 17
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`define SRC1_RNG 33:17
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`define SRC1_RNG 33:17
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`define SRC1_ADDR_SIZE 8
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`define SRC1_ADDR_SIZE 8
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`define SRC1_SIGN_RNG 16:14
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`define SRC1_SIGN_RNG 16:14
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`define SRC1_SWZX_RNG 13:8
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`define SRC1_SWZX_RNG 13:8
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`define SRC1_ADDR_RNG 7:0
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`define SRC1_ADDR_RNG 7:0
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`define NUMBER_OF_RSVR_STATIONS 7
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`define NUMBER_OF_RSVR_STATIONS 7
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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//Instruction structure
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//Instruction structure
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`define INST_IMM_RNG 31:0
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`define INST_IMM_RNG 31:0
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`define INST_SRC0_ADDR_RNG 7:0
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`define INST_SRC0_ADDR_RNG 7:0
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`define INST_SRC0_SWZL_RNG 13:8
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`define INST_SRC0_SWZL_RNG 13:8
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`define INST_SRC0_SWLZ_RNG 9:8
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`define INST_SRC0_SWLZ_RNG 9:8
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`define INST_SRC0_SWLY_RNG 11:10
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`define INST_SRC0_SWLY_RNG 11:10
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`define INST_SRC0_SWLX_RNG 13:12
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`define INST_SRC0_SWLX_RNG 13:12
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`define INST_SRC0_SIGN_RNG 16:14
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`define INST_SRC0_SIGN_RNG 16:14
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`define INST_SRC0_SIGNZ 14
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`define INST_SRC0_SIGNZ 14
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`define INST_SRC0_SIGNY 15
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`define INST_SRC0_SIGNY 15
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`define INST_SRC0_SIGNX 16
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`define INST_SRC0_SIGNX 16
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`define INST_SCR1_ADDR_RNG 24:17
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`define INST_SCR1_ADDR_RNG 24:17
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`define INST_SCR1_SWZL_RNG 30:25
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`define INST_SCR1_SWZL_RNG 30:25
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`define INST_SRC1_SWLZ_RNG 26:25
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`define INST_SRC1_SWLZ_RNG 26:25
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`define INST_SRC1_SWLY_RNG 28:27
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`define INST_SRC1_SWLY_RNG 28:27
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`define INST_SRC1_SWLX_RNG 30:29
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`define INST_SRC1_SWLX_RNG 30:29
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`define INST_SRC1_SIGN_RNG 33:31
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`define INST_SRC1_SIGN_RNG 33:31
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`define INST_SRC1_SIGNZ 31
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`define INST_SRC1_SIGNZ 31
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`define INST_SRC1_SIGNY 32
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`define INST_SRC1_SIGNY 32
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`define INST_SRC1_SIGNX 33
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`define INST_SRC1_SIGNX 33
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`define INST_DST_RNG 41:34
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`define INST_DST_RNG 41:34
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`define INST_WE_Z 42
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`define INST_WE_Z 42
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`define INST_WE_Y 43
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`define INST_WE_Y 43
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`define INST_WE_X 44
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`define INST_WE_X 44
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/*
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/*
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`define INST_RESERVED_RNG 46:42
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`define INST_RESERVED_RNG 46:42
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*/
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*/
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`define INST_SRC0_DISPLACED 45
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`define INST_SRC0_DISPLACED 45
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`define INST_SRC1_DISPLACED 46
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`define INST_SRC1_DISPLACED 46
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`define INST_DEST_ZERO 47
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`define INST_DEST_ZERO 47
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`define INST_ADDRMODE_RNG 47:45
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`define INST_ADDRMODE_RNG 47:45
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`define INST_CODE_RNG 50:48
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`define INST_CODE_RNG 50:48
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//`define INST_SCOP_RNG 53:51
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//`define INST_SCOP_RNG 53:51
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`define INST_RESERVED_RNG 51:53
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`define INST_RESERVED_RNG 51:53
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`define INST_BRANCH_OP_RNG 56:54
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`define INST_BRANCH_OP_RNG 56:54
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`define INST_BRANCH_BIT 57
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`define INST_BRANCH_BIT 57
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`define INST_EOF_RNG 58 //End of flow
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`define INST_EOF_RNG 58 //End of flow
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`define INST_SCOP_RNG 62:59
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`define INST_SCOP_RNG 62:59
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`define INST_IMM 63
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`define INST_IMM 63
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`define INST_WE_RNG 44:42
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`define INST_WE_RNG 44:42
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`define SCALE_SRC1_EN 0
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`define SCALE_SRC1_EN 0
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`define SCALE_SRC0_EN 1
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`define SCALE_SRC0_EN 1
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`define SCALE_SRCR_EN 2
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`define SCALE_SRCR_EN 2
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`define SCALE_OP 3
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`define SCALE_OP 3
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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//Compiler has to put the WE.x, WE.y and WE.z in zero (no write)
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//Compiler has to put the WE.x, WE.y and WE.z in zero (no write)
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//for the branch instructions
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//for the branch instructions
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`define BRANCH_ALWAYS 3'b000 //JMP
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`define BRANCH_ALWAYS 3'b000 //JMP
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`define BRANCH_IF_ZERO 3'b001 //==
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`define BRANCH_IF_ZERO 3'b001 //==
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`define BRANCH_IF_NOT_ZERO 3'b010 //!=
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`define BRANCH_IF_NOT_ZERO 3'b010 //!=
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`define BRANCH_IF_SIGN 3'b011 //<
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`define BRANCH_IF_SIGN 3'b011 //<
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`define BRANCH_IF_NOT_SIGN 3'b100 //>
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`define BRANCH_IF_NOT_SIGN 3'b100 //>
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`define BRANCH_IF_ZERO_OR_SIGN 3'b101 //<=
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`define BRANCH_IF_ZERO_OR_SIGN 3'b101 //<=
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`define BRANCH_IF_ZERO_OR_NOT_SIGN 3'b110 //>=
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`define BRANCH_IF_ZERO_OR_NOT_SIGN 3'b110 //>=
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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`define IO_OPERATION_OMWRITE 3'b0
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`define IO_OPERATION_TMREAD 3'b1
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`define SRC_RET_ADDR_RNG 95:64
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`define SRC_RET_ADDR_RNG 95:64
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`define X_RNG 95:64
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`define X_RNG 95:64
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`define Y_RNG 63:32
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`define Y_RNG 63:32
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`define Z_RNG 31:0
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`define Z_RNG 31:0
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`define ALU_BIT_ADD 0 //Bit 2 of operation is div bit
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`define ALU_BIT_ADD 0 //Bit 2 of operation is div bit
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`define ALU_BIT_ASSIGN 1 //Bit 2 of operation is div bit
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`define ALU_BIT_ASSIGN 1 //Bit 2 of operation is div bit
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`define ALU_BIT_DIV 2 //Bit 2 of operation is div bit
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`define ALU_BIT_DIV 2 //Bit 2 of operation is div bit
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`define ALU_BIT_MUL 3
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`define ALU_BIT_MUL 3
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`define OPERAND_BIT_X 15
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`define OPERAND_BIT_X 15
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`define OPERAND_BIT_Y 14
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`define OPERAND_BIT_Y 14
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`define OPERAND_BIT_Z 13
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`define OPERAND_BIT_Z 13
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`define NOP `INSTRUCTION_OP_LENGTH'b0_000000000000000
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`define NOP `INSTRUCTION_OP_LENGTH'b0_000000000000000
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`define ADD `INSTRUCTION_OP_LENGTH'b0_000000000000001
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`define ADD `INSTRUCTION_OP_LENGTH'b0_000000000000001
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`define AND `INSTRUCTION_OP_LENGTH'b0_000000000000010
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`define AND `INSTRUCTION_OP_LENGTH'b0_000000000000010
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`define DIV `INSTRUCTION_OP_LENGTH'b0_000000000000100
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`define DIV `INSTRUCTION_OP_LENGTH'b0_000000000000100
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`define MUL `INSTRUCTION_OP_LENGTH'b0_000000000001000
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`define MUL `INSTRUCTION_OP_LENGTH'b0_000000000001000
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//You can play around with the size of instuctions, but keep
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//You can play around with the size of instuctions, but keep
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//in mind that Bits 3 and 4 of the Operand have a special meaning
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//in mind that Bits 3 and 4 of the Operand have a special meaning
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//that is used for the jump familiy of instructions (see Documentation).
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//that is used for the jump familiy of instructions (see Documentation).
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//Also the MSB of Operand is used by the decoder to distinguish
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//Also the MSB of Operand is used by the decoder to distinguish
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//between Type I and Type II instructions.
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//between Type I and Type II instructions.
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`define INSTRUCTION_WIDTH 64
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`define INSTRUCTION_WIDTH 64
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//Defines the Lenght of Memory blocks
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//Defines the Lenght of Memory blocks
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//`define RESOURCE_VECTOR_SIZE 11
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//`define RESOURCE_VECTOR_SIZE 11
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`define INSTRUCTION_ADDR_WIDTH 16
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`define INSTRUCTION_ADDR_WIDTH 16
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`define DATA_ROW_WIDTH 96
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`define DATA_ROW_WIDTH 96
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`define DATA_ADDRESS_WIDTH 8//7
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`define DATA_ADDRESS_WIDTH 8//7
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`define ROM_ADDRESS_WIDTH 16
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`define ROM_ADDRESS_WIDTH 16
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`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
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`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
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`define SPR_CONTROL0 `DATA_ADDRESS_WIDTH'd2
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`define SPR_CONTROL0 `DATA_ADDRESS_WIDTH'd2
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`define SPR_CONTROL1 `DATA_ADDRESS_WIDTH'd3
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`define SPR_CONTROL1 `DATA_ADDRESS_WIDTH'd3
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`define SPR_TCONTROL0_MT_ENABLED 0
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`define SPR_TCONTROL0_MT_ENABLED 0
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`define SPR_TCONTROL0_T0_INST_OFFSET_RNG 16:1
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`define SPR_TCONTROL0_T0_INST_OFFSET_RNG 16:1
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`define C1 `DATA_ADDRESS_WIDTH'd64
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`define C1 `DATA_ADDRESS_WIDTH'd64
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`define C2 `DATA_ADDRESS_WIDTH'd65
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`define C2 `DATA_ADDRESS_WIDTH'd65
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`define C3 `DATA_ADDRESS_WIDTH'd66
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`define C3 `DATA_ADDRESS_WIDTH'd66
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`define C4 `DATA_ADDRESS_WIDTH'd67
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`define C4 `DATA_ADDRESS_WIDTH'd67
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`define C5 `DATA_ADDRESS_WIDTH'd68
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`define C5 `DATA_ADDRESS_WIDTH'd68
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`define C6 `DATA_ADDRESS_WIDTH'd69
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`define C6 `DATA_ADDRESS_WIDTH'd69
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`define C7 `DATA_ADDRESS_WIDTH'd70
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`define C7 `DATA_ADDRESS_WIDTH'd70
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`define R1 `DATA_ADDRESS_WIDTH'd71
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`define R1 `DATA_ADDRESS_WIDTH'd71
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`define R2 `DATA_ADDRESS_WIDTH'd72
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`define R2 `DATA_ADDRESS_WIDTH'd72
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`define R3 `DATA_ADDRESS_WIDTH'd73
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`define R3 `DATA_ADDRESS_WIDTH'd73
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`define R4 `DATA_ADDRESS_WIDTH'd74
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`define R4 `DATA_ADDRESS_WIDTH'd74
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`define R5 `DATA_ADDRESS_WIDTH'd75
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`define R5 `DATA_ADDRESS_WIDTH'd75
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`define R6 `DATA_ADDRESS_WIDTH'd76
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`define R6 `DATA_ADDRESS_WIDTH'd76
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`define R7 `DATA_ADDRESS_WIDTH'd77
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`define R7 `DATA_ADDRESS_WIDTH'd77
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`define R8 `DATA_ADDRESS_WIDTH'd78
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`define R8 `DATA_ADDRESS_WIDTH'd78
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`define R9 `DATA_ADDRESS_WIDTH'd79
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`define R9 `DATA_ADDRESS_WIDTH'd79
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`define R10 `DATA_ADDRESS_WIDTH'd80
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`define R10 `DATA_ADDRESS_WIDTH'd80
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`define R11 `DATA_ADDRESS_WIDTH'd81
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`define R11 `DATA_ADDRESS_WIDTH'd81
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`define R12 `DATA_ADDRESS_WIDTH'd82
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`define R12 `DATA_ADDRESS_WIDTH'd82
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