`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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//-----------------------------------------------------------
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//-----------------------------------------------------------
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module INCREMENT # ( parameter SIZE=`WIDTH )
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module INCREMENT # ( parameter SIZE=`WIDTH )
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire[SIZE-1:0] A,
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input wire[SIZE-1:0] A,
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output reg [SIZE-1:0] R
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output reg [SIZE-1:0] R
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);
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);
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always @ (posedge Clock)
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always @ (posedge Clock)
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begin
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begin
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R = A + 1;
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R = A + 1;
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end
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end
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endmodule
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endmodule
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//-----------------------------------------------------------
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//-----------------------------------------------------------
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module FixedAddSub
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module FixedAddSub
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire[`LONG_WIDTH-1:0] A,
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input wire[`LONG_WIDTH-1:0] A,
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input wire[`LONG_WIDTH-1:0] B,
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input wire[`LONG_WIDTH-1:0] B,
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output reg[`LONG_WIDTH-1:0] R,
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output reg[`LONG_WIDTH-1:0] R,
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input wire iOperation,
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input wire iOperation,
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input wire iInputReady, //Is the input data valid?
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input wire iInputReady, //Is the input data valid?
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output wire OutputReady //Our output data is ready!
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output wire OutputReady //Our output data is ready!
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);
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);
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reg MyOutputReady = 0;
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reg MyOutputReady = 0;
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wire [`LONG_WIDTH-1:0] wB;
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wire [`LONG_WIDTH-1:0] wB;
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assign wB = ( iOperation ) ? ~B + 1'b1 : B;
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assign wB = ( iOperation ) ? ~B + 1'b1 : B;
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//Output ready just take 1 cycle
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//Output ready just take 1 cycle
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//assign OutputReady = iInputReady;
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//assign OutputReady = iInputReady;
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FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay2
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FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iInputReady ),
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.D( iInputReady ),
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.Q( OutputReady )
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.Q( OutputReady )
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);
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);
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//-------------------------------
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//-------------------------------
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always @ (posedge Clock)
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always @ (posedge Clock)
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begin
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begin
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if (iInputReady == 1)
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if (iInputReady == 1)
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begin
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begin
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R = ( A + wB );
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R = ( A + wB );
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end
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end
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else
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else
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begin
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begin
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R = 64'hFFFFFFFF;
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R = 64'hFFFFFFFF;
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end
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end
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end // always
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end // always
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endmodule
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endmodule
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