`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "aDefinitions.v"
|
`include "aDefinitions.v"
|
|
|
|
//Square Root State Machine Constants
|
|
`define SQUARE_ROOT_LOOP 1
|
|
`define WRITE_SQUARE_ROOT_RESULT 2
|
|
|
|
|
`define SR_AFTER_RESET_STATE 0
|
`define SR_AFTER_RESET_STATE 0
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
/*
|
/*
|
|
|
Calcualtes the SquareRoot of a Fixed Point Number
|
Calcualtes the SquareRoot of a Fixed Point Number
|
Input: Q32.32
|
Input: Q32.32
|
Output: Q16.16
|
Output: Q16.16
|
Notice that the result has half the precicion as the operands!!
|
Notice that the result has half the precicion as the operands!!
|
*/
|
*/
|
module FixedPointSquareRoot
|
module FixedPointSquareRoot
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[`LONG_WIDTH-1:0] Operand,
|
input wire[`LONG_WIDTH-1:0] Operand,
|
input wire iInputReady,
|
input wire iInputReady,
|
output reg OutputReady,
|
output reg OutputReady,
|
output reg [`WIDTH-1:0] Result
|
output reg [`WIDTH-1:0] Result
|
);
|
);
|
|
|
reg[63:0] x;
|
reg[63:0] x;
|
reg[0:`WIDTH-1] group,sum,diff;
|
reg[0:`WIDTH-1] group,sum,diff;
|
reg[0:`WIDTH-1] temp1,temp2;
|
reg[0:`WIDTH-1] temp1,temp2;
|
reg [5:0] CurrentState, NextState;
|
reg [5:0] CurrentState, NextState;
|
|
|
reg myInputReady;
|
reg myInputReady;
|
|
|
//----------------------------------------
|
//----------------------------------------
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
myInputReady = iInputReady;
|
myInputReady = iInputReady;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
//Next states logic
|
//Next states logic
|
always @(negedge Clock)
|
always @(negedge Clock)
|
begin
|
begin
|
if( Reset!=1 )
|
if( Reset!=1 )
|
CurrentState = NextState;
|
CurrentState = NextState;
|
else
|
else
|
CurrentState = `SR_AFTER_RESET_STATE;
|
CurrentState = `SR_AFTER_RESET_STATE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
begin
|
begin
|
case (CurrentState)
|
case (CurrentState)
|
//----------------------------------------
|
//----------------------------------------
|
`SR_AFTER_RESET_STATE:
|
`SR_AFTER_RESET_STATE:
|
begin
|
begin
|
OutputReady = 0;
|
OutputReady = 0;
|
Result = 0;
|
Result = 0;
|
sum = 0;
|
sum = 0;
|
diff = 0;
|
diff = 0;
|
group=32; //WAS 16
|
group=32; //WAS 16
|
x = 0;
|
x = 0;
|
if ( myInputReady == 1 )
|
if ( myInputReady == 1 )
|
begin
|
begin
|
// x[31:0] = Operand;
|
// x[31:0] = Operand;
|
x = Operand;
|
x = Operand;
|
x = x << `SCALE;
|
x = x << `SCALE;
|
NextState = `SQUARE_ROOT_LOOP;
|
NextState = `SQUARE_ROOT_LOOP;
|
end else
|
end else
|
NextState = `SR_AFTER_RESET_STATE;
|
NextState = `SR_AFTER_RESET_STATE;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`SQUARE_ROOT_LOOP:
|
`SQUARE_ROOT_LOOP:
|
begin
|
begin
|
|
|
|
|
|
|
sum = sum << 1;
|
sum = sum << 1;
|
sum = sum + 1;
|
sum = sum + 1;
|
temp1 = diff << 2;
|
temp1 = diff << 2;
|
//diff = diff + (x>>(group*2)) &3;
|
//diff = diff + (x>>(group*2)) &3;
|
temp2 = group << 1; //group * 2 ??
|
temp2 = group << 1; //group * 2 ??
|
diff = temp1 + ((x >> temp2) &3);
|
diff = temp1 + ((x >> temp2) &3);
|
|
|
if (sum > diff)
|
if (sum > diff)
|
begin
|
begin
|
sum = sum -1;
|
sum = sum -1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Result = Result + (1<<group);
|
Result = Result + (1<<group);
|
diff = diff - sum;
|
diff = diff - sum;
|
sum = sum + 1;
|
sum = sum + 1;
|
end//if
|
end//if
|
|
|
|
|
if ( group != 0 )
|
if ( group != 0 )
|
begin
|
begin
|
group = group - 1;
|
group = group - 1;
|
NextState = `SQUARE_ROOT_LOOP;
|
NextState = `SQUARE_ROOT_LOOP;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
NextState = `WRITE_SQUARE_ROOT_RESULT;
|
NextState = `WRITE_SQUARE_ROOT_RESULT;
|
|
|
end
|
end
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`WRITE_SQUARE_ROOT_RESULT:
|
`WRITE_SQUARE_ROOT_RESULT:
|
begin
|
begin
|
OutputReady = 1;
|
OutputReady = 1;
|
NextState = (iInputReady == 0) ?
|
NextState = (iInputReady == 0) ?
|
`SR_AFTER_RESET_STATE : `WRITE_SQUARE_ROOT_RESULT;
|
`SR_AFTER_RESET_STATE : `WRITE_SQUARE_ROOT_RESULT;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
endcase
|
endcase
|
end //always
|
end //always
|
endmodule
|
endmodule
|
|
|
