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| Rev 93 |
Rev 128 |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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module ControlRegister
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module ControlRegister
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire[15:0] iControlRegister,
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input wire[15:0] iControlRegister,
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output wire[15:0] oControlRegister
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output wire[15:0] oControlRegister
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);
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);
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reg [15:0] rControlRegister;
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reg [15:0] rControlRegister;
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assign oControlRegister = rControlRegister;
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assign oControlRegister = rControlRegister;
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always @ (posedge Clock)
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always @ (posedge Clock)
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begin
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begin
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if ( Reset )
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if ( Reset )
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rControlRegister <= 16'b0;
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rControlRegister <= 16'b0;
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else
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else
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begin
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begin
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rControlRegister <= iControlRegister;
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rControlRegister <= iControlRegister;
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end
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end
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end
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end
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endmodule
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endmodule
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