`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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module SWAP_MEM # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 )
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module SWAP_MEM # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 )
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(
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(
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input wire Clock,
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input wire Clock,
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input wire iSelect,
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input wire iSelect,
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input wire iWriteEnableA,
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input wire iWriteEnableA,
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input wire[ADDR_WIDTH-1:0] iReadAddressA0,
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input wire[ADDR_WIDTH-1:0] iReadAddressA0,
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input wire[ADDR_WIDTH-1:0] iReadAddressA1,
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input wire[ADDR_WIDTH-1:0] iReadAddressA1,
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input wire[ADDR_WIDTH-1:0] iWriteAddressA,
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input wire[ADDR_WIDTH-1:0] iWriteAddressA,
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input wire[DATA_WIDTH-1:0] iDataInA,
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input wire[DATA_WIDTH-1:0] iDataInA,
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output wire [DATA_WIDTH-1:0] oDataOutA0,
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output wire [DATA_WIDTH-1:0] oDataOutA0,
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output wire [DATA_WIDTH-1:0] oDataOutA1,
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output wire [DATA_WIDTH-1:0] oDataOutA1,
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input wire iWriteEnableB,
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input wire iWriteEnableB,
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input wire[ADDR_WIDTH-1:0] iReadAddressB0,
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input wire[ADDR_WIDTH-1:0] iReadAddressB0,
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input wire[ADDR_WIDTH-1:0] iReadAddressB1,
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input wire[ADDR_WIDTH-1:0] iReadAddressB1,
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input wire[ADDR_WIDTH-1:0] iWriteAddressB,
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input wire[ADDR_WIDTH-1:0] iWriteAddressB,
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input wire[DATA_WIDTH-1:0] iDataInB,
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input wire[DATA_WIDTH-1:0] iDataInB,
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output wire [DATA_WIDTH-1:0] oDataOutB0,
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output wire [DATA_WIDTH-1:0] oDataOutB0,
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output wire [DATA_WIDTH-1:0] oDataOutB1
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output wire [DATA_WIDTH-1:0] oDataOutB1
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);
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);
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wire wWriteEnableA;
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wire wWriteEnableA;
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wire[ADDR_WIDTH-1:0] wReadAddressA0;
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wire[ADDR_WIDTH-1:0] wReadAddressA0;
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wire[ADDR_WIDTH-1:0] wReadAddressA1;
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wire[ADDR_WIDTH-1:0] wReadAddressA1;
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wire[ADDR_WIDTH-1:0] wWriteAddressA;
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wire[ADDR_WIDTH-1:0] wWriteAddressA;
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wire[DATA_WIDTH-1:0] wDataInA;
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wire[DATA_WIDTH-1:0] wDataInA;
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wire [DATA_WIDTH-1:0] wDataOutA0;
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wire [DATA_WIDTH-1:0] wDataOutA0;
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wire [DATA_WIDTH-1:0] wDataOutA1;
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wire [DATA_WIDTH-1:0] wDataOutA1;
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wire wWriteEnableB;
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wire wWriteEnableB;
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wire[ADDR_WIDTH-1:0] wReadAddressB0;
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wire[ADDR_WIDTH-1:0] wReadAddressB0;
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wire[ADDR_WIDTH-1:0] wReadAddressB1;
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wire[ADDR_WIDTH-1:0] wReadAddressB1;
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wire[ADDR_WIDTH-1:0] wWriteAddressB;
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wire[ADDR_WIDTH-1:0] wWriteAddressB;
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wire[DATA_WIDTH-1:0] wDataInB;
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wire[DATA_WIDTH-1:0] wDataInB;
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wire [DATA_WIDTH-1:0] wDataOutB0;
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wire [DATA_WIDTH-1:0] wDataOutB0;
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wire [DATA_WIDTH-1:0] wDataOutB1;
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wire [DATA_WIDTH-1:0] wDataOutB1;
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assign wWriteEnableA = ( iSelect ) ? iWriteEnableA : iWriteEnableB;
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assign wWriteEnableA = ( iSelect ) ? iWriteEnableA : iWriteEnableB;
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assign wWriteEnableB = ( ~iSelect ) ? iWriteEnableA : iWriteEnableB;
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assign wWriteEnableB = ( ~iSelect ) ? iWriteEnableA : iWriteEnableB;
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assign wReadAddressA0 = ( iSelect ) ? iReadAddressA0 : iReadAddressB0;
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assign wReadAddressA0 = ( iSelect ) ? iReadAddressA0 : iReadAddressB0;
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assign wReadAddressB0 = ( ~iSelect ) ? iReadAddressA0 : iReadAddressB0;
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assign wReadAddressB0 = ( ~iSelect ) ? iReadAddressA0 : iReadAddressB0;
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assign wReadAddressA1 = ( iSelect ) ? iReadAddressA1 : iReadAddressB1;
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assign wReadAddressA1 = ( iSelect ) ? iReadAddressA1 : iReadAddressB1;
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assign wReadAddressB1 = ( ~iSelect ) ? iReadAddressA1 : iReadAddressB1;
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assign wReadAddressB1 = ( ~iSelect ) ? iReadAddressA1 : iReadAddressB1;
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assign wWriteAddressA = ( iSelect ) ? iWriteAddressA : iWriteAddressB;
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assign wWriteAddressA = ( iSelect ) ? iWriteAddressA : iWriteAddressB;
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assign wWriteAddressB = ( ~iSelect ) ? iWriteAddressA : iWriteAddressB;
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assign wWriteAddressB = ( ~iSelect ) ? iWriteAddressA : iWriteAddressB;
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assign wDataInA = ( iSelect ) ? iDataInA : iDataInB;
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assign wDataInA = ( iSelect ) ? iDataInA : iDataInB;
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assign wDataInB = ( ~iSelect ) ? iDataInA : iDataInB;
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assign wDataInB = ( ~iSelect ) ? iDataInA : iDataInB;
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assign oDataOutA0 = ( iSelect ) ? wDataOutA0 : wDataOutB0;
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assign oDataOutA0 = ( iSelect ) ? wDataOutA0 : wDataOutB0;
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assign oDataOutB0 = ( ~iSelect ) ? wDataOutA0 : wDataOutB0;
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assign oDataOutB0 = ( ~iSelect ) ? wDataOutA0 : wDataOutB0;
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assign oDataOutA1 = ( iSelect ) ? wDataOutA1 : wDataOutB1;
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assign oDataOutA1 = ( iSelect ) ? wDataOutA1 : wDataOutB1;
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assign oDataOutB1 = ( ~iSelect ) ? wDataOutA1 : wDataOutB1;
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assign oDataOutB1 = ( ~iSelect ) ? wDataOutA1 : wDataOutB1;
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RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_A
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RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_A
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( wWriteEnableA ),
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.iWriteEnable( wWriteEnableA ),
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.iReadAddress0( wReadAddressA0 ),
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.iReadAddress0( wReadAddressA0 ),
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.iReadAddress1( wReadAddressA1 ),
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.iReadAddress1( wReadAddressA1 ),
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.iWriteAddress( wWriteAddressA ),
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.iWriteAddress( wWriteAddressA ),
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.iDataIn( wDataInA ),
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.iDataIn( wDataInA ),
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.oDataOut0( wDataOutA0 ),
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.oDataOut0( wDataOutA0 ),
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.oDataOut1( wDataOutA1 )
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.oDataOut1( wDataOutA1 )
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);
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);
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RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_B
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RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_B
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( wWriteEnableB ),
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.iWriteEnable( wWriteEnableB ),
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.iReadAddress0( wReadAddressB0 ),
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.iReadAddress0( wReadAddressB0 ),
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.iReadAddress1( wReadAddressB1 ),
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.iReadAddress1( wReadAddressB1 ),
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.iWriteAddress( wWriteAddressB ),
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.iWriteAddress( wWriteAddressB ),
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.iDataIn( wDataInB ),
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.iDataIn( wDataInB ),
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.oDataOut0( wDataOutB0 ),
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.oDataOut0( wDataOutB0 ),
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.oDataOut1( wDataOutB1 )
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.oDataOut1( wDataOutB1 )
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);
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);
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endmodule
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endmodule
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