/*
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/*
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Fixed point Multiplication Module Qm.n
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Fixed point Multiplication Module Qm.n
|
C = (A << n) / B
|
C = (A << n) / B
|
|
|
*/
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*/
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|
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// serial_divide_uu.v -- Serial division module
|
// serial_divide_uu.v -- Serial division module
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//
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//
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//
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//
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// Description: See description below (which suffices for IP core
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// Description: See description below (which suffices for IP core
|
// specification document.)
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// specification document.)
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//
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//
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG (this Verilog version)
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// Copyright (C) 2002 John Clayton and OPENCORES.ORG (this Verilog version)
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//
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//
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// This source file may be used and distributed without restriction provided
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// This source file may be used and distributed without restriction provided
|
// that this copyright statement is not removed from the file and that any
|
// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// derivative work contains the original copyright notice and the associated
|
// disclaimer.
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// disclaimer.
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//
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//
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// This source file is free software; you can redistribute it and/or modify
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
|
// This source is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
|
// License for more details.
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// License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
|
// You should have received a copy of the GNU Lesser General Public License
|
// along with this source.
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// Author: John Clayton
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// Author: John Clayton
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// Date : Jan. 30, 2003
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// Date : Jan. 30, 2003
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// Update: Jan. 30, 2003 Copied this file from "vga_crosshair.v"
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// Update: Jan. 30, 2003 Copied this file from "vga_crosshair.v"
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// Stripped out extraneous stuff.
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// Stripped out extraneous stuff.
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// Update: Mar. 14, 2003 Added S_PP parameter, made some simple changes to
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// Update: Mar. 14, 2003 Added S_PP parameter, made some simple changes to
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// implement quotient leading zero "skip" feature.
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// implement quotient leading zero "skip" feature.
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// Update: Mar. 24, 2003 Updated comments to improve readability.
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// Update: Mar. 24, 2003 Updated comments to improve readability.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Description:
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// Description:
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//
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//
|
// This module performs a division operation serially, producing one bit of the
|
// This module performs a division operation serially, producing one bit of the
|
// answer per clock cycle. The dividend and the divisor are both taken to be
|
// answer per clock cycle. The dividend and the divisor are both taken to be
|
// unsigned quantities. The divider is conceived as an integer divider (as
|
// unsigned quantities. The divider is conceived as an integer divider (as
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// opposed to a divider for fractional quantities) but the user can configure
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// opposed to a divider for fractional quantities) but the user can configure
|
// the divider to divide fractional quantities as long as the position of the
|
// the divider to divide fractional quantities as long as the position of the
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// binary point is carefully monitored.
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// binary point is carefully monitored.
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//
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//
|
// The widths of the signals are configurable by parameters, as follows:
|
// The widths of the signals are configurable by parameters, as follows:
|
//
|
//
|
// M_PP = Bit width of the dividend
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// M_PP = Bit width of the dividend
|
// N_PP = Bit width of the divisor
|
// N_PP = Bit width of the divisor
|
// R_PP = Remainder bits desired
|
// R_PP = Remainder bits desired
|
// S_PP = Skipped quotient bits
|
// S_PP = Skipped quotient bits
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//
|
//
|
// The skipped quotient bits parameter provides a way to prevent the divider
|
// The skipped quotient bits parameter provides a way to prevent the divider
|
// from calculating the full M_PP+R_PP output bits, in case some of the leading
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// from calculating the full M_PP+R_PP output bits, in case some of the leading
|
// bits are already known to be zero. This is the case, for example, when
|
// bits are already known to be zero. This is the case, for example, when
|
// dividing two quantities to obtain a result that is a fraction between 0 and 1
|
// dividing two quantities to obtain a result that is a fraction between 0 and 1
|
// (as when measuring PWM signals). In that case the integer portion of the
|
// (as when measuring PWM signals). In that case the integer portion of the
|
// quotient is always zero, and therefore it need not be calculated.
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// quotient is always zero, and therefore it need not be calculated.
|
//
|
//
|
// The divide operation is begun by providing a pulse on the divide_i input.
|
// The divide operation is begun by providing a pulse on the divide_i input.
|
// The quotient is provided (M_PP+R_PP-S_PP) clock cycles later.
|
// The quotient is provided (M_PP+R_PP-S_PP) clock cycles later.
|
// The divide_i pulse stores the input parameters in registers, so they do
|
// The divide_i pulse stores the input parameters in registers, so they do
|
// not need to be maintained at the inputs throughout the operation of the module.
|
// not need to be maintained at the inputs throughout the operation of the module.
|
// If a divide_i pulse is given to the serial_divide_uu module during the time
|
// If a divide_i pulse is given to the serial_divide_uu module during the time
|
// when it is already working on a previous divide operation, it will abort the
|
// when it is already working on a previous divide operation, it will abort the
|
// operation it was doing, and begin working on the new one.
|
// operation it was doing, and begin working on the new one.
|
//
|
//
|
// The user is responsible for treating the results correctly. The position
|
// The user is responsible for treating the results correctly. The position
|
// of the binary point is not given, but it is understood that the integer part
|
// of the binary point is not given, but it is understood that the integer part
|
// of the result is the M_PP most significant bits of the quotient output.
|
// of the result is the M_PP most significant bits of the quotient output.
|
// The remaining R_PP least significant bits are the fractional part.
|
// The remaining R_PP least significant bits are the fractional part.
|
//
|
//
|
// This is illustrated graphically:
|
// This is illustrated graphically:
|
//
|
//
|
// [ M_PP bits ][ R_PP bits]
|
// [ M_PP bits ][ R_PP bits]
|
// [ S_PP bits ][quotient_o]
|
// [ S_PP bits ][quotient_o]
|
//
|
//
|
// The quotient will consist of whatever bits are left after removing the S_PP
|
// The quotient will consist of whatever bits are left after removing the S_PP
|
// most significant bits from the (M_PP+R_PP) result bits.
|
// most significant bits from the (M_PP+R_PP) result bits.
|
//
|
//
|
// Attempting to divide by zero will simply produce a result of all ones.
|
// Attempting to divide by zero will simply produce a result of all ones.
|
// This core is so simple, that no checking for this condition is provided.
|
// This core is so simple, that no checking for this condition is provided.
|
// If the user is concerned about a possible divide by zero condition, he should
|
// If the user is concerned about a possible divide by zero condition, he should
|
// compare the divisor to zero and flag that condition himself!
|
// compare the divisor to zero and flag that condition himself!
|
//
|
//
|
// The COUNT_WIDTH_PP parameter must be sized so that 2^COUNT_WIDTH_PP-1 is >=
|
// The COUNT_WIDTH_PP parameter must be sized so that 2^COUNT_WIDTH_PP-1 is >=
|
// M_PP+R_PP-S_PP-1. The unit terminates the divide operation when the count
|
// M_PP+R_PP-S_PP-1. The unit terminates the divide operation when the count
|
// is equal to M_PP+R_PP-S_PP-1.
|
// is equal to M_PP+R_PP-S_PP-1.
|
//
|
//
|
// The HELD_OUTPUT_PP parameter causes the unit to keep its output result in
|
// The HELD_OUTPUT_PP parameter causes the unit to keep its output result in
|
// a register other than the one which it uses to compute the quotient. This
|
// a register other than the one which it uses to compute the quotient. This
|
// is useful for applications where the divider is used repeatedly and the
|
// is useful for applications where the divider is used repeatedly and the
|
// previous divide result (quotient) must be stable during the computation of the
|
// previous divide result (quotient) must be stable during the computation of the
|
// next divide result. Using the additional output register does incur some
|
// next divide result. Using the additional output register does incur some
|
// additional utilization of resources.
|
// additional utilization of resources.
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
|
|
module serial_divide_uu (
|
module serial_divide_uu (
|
clk_i,
|
clk_i,
|
clk_en_i,
|
clk_en_i,
|
rst_i,
|
rst_i,
|
divide_i,
|
divide_i,
|
dividend_i,
|
dividend_i,
|
divisor_i,
|
divisor_i,
|
quotient_o,
|
quotient_o,
|
done_o
|
done_o
|
);
|
);
|
/*
|
/*
|
M_PP => 21,
|
M_PP => 21,
|
N_PP => 21,
|
N_PP => 21,
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R_PP => 0,
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R_PP => 0,
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S_PP => 0,
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S_PP => 0,
|
HELD_OUTPUT_PP => 1
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HELD_OUTPUT_PP => 1
|
*/
|
*/
|
parameter M_PP = 21; // Size of dividend
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parameter M_PP = 21; // Size of dividend
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parameter N_PP = 21; // Size of divisor
|
parameter N_PP = 21; // Size of divisor
|
parameter R_PP = 0; // Size of remainder
|
parameter R_PP = 0; // Size of remainder
|
parameter S_PP = 0; // Skip this many bits (known leading zeros)
|
parameter S_PP = 0; // Skip this many bits (known leading zeros)
|
parameter COUNT_WIDTH_PP = 5; // 2^COUNT_WIDTH_PP-1 >= (M_PP+R_PP-S_PP-1)
|
parameter COUNT_WIDTH_PP = 5; // 2^COUNT_WIDTH_PP-1 >= (M_PP+R_PP-S_PP-1)
|
parameter HELD_OUTPUT_PP = 1; // Set to 1 if stable output should be held
|
parameter HELD_OUTPUT_PP = 1; // Set to 1 if stable output should be held
|
// from previous operation, during current
|
// from previous operation, during current
|
// operation. Using this option will increase
|
// operation. Using this option will increase
|
// the resource utilization (costs extra
|
// the resource utilization (costs extra
|
// d-flip-flops.)
|
// d-flip-flops.)
|
|
|
// I/O declarations
|
// I/O declarations
|
input clk_i; //
|
input clk_i; //
|
input clk_en_i;
|
input clk_en_i;
|
input rst_i; // synchronous reset
|
input rst_i; // synchronous reset
|
input divide_i; // starts division operation
|
input divide_i; // starts division operation
|
input [M_PP-1:0] dividend_i; //
|
input [M_PP-1:0] dividend_i; //
|
input [N_PP-1:0] divisor_i; //
|
input [N_PP-1:0] divisor_i; //
|
output [M_PP+R_PP-S_PP-1:0] quotient_o; //
|
output [M_PP+R_PP-S_PP-1:0] quotient_o; //
|
output done_o; // indicates completion of operation
|
output done_o; // indicates completion of operation
|
|
|
//reg [M_PP+R_PP-1:0] quotient_o;
|
//reg [M_PP+R_PP-1:0] quotient_o;
|
reg done_o;
|
reg done_o;
|
|
|
// Internal signal declarations
|
// Internal signal declarations
|
|
|
reg [M_PP+R_PP-1:0] grand_dividend;
|
reg [M_PP+R_PP-1:0] grand_dividend;
|
reg [M_PP+N_PP+R_PP-2:0] grand_divisor;
|
reg [M_PP+N_PP+R_PP-2:0] grand_divisor;
|
reg [M_PP+R_PP-S_PP-1:0] quotient;
|
reg [M_PP+R_PP-S_PP-1:0] quotient;
|
reg [M_PP+R_PP-1:0] quotient_reg; // Used exclusively for the held output
|
reg [M_PP+R_PP-1:0] quotient_reg; // Used exclusively for the held output
|
reg [COUNT_WIDTH_PP-1:0] divide_count;
|
reg [COUNT_WIDTH_PP-1:0] divide_count;
|
|
|
wire [M_PP+N_PP+R_PP-1:0] subtract_node; // Subtract node has extra "sign" bit
|
wire [M_PP+N_PP+R_PP-1:0] subtract_node; // Subtract node has extra "sign" bit
|
wire [M_PP+R_PP-1:0] quotient_node; // Shifted version of quotient
|
wire [M_PP+R_PP-1:0] quotient_node; // Shifted version of quotient
|
wire [M_PP+N_PP+R_PP-2:0] divisor_node; // Shifted version of grand divisor
|
wire [M_PP+N_PP+R_PP-2:0] divisor_node; // Shifted version of grand divisor
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Module code
|
// Module code
|
|
|
// Serial dividing module
|
// Serial dividing module
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
begin
|
begin
|
if (rst_i)
|
if (rst_i)
|
begin
|
begin
|
grand_dividend <= 0;
|
grand_dividend <= 0;
|
grand_divisor <= 0;
|
grand_divisor <= 0;
|
divide_count <= 0;
|
divide_count <= 0;
|
quotient <= 0;
|
quotient <= 0;
|
done_o <= 0;
|
done_o <= 0;
|
end
|
end
|
else if (clk_en_i)
|
else if (clk_en_i)
|
begin
|
begin
|
done_o <= 0;
|
done_o <= 0;
|
if (divide_i) // Start a new division
|
if (divide_i) // Start a new division
|
begin
|
begin
|
quotient <= 0;
|
quotient <= 0;
|
divide_count <= 0;
|
divide_count <= 0;
|
// dividend placed initially so that remainder bits are zero...
|
// dividend placed initially so that remainder bits are zero...
|
grand_dividend <= dividend_i << R_PP;
|
grand_dividend <= dividend_i << R_PP;
|
// divisor placed initially for a 1 bit overlap with dividend...
|
// divisor placed initially for a 1 bit overlap with dividend...
|
// But adjust it back by S_PP, to account for bits that are known
|
// But adjust it back by S_PP, to account for bits that are known
|
// to be leading zeros in the quotient.
|
// to be leading zeros in the quotient.
|
|
/* verilator lint_off WIDTH */
|
grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1);
|
grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1);
|
|
/* verilator lint_on WIDTH */
|
end
|
end
|
|
/* verilator lint_off WIDTH */
|
else if (divide_count == M_PP+R_PP-S_PP-1)
|
else if (divide_count == M_PP+R_PP-S_PP-1)
|
|
/* verilator lint_on WIDTH */
|
begin
|
begin
|
if (~done_o) quotient <= quotient_node; // final shift...
|
if (~done_o) quotient <= quotient_node; // final shift...
|
if (~done_o) quotient_reg <= quotient_node; // final shift (held output)
|
if (~done_o) quotient_reg <= quotient_node; // final shift (held output)
|
done_o <= 1; // Indicate done, just sit
|
done_o <= 1; // Indicate done, just sit
|
end
|
end
|
else // Division in progress
|
else // Division in progress
|
begin
|
begin
|
// If the subtraction yields a positive result, then store that result
|
// If the subtraction yields a positive result, then store that result
|
|
/* verilator lint_off WIDTH */
|
if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
|
if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
|
|
/* verilator lint_on WIDTH */
|
// If the subtraction yields a positive result, then a 1 bit goes into
|
// If the subtraction yields a positive result, then a 1 bit goes into
|
// the quotient, via a shift register
|
// the quotient, via a shift register
|
quotient <= quotient_node;
|
quotient <= quotient_node;
|
// shift the grand divisor to the right, to cut it in half next clock cycle
|
// shift the grand divisor to the right, to cut it in half next clock cycle
|
grand_divisor <= divisor_node;
|
grand_divisor <= divisor_node;
|
// Advance the counter
|
// Advance the counter
|
divide_count <= divide_count + 1;
|
divide_count <= divide_count + 1;
|
end
|
end
|
end // End of else if clk_en_i
|
end // End of else if clk_en_i
|
end // End of always block
|
end // End of always block
|
|
|
|
/* verilator lint_off WIDTH */
|
assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
|
assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
|
|
/* verilator lint_on WIDTH */
|
assign quotient_node =
|
assign quotient_node =
|
{quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
|
{quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
|
assign divisor_node = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
|
assign divisor_node = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
|
|
|
assign quotient_o = (HELD_OUTPUT_PP == 0)?quotient:quotient_reg;
|
assign quotient_o = (HELD_OUTPUT_PP == 0)?quotient:quotient_reg;
|
|
|
endmodule
|
endmodule
|
|
|
module SignedIntegerDivision
|
module SignedIntegerDivision
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
output wire [`WIDTH-1:0] oQuotient,
|
output wire [`WIDTH-1:0] oQuotient,
|
input wire [`WIDTH-1:0] iDividend,
|
input wire [`WIDTH-1:0] iDividend,
|
input wire [`WIDTH-1:0] iDivisor,
|
input wire [`WIDTH-1:0] iDivisor,
|
input wire iInputReady,
|
input wire iInputReady,
|
output wire OutputReady
|
output wire OutputReady
|
|
|
|
|
);
|
);
|
|
|
|
|
wire wInputReadyDelay1,wInputReadyPulse;
|
wire wInputReadyDelay1,wInputReadyPulse;
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Enable( 1'b1 ),
|
.Enable( 1'b1 ),
|
.D( iInputReady ),
|
.D( iInputReady ),
|
.Q(wInputReadyDelay1)
|
.Q(wInputReadyDelay1)
|
);
|
);
|
|
|
assign wInputReadyPulse = iInputReady ^ wInputReadyDelay1;
|
assign wInputReadyPulse = iInputReady ^ wInputReadyDelay1;
|
|
|
wire [`LONG_WIDTH-1:0] wDividend,wDivisor,wScaledDividend;
|
wire [`LONG_WIDTH-1:0] wDividend,wDivisor,wScaledDividend;
|
wire [`WIDTH-1:0] wNegDividend,wNegDivisor;
|
wire [`WIDTH-1:0] wNegDividend,wNegDivisor;
|
assign wNegDividend = ~iDividend+1'b1;
|
assign wNegDividend = ~iDividend+1'b1;
|
assign wNegDivisor = ~iDivisor + 1'b1;
|
assign wNegDivisor = ~iDivisor + 1'b1;
|
|
|
wire [`LONG_WIDTH-1:0] wQuotient;
|
wire [`LONG_WIDTH-1:0] wQuotient;
|
//Assign the sign extended signed value
|
//Assign the sign extended signed value
|
assign wDividend = (iDividend[`WIDTH-1] == 1'b1) ?
|
assign wDividend = (iDividend[`WIDTH-1] == 1'b1) ?
|
{{32{wNegDividend[31]}},wNegDividend[31:0]} : {{32{iDividend[31]}},iDividend[31:0]} ;
|
{{32{wNegDividend[31]}},wNegDividend[31:0]} : {{32{iDividend[31]}},iDividend[31:0]} ;
|
|
|
assign wDivisor = (iDivisor[`WIDTH-1] == 1'b1) ?
|
assign wDivisor = (iDivisor[`WIDTH-1] == 1'b1) ?
|
{{32{wNegDivisor[31]}},wNegDivisor[31:0]} : {{32{iDivisor[31]}},iDivisor[31:0]} ;
|
{{32{wNegDivisor[31]}},wNegDivisor[31:0]} : {{32{iDivisor[31]}},iDivisor[31:0]} ;
|
wire wNegativeOutput;
|
wire wNegativeOutput;
|
assign wNegativeOutput = iDividend[`WIDTH-1] ^ iDivisor[`WIDTH-1];
|
assign wNegativeOutput = iDividend[`WIDTH-1] ^ iDivisor[`WIDTH-1];
|
|
|
wire wNegativeOutput_Latched;
|
wire wNegativeOutput_Latched;
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_NEG
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_NEG
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Enable( iInputReady ),
|
.Enable( iInputReady ),
|
.D( wNegativeOutput ),
|
.D( wNegativeOutput ),
|
.Q(wNegativeOutput_Latched)
|
.Q(wNegativeOutput_Latched)
|
);
|
);
|
|
|
assign oQuotient = (wNegativeOutput_Latched) ? ~wQuotient[`WIDTH-1:0]+1'b1 : wQuotient[`WIDTH-1:0];
|
assign oQuotient = (wNegativeOutput_Latched) ? ~wQuotient[`WIDTH-1:0]+1'b1 : wQuotient[`WIDTH-1:0];
|
wire wOutputReady,wOutputReadyDelay1;
|
wire wOutputReady,wOutputReadyDelay1;
|
|
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FF_DELAY2
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(
|
(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | iInputReady),
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.Reset( Reset | iInputReady),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( wOutputReady ),
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.D( wOutputReady ),
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.Q(wOutputReadyDelay1)
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.Q(wOutputReadyDelay1)
|
);
|
);
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assign OutputReady = wOutputReady ^ wOutputReadyDelay1;
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assign OutputReady = wOutputReady ^ wOutputReadyDelay1;
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assign wScaledDividend = (wDividend << `SCALE);
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assign wScaledDividend = (wDividend << `SCALE);
|
|
|
serial_divide_uu # ( 64,64,0,0,6,1 ) uu_div(
|
serial_divide_uu # ( 64,64,0,0,6,1 ) uu_div(
|
.clk_i(Clock),
|
.clk_i(Clock),
|
.clk_en_i(1'b1),
|
.clk_en_i(1'b1),
|
.rst_i(Reset),
|
.rst_i(Reset),
|
.divide_i(iInputReady),
|
.divide_i(iInputReady),
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.dividend_i(wScaledDividend),
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.dividend_i(wScaledDividend),
|
.divisor_i(wDivisor),
|
.divisor_i(wDivisor),
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.quotient_o(wQuotient),
|
.quotient_o(wQuotient),
|
.done_o(wOutputReady)
|
.done_o(wOutputReady)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
