`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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module WBMaster
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module WBMaster
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire iShortFlow,
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input wire iShortFlow,
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input wire [`WB_WIDTH-1:0] iInitialReadAddr,
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input wire [`WB_WIDTH-1:0] iInitialReadAddr,
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input wire [`WB_WIDTH-1:0] iWriteAddr,
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input wire [`WB_WIDTH-1:0] iWriteAddr,
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output wire [`WB_WIDTH-1:0] oReadAddress,
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output wire [`WB_WIDTH-1:0] oReadAddress,
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input wire [`WB_WIDTH-1:0] iReadData,
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input wire [`WB_WIDTH-1:0] iReadData,
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output reg STB_O,
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output reg STB_O,
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input wire ACK_I,
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input wire ACK_I,
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output wire CYC_O,
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output wire CYC_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire oDone
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output wire oDone
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);
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);
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assign ADR_O = iWriteAddr;
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assign ADR_O = iWriteAddr;
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wire [3:0] wXYZSel_Long;
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wire [3:0] wXYZSel_Long;
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wire [2:0] wXYZSel_Short;
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wire [2:0] wXYZSel_Short;
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UPCOUNTER_POSEDGE # (`WB_WIDTH) WBM_O_READ_ADDRESS
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UPCOUNTER_POSEDGE # (`WB_WIDTH) WBM_O_READ_ADDRESS
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(iEnable & ACK_I),
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.Enable(iEnable & ACK_I),
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.Initial(iInitialReadAddr),
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.Initial(iInitialReadAddr),
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.Q(oReadAddress)
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.Q(oReadAddress)
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);
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);
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CIRCULAR_SHIFTLEFT_POSEDGE #(4) SHL
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CIRCULAR_SHIFTLEFT_POSEDGE #(4) SHL
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Enable(ACK_I & iEnable),
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.Enable(ACK_I & iEnable),
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.Reset( Reset ),
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.Reset( Reset ),
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.Initial(4'b1),
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.Initial(4'b1),
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.O(wXYZSel_Long)
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.O(wXYZSel_Long)
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);
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);
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CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL2
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CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL2
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Enable(ACK_I & iEnable),
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.Enable(ACK_I & iEnable),
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.Reset( Reset ),
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.Reset( Reset ),
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.Initial(3'b1),
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.Initial(3'b1),
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.O(wXYZSel_Short)
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.O(wXYZSel_Short)
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);
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);
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assign oDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
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//`ifdef VERILATOR
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wire wDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
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//Adding FFD to break combinatorial loop.
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//Host::wShortCycle -> WBM::iShortCycle -> WBM::wDone -> Host::wWBMDone -> Host::always ->Host::oMemSelect -> Host::wShortCycle
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_DONE
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.D(wDone),
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.Q(oDone)
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);
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//`else
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// assign oDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
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//`endif
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assign DAT_O = iReadData;
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assign DAT_O = iReadData;
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assign CYC_O = iEnable;
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assign CYC_O = iEnable;
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always @ (posedge Clock)
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always @ (posedge Clock)
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begin
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begin
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if (iEnable )
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if (iEnable )
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STB_O <= ~ACK_I;
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STB_O <= ~ACK_I;
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else
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else
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STB_O <= 0;
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STB_O <= 0;
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end
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end
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endmodule
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endmodule
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