`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define TAG_WBS_INSTRUCTION_ADDRESS_TYPE 2'b10
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`define TAG_WBS_INSTRUCTION_ADDRESS_TYPE 2'b10
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`define TAG_WBS_DATA_ADDRESS_TYPE 2'b01
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`define TAG_WBS_DATA_ADDRESS_TYPE 2'b01
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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module WishBoneSlaveUnit
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module WishBoneSlaveUnit
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(
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(
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//WB Input signals
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//WB Input signals
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input wire CLK_I,
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input wire CLK_I,
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input wire RST_I,
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input wire RST_I,
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input wire STB_I,
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input wire STB_I,
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input wire WE_I,
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input wire WE_I,
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input wire[`WB_WIDTH-1:0] DAT_I,
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input wire[`WB_WIDTH-1:0] DAT_I,
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input wire[`WB_WIDTH-1:0] ADR_I,
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input wire[`WB_WIDTH-1:0] ADR_I,
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input wire [1:0] TGA_I,
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input wire [1:0] TGA_I,
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output wire ACK_O,
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output wire ACK_O,
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input wire MST_I, //Master In!
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input wire MST_I, //Master In!
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input wire CYC_I,
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input wire CYC_I,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
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output wire oDataWriteEnable,
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output wire oDataWriteEnable,
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output wire oInstructionWriteEnable
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output wire oInstructionWriteEnable
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # (16) FFADR
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FFD_POSEDGE_SYNCRONOUS_RESET # (16) FFADR
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(
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(
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.Clock( CYC_I ),
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.Clock( CYC_I ),
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.Reset( RST_I ),
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.Reset( RST_I ),
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.Enable(1'b1),
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.Enable(1'b1),
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.D( ADR_I[15:0] ),
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.D( ADR_I[15:0] ),
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.Q( oInstructionWriteAddress )
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.Q( oInstructionWriteAddress )
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);
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);
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assign oDataWriteAddress = oInstructionWriteAddress;
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assign oDataWriteAddress = oInstructionWriteAddress;
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wire[1:0] wTGA_Latched;
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wire[1:0] wTGA_Latched;
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FFD_POSEDGE_SYNCRONOUS_RESET # (2) FFADDRTYPE
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FFD_POSEDGE_SYNCRONOUS_RESET # (2) FFADDRTYPE
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(
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(
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.Clock( CYC_I ),
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.Clock( CYC_I ),
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.Reset( RST_I ),
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.Reset( RST_I ),
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.Enable(1'b1),
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.Enable(1'b1),
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.D( TGA_I ),
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.D( TGA_I ),
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.Q( wTGA_Latched )
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.Q( wTGA_Latched )
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);
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);
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wire Clock,Reset;
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wire Clock,Reset;
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assign Clock = CLK_I;
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assign Clock = CLK_I;
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assign Reset = RST_I;
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assign Reset = RST_I;
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wire wLatchNow;
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wire wLatchNow;
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assign wLatchNow = STB_I & WE_I;
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assign wLatchNow = STB_I & WE_I;
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//1 Clock cycle after we assert the latch signal
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//1 Clock cycle after we assert the latch signal
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//then the FF has the data ready to propagate
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//then the FF has the data ready to propagate
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wire wDelay;
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wire wDelay;
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FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputDelay
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FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputDelay
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.Reset( Reset ),
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.Reset( Reset ),
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.D( wLatchNow ),
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.D( wLatchNow ),
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.Q( wDelay )
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.Q( wDelay )
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);
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);
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assign ACK_O = wDelay & STB_I; //make sure we set ACK_O back to zero when STB_I is zero
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assign ACK_O = wDelay & STB_I; //make sure we set ACK_O back to zero when STB_I is zero
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wire [2:0] wXYZSel;
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wire [2:0] wXYZSel;
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SHIFTLEFT_POSEDGE #(3) SHL
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SHIFTLEFT_POSEDGE #(3) SHL
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(
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(
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.Clock(CLK_I),
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.Clock(CLK_I),
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.Enable(STB_I & ~ACK_O),
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.Enable(STB_I & ~ACK_O),
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.Reset(~CYC_I),
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.Reset(~CYC_I),
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.Initial(3'b1),
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.Initial(3'b1),
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.O(wXYZSel)
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.O(wXYZSel)
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);
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);
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//Flip Flop to Store Vx
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//Flip Flop to Store Vx
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wire [`WIDTH-1:0] wVx;
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wire [`WIDTH-1:0] wVx;
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vx
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vx
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wXYZSel[0] & STB_I ),
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.Enable( wXYZSel[0] & STB_I ),
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.D( DAT_I ),
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.D( DAT_I ),
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.Q( wVx )
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.Q( wVx )
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);
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);
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//Flip Flop to Store Vy
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//Flip Flop to Store Vy
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wire [`WIDTH-1:0] wVy;
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wire [`WIDTH-1:0] wVy;
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vy
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vy
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wXYZSel[1] & STB_I ),
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.Enable( wXYZSel[1] & STB_I ),
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.D( DAT_I ),
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.D( DAT_I ),
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.Q( wVy )
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.Q( wVy )
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);
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);
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//Flip Flop to Store Vz
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//Flip Flop to Store Vz
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wire [`WIDTH-1:0] wVz;
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wire [`WIDTH-1:0] wVz;
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vz
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vz
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wXYZSel[2] & STB_I ),
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.Enable( wXYZSel[2] & STB_I ),
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.D( DAT_I ),
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.D( DAT_I ),
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.Q( wVz )
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.Q( wVz )
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);
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);
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assign oDataBus = {wVx,wVy,wVz};
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assign oDataBus = {wVx,wVy,wVz};
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assign oInstructionBus = {wVx,wVy};
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assign oInstructionBus = {wVx,wVy};
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wire wIsInstructionAddress,wIsDataAddress;
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wire wIsInstructionAddress,wIsDataAddress;
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assign wIsInstructionAddress = (wTGA_Latched == `TAG_WBS_INSTRUCTION_ADDRESS_TYPE) ? 1'b1 : 1'b0;
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assign wIsInstructionAddress = (wTGA_Latched == `TAG_WBS_INSTRUCTION_ADDRESS_TYPE) ? 1'b1 : 1'b0;
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assign wIsDataAddress = (wTGA_Latched == `TAG_WBS_DATA_ADDRESS_TYPE ) ? 1'b1 : 1'b0;
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assign wIsDataAddress = (wTGA_Latched == `TAG_WBS_DATA_ADDRESS_TYPE ) ? 1'b1 : 1'b0;
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assign oDataWriteEnable = (MST_I && !CYC_I && wIsInstructionAddress) ? 1'b1 : 1'b0;
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assign oDataWriteEnable = (MST_I && !CYC_I && wIsInstructionAddress) ? 1'b1 : 1'b0;
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assign oInstructionWriteEnable = ( MST_I && !CYC_I && wIsDataAddress) ? 1'b1 : 1'b0;
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assign oInstructionWriteEnable = ( MST_I && !CYC_I && wIsDataAddress) ? 1'b1 : 1'b0;
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endmodule
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endmodule
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