`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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|
`ifdef VERILATOR
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`include "Module_RAM.v"
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`include "Module_ROM.v"
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`include "Module_SwapMemory.v"
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`include "Module_ControlRegister.v"
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`endif
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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|
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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|
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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|
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***********************************************************************************/
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***********************************************************************************/
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/*
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/*
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The memory unit has all the memory related modules for THEIA.
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The memory unit has all the memory related modules for THEIA.
|
There a 3 memories in the core:
|
There a 3 memories in the core:
|
DMEM: The data memory, it is a R/W dual channel RAM, stores the data locations.
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DMEM: The data memory, it is a R/W dual channel RAM, stores the data locations.
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IMEM: The instruction memory, R/W dual channel RAM, stores user shaders.
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IMEM: The instruction memory, R/W dual channel RAM, stores user shaders.
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IROM: RO instruction memory, stores default shaders and other internal code.
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IROM: RO instruction memory, stores default shaders and other internal code.
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I use two ROMs with the same data, so that simulates dual channel.
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I use two ROMs with the same data, so that simulates dual channel.
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This unit also has a Control register.
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This unit also has a Control register.
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*/
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*/
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`define USER_CODE_ENABLED 2
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`define USER_CODE_ENABLED 2
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//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
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module MemoryUnit
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module MemoryUnit
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(
|
(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iFlipMemory,
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input wire iFlipMemory,
|
|
|
//Data bus for EXE Unit
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//Data bus for EXE Unit
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input wire iDataWriteEnable_EXE,
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input wire iDataWriteEnable_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_EXE,
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input wire[`DATA_ROW_WIDTH-1:0] iData_EXE,
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input wire[`DATA_ROW_WIDTH-1:0] iData_EXE,
|
|
|
//Data bus for IO Unit
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//Data bus for IO Unit
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input wire iDataWriteEnable_IO,
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input wire iDataWriteEnable_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_IO,
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input wire[`DATA_ROW_WIDTH-1:0] iData_IO,
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input wire[`DATA_ROW_WIDTH-1:0] iData_IO,
|
|
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//Instruction bus
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//Instruction bus
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input wire iInstructionWriteEnable,
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input wire iInstructionWriteEnable,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1,
|
output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2,
|
|
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`ifdef DEBUG
|
`ifdef DEBUG
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input wire [`MAX_CORES-1:0] iDebug_CoreID,
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input wire [`MAX_CORES-1:0] iDebug_CoreID,
|
`endif
|
`endif
|
|
|
|
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//Control Register
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//Control Register
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input wire[15:0] iControlRegister,
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input wire[15:0] iControlRegister,
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output wire[15:0] oControlRegister
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output wire[15:0] oControlRegister
|
|
|
|
|
);
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);
|
|
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut1,wIMEM2_IMUX__DataOut2,
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut1,wIMEM2_IMUX__DataOut2,
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wIROM2_IMUX__DataOut1,wIROM2_IMUX__DataOut2;
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wIROM2_IMUX__DataOut1,wIROM2_IMUX__DataOut2;
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wire wFlipSelect;
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wire wFlipSelect;
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|
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wire wInstructionSelector,wInstructionSelector2;
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wire wInstructionSelector,wInstructionSelector2;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
|
(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-1] ),
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.D( iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-1] ),
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.Q( wInstructionSelector )
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.Q( wInstructionSelector )
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);
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);
|
|
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
|
(
|
(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
|
.Reset(Reset),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-1] ),
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.D( iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-1] ),
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.Q( wInstructionSelector2 )
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.Q( wInstructionSelector2 )
|
);
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);
|
|
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assign oInstruction1 = (wInstructionSelector == 1) ?
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assign oInstruction1 = (wInstructionSelector == 1) ?
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wIMEM2_IMUX__DataOut1 : wIROM2_IMUX__DataOut1;
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wIMEM2_IMUX__DataOut1 : wIROM2_IMUX__DataOut1;
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|
|
|
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assign oInstruction2 = (wInstructionSelector2 == 1) ?
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assign oInstruction2 = (wInstructionSelector2 == 1) ?
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wIMEM2_IMUX__DataOut2 : wIROM2_IMUX__DataOut2;
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wIMEM2_IMUX__DataOut2 : wIROM2_IMUX__DataOut2;
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//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
|
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wire wDataWriteEnable_RMEM,wDataWriteEnable_SMEM,wDataWriteEnable_XMEM;
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wire wDataWriteEnable_RMEM,wDataWriteEnable_SMEM,wDataWriteEnable_XMEM;
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wire [`DATA_ROW_WIDTH-1:0] wData_SMEM1,wData_SMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wData_SMEM1,wData_SMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wData_RMEM1,wData_RMEM2,wData_IMEM1,wData_IMEM2,wData_XMEM1,wData_XMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wData_RMEM1,wData_RMEM2,wData_IMEM1,wData_IMEM2,wData_XMEM1,wData_XMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2;//,wData_OMEM1,wData_OMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2;//,wData_OMEM1,wData_OMEM2;
|
|
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/*******************************************************
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/*******************************************************
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The Data memory is divided into several memory banks.
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The Data memory is divided into several memory banks.
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Each Bank has different characteristics:
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Each Bank has different characteristics:
|
|
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* IO MEM: Input Registers, Written by IO, Read by EXE.
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* IO MEM: Input Registers, Written by IO, Read by EXE.
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* SWAP MEM: Swap registers, while IO reads/write values,
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* SWAP MEM: Swap registers, while IO reads/write values,
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EXE reads/write values.
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EXE reads/write values.
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* C1-C7, R1- R12: General purpose registers,
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* C1-C7, R1- R12: General purpose registers,
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EXE can R/W, IO can not see these sections of the memory
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EXE can R/W, IO can not see these sections of the memory
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* OREG*: Output registers written by EXE, Read by IO.
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* OREG*: Output registers written by EXE, Read by IO.
|
|
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Whenever an input address is received, this imput address
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Whenever an input address is received, this imput address
|
is divided in a bank selector and offset in the following way:
|
is divided in a bank selector and offset in the following way:
|
|
|
__________________________
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__________________________
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| b6 b5 | b4 b3 b2 b1 b0 |
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| b6 b5 | b4 b3 b2 b1 b0 |
|
|
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The bits b4 .. b0 are the LSB of the address, this give the
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The bits b4 .. b0 are the LSB of the address, this give the
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position relative to the bank
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position relative to the bank
|
|
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The bits b6 and b5 give the actual Bank to select.
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The bits b6 and b5 give the actual Bank to select.
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Please see aDefinitions.v for a description of each
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Please see aDefinitions.v for a description of each
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register location.
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register location.
|
|
|
0____________________
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0____________________
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| IO MEM |
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| IO MEM |
|
| |
|
| |
|
| | b6b5 = 00
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| | b6b5 = 00
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32|__________________|
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32|__________________|
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| SWAP MEM |
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| SWAP MEM |
|
| | b6b5 = 01
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| | b6b5 = 01
|
| |
|
| |
|
64|__________________|
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64|__________________|
|
| C1 - C7 |
|
| C1 - C7 |
|
| R1 - R12 | b6b5 = 10
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| R1 - R12 | b6b5 = 10
|
| |
|
| |
|
96|__________________|
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96|__________________|
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| CREG* |
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| CREG* |
|
| | b6b5 = 11
|
| | b6b5 = 11
|
| |
|
| |
|
|__________________|
|
|__________________|
|
|
|
|
|
*******************************************************/
|
*******************************************************/
|
|
|
|
|
|
|
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
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MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
|
(
|
(
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.Sel( iDataReadAddress1_EXE[6:5] ),
|
.Sel( iDataReadAddress1_EXE[6:5] ),
|
.I1( wData_IMEM1 ), //IO MEM
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.I1( wData_IMEM1 ), //IO MEM
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.I2( wData_SMEM1 ), //SWAP MEM
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.I2( wData_SMEM1 ), //SWAP MEM
|
.I3( wData_RMEM1 ), //R*, C*
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.I3( wData_RMEM1 ), //R*, C*
|
.I4( wData_XMEM1 ), //CREG*
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.I4( wData_XMEM1 ), //CREG*
|
.O1( oData1_EXE )
|
.O1( oData1_EXE )
|
);
|
);
|
|
|
|
|
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX2
|
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX2
|
(
|
(
|
.Sel( iDataReadAddress2_EXE[6:5] ),
|
.Sel( iDataReadAddress2_EXE[6:5] ),
|
.I1( wData_IMEM2 ), //IO MEM
|
.I1( wData_IMEM2 ), //IO MEM
|
.I2( wData_SMEM2 ), //SWAP MEM
|
.I2( wData_SMEM2 ), //SWAP MEM
|
.I3( wData_RMEM2 ), //R*, C*
|
.I3( wData_RMEM2 ), //R*, C*
|
.I4( wData_XMEM2 ), //CREG*
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.I4( wData_XMEM2 ), //CREG*
|
.O1( oData2_EXE )
|
.O1( oData2_EXE )
|
);
|
);
|
|
|
assign wDataWriteEnable_SMEM = ( iDataWriteAddress_EXE[6:5] == 2'b01 && iDataWriteEnable_EXE ); //Enable WE for SMEM if bank == 01
|
assign wDataWriteEnable_SMEM = ( iDataWriteAddress_EXE[6:5] == 2'b01 && iDataWriteEnable_EXE ); //Enable WE for SMEM if bank == 01
|
assign wDataWriteEnable_RMEM = ( iDataWriteAddress_EXE[6:5] == 2'b10 && iDataWriteEnable_EXE); //Enable WE for RMEM if bank == 10
|
assign wDataWriteEnable_RMEM = ( iDataWriteAddress_EXE[6:5] == 2'b10 && iDataWriteEnable_EXE); //Enable WE for RMEM if bank == 10
|
assign wDataWriteEnable_XMEM = ( iDataWriteAddress_EXE[6:5] == 2'b11 && iDataWriteEnable_EXE); //Enable WE for RMEM if bank == 11
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assign wDataWriteEnable_XMEM = ( iDataWriteAddress_EXE[6:5] == 2'b11 && iDataWriteEnable_EXE); //Enable WE for RMEM if bank == 11
|
|
|
|
|
//Input Registers, Written by IO, Read by EXE
|
//Input Registers, Written by IO, Read by EXE
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,/*42*/32) IMEM //16 here is enough, I hate small devices!
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,/*42*/32) IMEM //16 here is enough, I hate small devices!
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( iDataWriteEnable_IO ), //Only IO can write into this bank
|
.iWriteEnable( iDataWriteEnable_IO ), //Only IO can write into this bank
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ), //EXE read address channel 1
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ), //EXE read address channel 1
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ), //EXE read address channel 2
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ), //EXE read address channel 2
|
.iWriteAddress( iDataWriteAddress_IO[4:0] ), //Only IO can write into this bank
|
.iWriteAddress( iDataWriteAddress_IO[4:0] ), //Only IO can write into this bank
|
.iDataIn( iData_IO ),
|
.iDataIn( iData_IO ),
|
.oDataOut0( wData_IMEM1 ),
|
.oDataOut0( wData_IMEM1 ),
|
.oDataOut1( wData_IMEM2 )
|
.oDataOut1( wData_IMEM2 )
|
);
|
);
|
|
|
//Swap registers, while IO reads/write values, EXE reads/write values
|
//Swap registers, while IO reads/write values, EXE reads/write values
|
//the pointers get filped in the next iteration
|
//the pointers get filped in the next iteration
|
`define SWAP_MEM_ADDR_WIDHT 5
|
`define SWAP_MEM_ADDR_WIDHT 5
|
SWAP_MEM # (`DATA_ROW_WIDTH,5,32) SMEM
|
SWAP_MEM # (`DATA_ROW_WIDTH,5,32) SMEM
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iSelect( wFlipSelect ),
|
.iSelect( wFlipSelect ),
|
|
|
.iWriteEnableA( wDataWriteEnable_SMEM ),
|
.iWriteEnableA( wDataWriteEnable_SMEM ),
|
.iReadAddressA0( iDataReadAddress1_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressA0( iDataReadAddress1_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressA1( iDataReadAddress2_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressA1( iDataReadAddress2_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iWriteAddressA( iDataWriteAddress_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iWriteAddressA( iDataWriteAddress_EXE[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iDataInA( iData_EXE ),
|
.iDataInA( iData_EXE ),
|
.oDataOutA0( wData_SMEM1 ),
|
.oDataOutA0( wData_SMEM1 ),
|
.oDataOutA1( wData_SMEM2 ),
|
.oDataOutA1( wData_SMEM2 ),
|
|
|
.iWriteEnableB( iDataWriteEnable_IO ),
|
.iWriteEnableB( iDataWriteEnable_IO ),
|
.iReadAddressB0( iDataReadAddress1_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressB0( iDataReadAddress1_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressB1( iDataReadAddress2_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iReadAddressB1( iDataReadAddress2_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iWriteAddressB( iDataWriteAddress_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iWriteAddressB( iDataWriteAddress_IO[`SWAP_MEM_ADDR_WIDHT-1:0] ),
|
.iDataInB( iData_IO )
|
.iDataInB( iData_IO )
|
// .oDataOutB0( wIOData_SMEM1 ),
|
// .oDataOutB0( wIOData_SMEM1 ),
|
// .oDataOutB1( wIOData_SMEM2 )
|
// .oDataOutB1( wIOData_SMEM2 )
|
|
|
);
|
);
|
|
|
//General purpose registers, EXE can R/W, IO can not see these sections
|
//General purpose registers, EXE can R/W, IO can not see these sections
|
//of the memory
|
//of the memory
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,32) RMEM //Ok so we have fewer Registers then...
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,32) RMEM //Ok so we have fewer Registers then...
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( wDataWriteEnable_RMEM ),
|
.iWriteEnable( wDataWriteEnable_RMEM ),
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ),
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ),
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ),
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ),
|
.iWriteAddress( iDataWriteAddress_EXE[4:0] ),
|
.iWriteAddress( iDataWriteAddress_EXE[4:0] ),
|
.iDataIn( iData_EXE ),
|
.iDataIn( iData_EXE ),
|
.oDataOut0( wData_RMEM1 ),
|
.oDataOut0( wData_RMEM1 ),
|
.oDataOut1( wData_RMEM2 )
|
.oDataOut1( wData_RMEM2 )
|
);
|
);
|
|
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,32) XMEM //Ok so we have fewer Registers then...
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,5,32) XMEM //Ok so we have fewer Registers then...
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( wDataWriteEnable_XMEM ),
|
.iWriteEnable( wDataWriteEnable_XMEM ),
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ),
|
.iReadAddress0( iDataReadAddress1_EXE[4:0] ),
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ),
|
.iReadAddress1( iDataReadAddress2_EXE[4:0] ),
|
.iWriteAddress( iDataWriteAddress_EXE[4:0] ),
|
.iWriteAddress( iDataWriteAddress_EXE[4:0] ),
|
.iDataIn( iData_EXE ),
|
.iDataIn( iData_EXE ),
|
.oDataOut0( wData_XMEM1 ),
|
.oDataOut0( wData_XMEM1 ),
|
.oDataOut1( wData_XMEM2 )
|
.oDataOut1( wData_XMEM2 )
|
);
|
);
|
|
|
|
|
UPCOUNTER_POSEDGE # (1) UPC1
|
UPCOUNTER_POSEDGE # (1) UPC1
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Initial(1'b0),
|
.Initial(1'b0),
|
.Enable(iFlipMemory),
|
.Enable(iFlipMemory),
|
.Q(wFlipSelect)
|
.Q(wFlipSelect)
|
);
|
);
|
|
|
|
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
/*
|
/*
|
Instruction memory.
|
Instruction memory.
|
*/
|
*/
|
|
|
// ROM_ADDRESS_WIDTH exceds the array size it may get trimmed...
|
// ROM_ADDRESS_WIDTH exceds the array size it may get trimmed...
|
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH,/*512*/128) INST_MEM //Only 128 instructions :( well this is for the user anyway
|
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH,/*512*/128) INST_MEM //Only 128 instructions :( well this is for the user anyway
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( iInstructionWriteEnable ),
|
.iWriteEnable( iInstructionWriteEnable ),
|
.iReadAddress0( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress0( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress1( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress1( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iWriteAddress( iInstructionWriteAddress ),
|
.iWriteAddress( iInstructionWriteAddress ),
|
.iDataIn( iInstruction ),
|
.iDataIn( iInstruction ),
|
.oDataOut0( wIMEM2_IMUX__DataOut1 ),
|
.oDataOut0( wIMEM2_IMUX__DataOut1 ),
|
.oDataOut1( wIMEM2_IMUX__DataOut2 )
|
.oDataOut1( wIMEM2_IMUX__DataOut2 )
|
|
|
);
|
);
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
/*
|
/*
|
Default code stored in ROM.
|
Default code stored in ROM.
|
*/
|
*/
|
wire [`INSTRUCTION_WIDTH-1:0] wRomDelay1,wRomDelay2;
|
wire [`INSTRUCTION_WIDTH-1:0] wRomDelay1,wRomDelay2;
|
//In real world ROM will take at least 1 clock cycle,
|
//In real world ROM will take at least 1 clock cycle,
|
//since ROMs are not syhtethizable, I won't hurt to put
|
//since ROMs are not syhtethizable, I won't hurt to put
|
//this delay
|
//this delay
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDA
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDA
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset(Reset),
|
.Reset(Reset),
|
.Enable(1'b1),
|
.Enable(1'b1),
|
.D(wRomDelay1),
|
.D(wRomDelay1),
|
.Q(wIROM2_IMUX__DataOut1 )
|
.Q(wIROM2_IMUX__DataOut1 )
|
);
|
);
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDB
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDB
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset(Reset),
|
.Reset(Reset),
|
.Enable(1'b1),
|
.Enable(1'b1),
|
.D(wRomDelay2),
|
.D(wRomDelay2),
|
.Q(wIROM2_IMUX__DataOut2 )
|
.Q(wIROM2_IMUX__DataOut2 )
|
);
|
);
|
|
|
//The reason I put two ROMs is because I need to read 2 different Instruction
|
//The reason I put two ROMs is because I need to read 2 different Instruction
|
//addresses at the same time (branch-taken and branch-not-taken) and not sure
|
//addresses at the same time (branch-taken and branch-not-taken) and not sure
|
//how to write dual read channel ROM this way...
|
//how to write dual read channel ROM this way...
|
|
|
ROM IROM
|
ROM IROM
|
(
|
(
|
.Address( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.Address( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
`ifdef DEBUG
|
`ifdef DEBUG
|
.iDebug_CoreID(iDebug_CoreID),
|
.iDebug_CoreID(iDebug_CoreID),
|
`endif
|
`endif
|
.I( wRomDelay1 )
|
.I( wRomDelay1 )
|
);
|
);
|
|
|
ROM IROM2
|
ROM IROM2
|
(
|
(
|
.Address( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.Address( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
`ifdef DEBUG
|
`ifdef DEBUG
|
.iDebug_CoreID(iDebug_CoreID),
|
.iDebug_CoreID(iDebug_CoreID),
|
`endif
|
`endif
|
.I( wRomDelay2 )
|
.I( wRomDelay2 )
|
);
|
);
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
ControlRegister CR
|
ControlRegister CR
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iControlRegister( iControlRegister ),
|
.iControlRegister( iControlRegister ),
|
.oControlRegister( oControlRegister )
|
.oControlRegister( oControlRegister )
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
