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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*******************************************************************************
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/*******************************************************************************
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Module Description:
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Module Description:
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This is the Main test bench of the GPU. It simulates the behavior of
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This is the Main test bench of the GPU. It simulates the behavior of
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an external control unit or CPU that sends configuration information into DUT.
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an external control unit or CPU that sends configuration information into DUT.
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It also implements a second processs that simulates a Wishbone slave that sends
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It also implements a second processs that simulates a Wishbone slave that sends
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data from an external memory. These blocks are just behavioral CTE and therefore
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data from an external memory. These blocks are just behavioral CTE and therefore
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are not meant to be synthethized.
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are not meant to be synthethized.
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*******************************************************************************/
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*******************************************************************************/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define RESOLUTION_WIDTH (rSceneParameters[13] >> `SCALE)
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`define RESOLUTION_WIDTH (rSceneParameters[13] >> `SCALE)
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`define RESOLUTION_HEIGHT (rSceneParameters[14] >> `SCALE)
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`define RESOLUTION_HEIGHT (rSceneParameters[14] >> `SCALE)
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`define DELTA_ROW (32'h1 << `SCALE)
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`define DELTA_ROW (32'h1 << `SCALE)
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`define DELTA_COL (32'h1 << `SCALE)
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`define DELTA_COL (32'h1 << `SCALE)
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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`define MAX_WIDTH 200
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`define MAX_WIDTH 200
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`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
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`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
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module TestBench_Theia;
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module TestBench_Theia;
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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//**WARNING: Declare all of your varaibles at the begining
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//**WARNING: Declare all of your varaibles at the begining
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//of the file. I hve noticed that sometimes the verilog
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//of the file. I hve noticed that sometimes the verilog
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//simulator allows you to use some regs even if they have not been
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//simulator allows you to use some regs even if they have not been
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//previously declared, leadeing to crahses or unexpected behavior
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//previously declared, leadeing to crahses or unexpected behavior
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// Inputs
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// Inputs
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reg Clock;
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reg Clock;
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reg Reset;
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reg Reset;
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wire [`WB_WIDTH-1:0] DAT_O;
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wire [`WB_WIDTH-1:0] DAT_O;
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reg ACK_O;
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reg ACK_O;
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wire ACK_I;
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wire ACK_I;
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wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
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wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
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wire WE_I,STB_I;
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wire WE_I,STB_I;
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wire CYC_O,WE_O,TGC_O,STB_O;
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wire CYC_O,WE_O,TGC_O,STB_O;
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wire [1:0] TGA_O;
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wire [1:0] TGA_O;
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wire [1:0] TGA_I;
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wire [1:0] TGA_I;
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reg [`WB_WIDTH-1:0] TMADR_O,TMDAT_O;
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reg [`WB_WIDTH-1:0] TMADR_O,TMDAT_O;
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reg [`MAX_TMEM_BANKS-1:0] TMSEL_O;
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reg [`MAX_TMEM_BANKS-1:0] TMSEL_O;
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reg TMWE_O;
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reg TMWE_O;
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reg [31:0] rControlRegister[2:0];
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reg [31:0] rControlRegister[2:0];
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integer file, log;
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integer file, log;
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reg [31:0] rSceneParameters[120:0];
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reg [31:0] rSceneParameters[120:0];
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reg [31:0] rVertexBuffer[7000:0];
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reg [31:0] rVertexBuffer[7000:0];
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reg [31:0] rInstructionBuffer[512:0];
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reg [31:0] rInstructionBuffer[512:0];
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
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reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
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wire wDone;
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wire wDone;
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wire [`MAX_CORES-1:0] RENDREN_O;
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wire [`MAX_CORES-1:0] RENDREN_O;
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reg [`MAX_CORE_BITS-1:0] wOMEMBankSelect;
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reg [`MAX_CORE_BITS-1:0] wOMEMBankSelect;
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reg [`WB_WIDTH-1:0] wOMEMReadAddr; //Output adress (relative to current bank)
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reg [`WB_WIDTH-1:0] wOMEMReadAddr; //Output adress (relative to current bank)
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wire [`WB_WIDTH-1:0] wOMEMData; //Output data bus (Wishbone)
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wire [`WB_WIDTH-1:0] wOMEMData; //Output data bus (Wishbone)
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reg rHostEnable;
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reg rHostEnable;
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integer k,out2;
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integer k,out2;
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wire GRDY_I;
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wire GRDY_I;
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wire GACK_O;
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wire GACK_O;
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wire STDONE_O;
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wire STDONE_O;
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wire wGPUCommitedResults;
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wire wGPUCommitedResults;
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wire wHostDataAvailable;
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wire wHostDataAvailable;
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wire[`WB_WIDTH-1:0] wHostReadAddress;
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wire[`WB_WIDTH-1:0] wHostReadAddress;
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wire[`WB_WIDTH-1:0] wMemorySize;
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wire[`WB_WIDTH-1:0] wMemorySize;
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wire[1:0] wMemSelect;
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wire[1:0] wMemSelect;
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX2
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX2
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(
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(
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.Sel( wMemSelect ),
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.Sel( wMemSelect ),
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.I1( rInstructionBuffer[0] ),
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.I1( rInstructionBuffer[0] ),
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.I2( rSceneParameters[0] ),
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.I2( rSceneParameters[0] ),
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.I3( rVertexBuffer[0] ),
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.I3( rVertexBuffer[0] ),
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.I4(0),
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.I4(0),
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.O1(wMemorySize)
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.O1(wMemorySize)
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);
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);
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//---------------------------------------------
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//---------------------------------------------
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top Top
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top Top
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iHostEnable( rHostEnable ),
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.iHostEnable( rHostEnable ),
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.oHostReadAddress( wHostReadAddress),
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.oHostReadAddress( wHostReadAddress),
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.iMemorySize( wMemorySize ),
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.iMemorySize( wMemorySize ),
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.oMemSelect( wMemSelect ),
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.oMemSelect( wMemSelect ),
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.iInstruction( rInstructionBuffer[wHostReadAddress] ),
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.iInstruction( rInstructionBuffer[wHostReadAddress] ),
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.iParameter( rSceneParameters[wHostReadAddress] ),
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.iParameter( rSceneParameters[wHostReadAddress] ),
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.iVertex( rVertexBuffer[wHostReadAddress] ),
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.iVertex( rVertexBuffer[wHostReadAddress] ),
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.iControlRegister( rControlRegister[0] ),
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.iControlRegister( rControlRegister[0] ),
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.iPrimitiveCount( (rVertexBuffer[6]+1) *7 ),
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.iPrimitiveCount( (rVertexBuffer[6]+1) *7 ),
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.iTMEMAdr( TMADR_O ),
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.iTMEMAdr( TMADR_O ),
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.iTMEMData( TMDAT_O ),
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.iTMEMData( TMDAT_O ),
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.iTMEM_WE( TMWE_O ),
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.iTMEM_WE( TMWE_O ),
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.iTMEM_Sel( TMSEL_O ),
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.iTMEM_Sel( TMSEL_O ),
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.iOMEMBankSelect( wOMEMBankSelect ),
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.iOMEMBankSelect( wOMEMBankSelect ),
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.iOMEMReadAddress( wOMEMReadAddr ),
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.iOMEMReadAddress( wOMEMReadAddr ),
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.oOMEMData( wOMEMData ),
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.oOMEMData( wOMEMData ),
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.iWidth(`RESOLUTION_WIDTH),
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.iWidth(`RESOLUTION_WIDTH),
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.iHeight(`RESOLUTION_HEIGHT),
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.iHeight(`RESOLUTION_HEIGHT),
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.oDone( wDone )
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.oDone( wDone )
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);
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);
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//---------------------------------------------
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//---------------------------------------------
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//generate the clock signal here
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//generate the clock signal here
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always begin
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always begin
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#`CLOCK_CYCLE Clock = ! Clock;
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#`CLOCK_CYCLE Clock = ! Clock;
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end
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end
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//---------------------------------------------
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//---------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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/*
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/*
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This makes sure the simulation actually writes the results to the PPM image file
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This makes sure the simulation actually writes the results to the PPM image file
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once all the cores are done executing
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once all the cores are done executing
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*/
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*/
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`define PARTITION_SIZE `RESOLUTION_HEIGHT/`MAX_CORES
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`define PARTITION_SIZE `RESOLUTION_HEIGHT/`MAX_CORES
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integer i,j,kk;
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integer i,j,kk;
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reg [31:0] R;
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reg [31:0] R;
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always @ ( * )
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always @ ( * )
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begin
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begin
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if (wDone == 1'b1)
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if (wDone == 1'b1)
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begin
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begin
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$display("Partition Size = %d",`PARTITION_SIZE);
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$display("Partition Size = %d",`PARTITION_SIZE);
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for (kk = 0; kk < `MAX_CORES; kk = kk+1)
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for (kk = 0; kk < `MAX_CORES; kk = kk+1)
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begin
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begin
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wOMEMBankSelect = kk;
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wOMEMBankSelect = kk;
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$display("wOMEMBankSelect = %d\n",wOMEMBankSelect);
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$display("wOMEMBankSelect = %d\n",wOMEMBankSelect);
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for (j=0; j < `PARTITION_SIZE; j=j+1)
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for (j=0; j < `PARTITION_SIZE; j=j+1)
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begin
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begin
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for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
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for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
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begin
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begin
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wOMEMReadAddr = i+j*`RESOLUTION_WIDTH*3;
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wOMEMReadAddr = i+j*`RESOLUTION_WIDTH*3;
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#`CLOCK_PERIOD;
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#`CLOCK_PERIOD;
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#1;
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#1;
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R = ((wOMEMData >> (`SCALE-8)) > 255) ? 255 : (wOMEMData >> (`SCALE-8));
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R = ((wOMEMData >> (`SCALE-8)) > 255) ? 255 : (wOMEMData >> (`SCALE-8));
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$fwrite(out2,"%d " , R );
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$fwrite(out2,"%d " , R );
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if ((i %3) == 0)
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if ((i %3) == 0)
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$fwrite(out2,"\n# %d %d\n",i/3,j);
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$fwrite(out2,"\n# %d %d\n",i/3,j);
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end
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end
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end
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end
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end
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end
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$fclose(out2);
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$fclose(out2);
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$fwrite(log, "Simulation end time : %dns\n",$time);
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$fwrite(log, "Simulation end time : %dns\n",$time);
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$fclose(log);
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$fclose(log);
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$stop();
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$stop();
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end
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end
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end
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end
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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reg [15:0] rTimeOut;
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reg [15:0] rTimeOut;
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// `define MAX_INSTRUCTIONS 2
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// `define MAX_INSTRUCTIONS 2
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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Clock = 0;
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Clock = 0;
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Reset = 0;
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Reset = 0;
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rTimeOut = 0;
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rTimeOut = 0;
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rHostEnable = 0;
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rHostEnable = 0;
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//Read Config register values
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//Read Config register values
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$write("Loading control register.... ");
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$write("Loading control register.... ");
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$readmemh("Creg.mem",rControlRegister);
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$readmemh("Creg.mem",rControlRegister);
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$display("Done");
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$display("Done");
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//Read configuration Data
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//Read configuration Data
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$write("Loading scene parameters.... ");
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$write("Loading scene parameters.... ");
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$readmemh("Params.mem", rSceneParameters );
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$readmemh("Params.mem", rSceneParameters );
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$display("Done");
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$display("Done");
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//Read Scene Data
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//Read Scene Data
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$write("Loading scene geometry.... ");
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$write("Loading scene geometry.... ");
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$readmemh("Vertex.mem",rVertexBuffer);
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$readmemh("Vertex.mem",rVertexBuffer);
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$display("Done");
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$display("Done");
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$display("Number of primitives(%d): %d",rVertexBuffer[6],(rVertexBuffer[6]+1) *7);
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$display("Number of primitives(%d): %d",rVertexBuffer[6],(rVertexBuffer[6]+1) *7);
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//Read Texture Data
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//Read Texture Data
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$write("Loading scene texture.... ");
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$write("Loading scene texture.... ");
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$readmemh("Textures.mem",rTextures);
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$readmemh("Textures.mem",rTextures);
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$display("Done");
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$display("Done");
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//Read instruction data
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//Read instruction data
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$write("Loading code allocation table and user shaders.... ");
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$write("Loading code allocation table and user shaders.... ");
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$readmemh("Instructions.mem",rInstructionBuffer);
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$readmemh("Instructions.mem",rInstructionBuffer);
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$display("Done");
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$display("Done");
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$display("Control Register : %b",rControlRegister[0]);
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$display("Control Register : %b",rControlRegister[0]);
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$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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//Open output file
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//Open output file
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out2 = $fopen("Output.ppm");
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out2 = $fopen("Output.ppm");
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$fwrite(out2,"P3\n");
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$fwrite(out2,"P3\n");
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$fwrite(out2,"#This file was generated by Theia's RTL simulation\n");
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$fwrite(out2,"#This file was generated by Theia's RTL simulation\n");
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$fwrite(out2,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$fwrite(out2,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$fwrite(out2,"255\n");
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$fwrite(out2,"255\n");
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#10
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#10
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Reset = 1;
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Reset = 1;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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TMWE_O = 1;
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TMWE_O = 1;
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#100 Reset = 0;
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#100 Reset = 0;
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TMWE_O = 1;
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TMWE_O = 1;
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$display("Intilializing TMEM @ %dns",$time);
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$display("Intilializing TMEM @ %dns",$time);
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//starts in 2 to skip Width and Height
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//starts in 2 to skip Width and Height
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for (k = 0;k < `TEXTURE_BUFFER_SIZE; k = k + 1)
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for (k = 0;k < `TEXTURE_BUFFER_SIZE; k = k + 1)
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begin
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begin
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TMADR_O <= (k >> (`MAX_CORE_BITS));
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TMADR_O <= (k >> (`MAX_CORE_BITS));
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TMSEL_O <= (k & (`MAX_TMEM_BANKS-1)); //X mod 2^n == X & (2^n - 1)
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TMSEL_O <= (k & (`MAX_TMEM_BANKS-1)); //X mod 2^n == X & (2^n - 1)
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TMDAT_O <= rTextures[k];
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TMDAT_O <= rTextures[k];
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#10;
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#10;
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if ((k % (256*3)) == 0)
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if ((k % (256*3)) == 0)
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begin
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begin
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$write("|");
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$write("|");
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$fflush;
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$fflush;
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end
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end
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end
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end
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$display("\nDone Intilializing TMEM @ %dns",$time);
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$display("\nDone Intilializing TMEM @ %dns",$time);
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TMWE_O = 0;
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TMWE_O = 0;
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rHostEnable = 1;
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rHostEnable = 1;
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log = $fopen("Simulation.log");
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log = $fopen("Simulation.log");
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$fwrite(log, "Simulation start time : %dns\n",$time);
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$fwrite(log, "Simulation start time : %dns\n",$time);
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$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
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$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
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$fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
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$fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
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//Start dumping VCD
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//Start dumping VCD
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$display("-I- Starting VCD Dump\n");
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$display("-I- Starting VCD Dump\n");
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// $dumpfile("TestBench_Theia.vcd");
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// $dumpfile("TestBench_Theia.vcd");
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// $dumpvars(0,TestBench_Theia);
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// $dumpvars(0,TestBench_Theia);
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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No newline at end of file
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No newline at end of file
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