`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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`define EXEU_AFTER_RESET 0
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`define EXEU_AFTER_RESET 0
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`define EXEU_INITIAL_STATE 1
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`define EXEU_INITIAL_STATE 1
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`define EXEU_WAIT_FOR_DECODE 2
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`define EXEU_WAIT_FOR_DECODE 2
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`define EXEU_FETCH_DECODED_INST 3
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`define EXEU_FETCH_DECODED_INST 3
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`define EXEU_WAIT_FOR_ALU_EXECUTION 4
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`define EXEU_WAIT_FOR_ALU_EXECUTION 4
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`define EXEU_WRITE_BACK_TO_RAM 5
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`define EXEU_WRITE_BACK_TO_RAM 5
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`define EXEU_HANDLE_JUMP 7
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`define EXEU_HANDLE_JUMP 7
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module ExecutionFSM
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module ExecutionFSM
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iDecodeDone,
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input wire iDecodeDone,
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input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
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input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
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input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
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input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
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inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
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inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
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//output reg ReadyForNextInstruction,
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//output reg ReadyForNextInstruction,
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output wire oJumpFlag ,
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output wire oJumpFlag ,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
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output wire oRAMWriteEnable ,
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output wire oRAMWriteEnable ,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
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output wire oExeLatchedValues,
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output wire oExeLatchedValues,
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output reg oBusy ,
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output reg oBusy ,
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//ALU ports and control signals
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//ALU ports and control signals
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output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
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output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
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output wire [`WIDTH-1:0] oALUChannelX1,
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output wire [`WIDTH-1:0] oALUChannelX1,
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output wire [`WIDTH-1:0] oALUChannelY1,
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output wire [`WIDTH-1:0] oALUChannelY1,
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output wire [`WIDTH-1:0] oALUChannelZ1,
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output wire [`WIDTH-1:0] oALUChannelZ1,
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output wire [`WIDTH-1:0] oALUChannelX2,
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output wire [`WIDTH-1:0] oALUChannelX2,
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output wire [`WIDTH-1:0] oALUChannelY2,
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output wire [`WIDTH-1:0] oALUChannelY2,
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output wire [`WIDTH-1:0] oALUChannelZ2,
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output wire [`WIDTH-1:0] oALUChannelZ2,
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output wire oTriggerALU,
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output wire oTriggerALU,
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input wire [`WIDTH-1:0] iALUResultX,
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input wire [`WIDTH-1:0] iALUResultX,
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input wire [`WIDTH-1:0] iALUResultY,
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input wire [`WIDTH-1:0] iALUResultY,
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input wire [`WIDTH-1:0] iALUResultZ,
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input wire [`WIDTH-1:0] iALUResultZ,
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input wire iALUOutputReady,
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input wire iALUOutputReady,
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input wire iBranchTaken,
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input wire iBranchTaken,
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input wire iBranchNotTaken,
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input wire iBranchNotTaken,
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`ifdef DEBUG
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`ifdef DEBUG
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input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
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input wire [`MAX_CORES-1:0] iDebug_CoreID,
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input wire [`MAX_CORES-1:0] iDebug_CoreID,
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`endif
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`endif
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//Data forward Signals
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//Data forward Signals
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output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
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output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
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);
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);
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wire wLatchNow;
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wire wLatchNow;
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reg rInputLatchesEnabled;
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reg rInputLatchesEnabled;
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//If ALU says jump, just pass along
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//If ALU says jump, just pass along
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assign oJumpFlag = iBranchTaken;
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assign oJumpFlag = iBranchTaken;
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//JumpIP is the instruction destination (= oRAMWriteAddress)
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//JumpIP is the instruction destination (= oRAMWriteAddress)
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assign oJumpIp = oRAMWriteAddress;
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assign oJumpIp = oRAMWriteAddress;
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assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
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assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
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assign oExeLatchedValues = wLatchNow;
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assign oExeLatchedValues = wLatchNow;
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assign oTriggerALU = wLatchNow;
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assign oTriggerALU = wLatchNow;
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wire wOperationIsJump;
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wire wOperationIsJump;
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assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
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assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
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//Don't allow me to write back back if the operation is a NOP
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//Don't allow me to write back back if the operation is a NOP
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`ifdef DEBUG
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`ifdef DEBUG
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
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(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
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(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
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`else
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`else
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
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`endif
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`endif
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assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
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assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
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assign oALUChannelX1 = iSource1[95:64];
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assign oALUChannelX1 = iSource1[95:64];
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assign oALUChannelY1 = iSource1[63:32];
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assign oALUChannelY1 = iSource1[63:32];
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assign oALUChannelZ1 = iSource1[31:0];
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assign oALUChannelZ1 = iSource1[31:0];
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assign oALUChannelX2 = iSource0[95:64];
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assign oALUChannelX2 = iSource0[95:64];
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assign oALUChannelY2 = iSource0[63:32];
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assign oALUChannelY2 = iSource0[63:32];
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assign oALUChannelZ2 = iSource0[31:0];
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assign oALUChannelZ2 = iSource0[31:0];
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/*
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/*
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource1[95:64] ),
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.D( iSource1[95:64] ),
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.Q( oALUChannelX1 )
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.Q( oALUChannelX1 )
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);
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource1[63:32] ),
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.D( iSource1[63:32] ),
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.Q( oALUChannelY1 )
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.Q( oALUChannelY1 )
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);
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource1[31:0] ),
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.D( iSource1[31:0] ),
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.Q( oALUChannelZ1 )
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.Q( oALUChannelZ1 )
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);
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);
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*/
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*/
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/*
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[95:64] ),
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.D( iSource1[95:64] ),
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.Q(oALUChannelX1)
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.Q(oALUChannelX1)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[63:32] ),
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.D( iSource1[63:32] ),
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.Q(oALUChannelY1)
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.Q(oALUChannelY1)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[31:0] ),
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.D( iSource1[31:0] ),
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.Q(oALUChannelZ1)
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.Q(oALUChannelZ1)
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);
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);
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*/
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*/
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/*
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/*
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource0[95:64] ),
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.D( iSource0[95:64] ),
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.Q( oALUChannelX2 )
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.Q( oALUChannelX2 )
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);
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource0[63:32] ),
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.D( iSource0[63:32] ),
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.Q( oALUChannelY2 )
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.Q( oALUChannelY2 )
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);
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iSource0[31:0] ),
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.D( iSource0[31:0] ),
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.Q( oALUChannelZ2 )
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.Q( oALUChannelZ2 )
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);
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);
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*/
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*/
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/*
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[95:64] ),
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.D( iSource0[95:64] ),
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.Q(oALUChannelX2)
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.Q(oALUChannelX2)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[63:32] ),
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.D( iSource0[63:32] ),
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.Q(oALUChannelY2)
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.Q(oALUChannelY2)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[31:0] ),
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.D( iSource0[31:0] ),
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.Q(oALUChannelZ2)
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.Q(oALUChannelZ2)
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);
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);
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*/
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*/
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//Finally one more latch to store
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//Finally one more latch to store
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//the iOperation and the destination
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//the iOperation and the destination
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assign oALUOperation = iOperation;
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assign oALUOperation = iOperation;
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//assign oRAMWriteAddress = iDestination;
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//assign oRAMWriteAddress = iDestination;
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/*
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/*
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FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
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FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iOperation ),
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.D( iOperation ),
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.Q( oALUOperation )
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.Q( oALUOperation )
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|
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);
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);
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FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
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FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
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(
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(
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.Clock( wLatchNow ),
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.Clear( Reset ),
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.D( iDestination ),
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.D( iDestination ),
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.Q( oRAMWriteAddress )
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.Q( oRAMWriteAddress )
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|
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);
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);
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*/
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*/
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/*
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iOperation ),
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.D( iOperation ),
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.Q(oALUOperation)
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.Q(oALUOperation)
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);
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);
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*/
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*/
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
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(
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(
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.Clock( Clock ),//wLatchNow ),
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iDestination ),
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.D( iDestination ),
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.Q(oRAMWriteAddress)
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.Q(oRAMWriteAddress)
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);
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);
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|
//Data forwarding
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//Data forwarding
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assign oLastDestination = oRAMWriteAddress;
|
assign oLastDestination = oRAMWriteAddress;
|
|
|
reg [7:0] CurrentState;
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reg [7:0] CurrentState;
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reg [7:0] NextState;
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reg [7:0] NextState;
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//------------------------------------------------
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//------------------------------------------------
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always @(posedge Clock or posedge Reset)
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always @(posedge Clock or posedge Reset)
|
begin
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begin
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|
|
|
|
|
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if (Reset)
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if (Reset)
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CurrentState <= `EXEU_AFTER_RESET;
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CurrentState <= `EXEU_AFTER_RESET;
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else
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else
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CurrentState <= NextState;
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CurrentState <= NextState;
|
|
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end
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end
|
//------------------------------------------------
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//------------------------------------------------
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|
|
|
|
always @( * )
|
always @( * )
|
begin
|
begin
|
case (CurrentState)
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case (CurrentState)
|
//------------------------------------------
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//------------------------------------------
|
`EXEU_AFTER_RESET:
|
`EXEU_AFTER_RESET:
|
begin
|
begin
|
//ReadyForNextInstruction <= 1;
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//ReadyForNextInstruction <= 1;
|
oBusy <= 0;
|
oBusy <= 0;
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rInputLatchesEnabled <= 1;
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rInputLatchesEnabled <= 1;
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|
|
|
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NextState <= `EXEU_WAIT_FOR_DECODE;
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NextState <= `EXEU_WAIT_FOR_DECODE;
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end
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end
|
//------------------------------------------
|
//------------------------------------------
|
/**
|
/**
|
At the same time iDecodeDone goes to 1, our Flops
|
At the same time iDecodeDone goes to 1, our Flops
|
will store the value, so next clock cycle we can
|
will store the value, so next clock cycle we can
|
tell IDU to go ahead and decode the next instruction
|
tell IDU to go ahead and decode the next instruction
|
in the pipeline.
|
in the pipeline.
|
*/
|
*/
|
`EXEU_WAIT_FOR_DECODE:
|
`EXEU_WAIT_FOR_DECODE:
|
begin
|
begin
|
|
|
|
|
//ReadyForNextInstruction <= 1;
|
//ReadyForNextInstruction <= 1;
|
oBusy <= 0;
|
oBusy <= 0;
|
rInputLatchesEnabled <= 1;
|
rInputLatchesEnabled <= 1;
|
|
|
|
|
if ( iDecodeDone ) //This same thing triggers the ALU
|
if ( iDecodeDone ) //This same thing triggers the ALU
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
else
|
else
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
end
|
end
|
//------------------------------------------
|
//------------------------------------------
|
/*
|
/*
|
If the instruction is aritmetic then pass the parameters
|
If the instruction is aritmetic then pass the parameters
|
the ALU, else if it store iOperation then...
|
the ALU, else if it store iOperation then...
|
*/
|
*/
|
`EXEU_WAIT_FOR_ALU_EXECUTION:
|
`EXEU_WAIT_FOR_ALU_EXECUTION:
|
begin
|
begin
|
|
|
//ReadyForNextInstruction <= 0; //*
|
//ReadyForNextInstruction <= 0; //*
|
oBusy <= 1;
|
oBusy <= 1;
|
rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!
|
rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!
|
|
|
|
|
|
|
if ( iALUOutputReady ) /////This same thing enables writing th results to RAM
|
if ( iALUOutputReady ) /////This same thing enables writing th results to RAM
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
else
|
else
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
end
|
end
|
//------------------------------------------
|
//------------------------------------------
|
`EXEU_WRITE_BACK_TO_RAM:
|
`EXEU_WRITE_BACK_TO_RAM:
|
begin
|
begin
|
|
|
//ReadyForNextInstruction <= 0;
|
//ReadyForNextInstruction <= 0;
|
oBusy <= 1;
|
oBusy <= 1;
|
rInputLatchesEnabled <= 1;
|
rInputLatchesEnabled <= 1;
|
|
|
if ( iDecodeDone )
|
if ( iDecodeDone )
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
|
else
|
else
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
NextState <= `EXEU_WAIT_FOR_DECODE;
|
|
|
end
|
end
|
|
|
//------------------------------------------
|
//------------------------------------------
|
default:
|
default:
|
begin
|
begin
|
|
|
//ReadyForNextInstruction <= 1;
|
//ReadyForNextInstruction <= 1;
|
oBusy <= 0;
|
oBusy <= 0;
|
rInputLatchesEnabled <= 1;
|
rInputLatchesEnabled <= 1;
|
|
|
NextState <= `EXEU_AFTER_RESET;
|
NextState <= `EXEU_AFTER_RESET;
|
end
|
end
|
//------------------------------------------
|
//------------------------------------------
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
`ifdef DUMP_CODE
|
`ifdef DUMP_CODE
|
integer ucode_file;
|
integer ucode_file;
|
integer reg_log;
|
integer reg_log;
|
initial
|
initial
|
begin
|
begin
|
|
|
$display("Opening ucode dump file....\n");
|
$display("Opening ucode dump file....\n");
|
ucode_file = $fopen("Code.log","w");
|
ucode_file = $fopen("Code.log","w");
|
$fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
|
$fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
|
$display("Opening Register lof file...\n");
|
$display("Opening Register lof file...\n");
|
reg_log = $fopen("Registers.log","w");
|
reg_log = $fopen("Registers.log","w");
|
|
|
end
|
end
|
|
|
`endif //Ucode dump
|
`endif //Ucode dump
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
`ifdef DEBUG
|
`ifdef DEBUG
|
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
|
wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
|
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
|
wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource1[95:64] ),
|
.D( iSource1[95:64] ),
|
.Q(wALUChannelX1)
|
.Q(wALUChannelX1)
|
);
|
);
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource1[63:32] ),
|
.D( iSource1[63:32] ),
|
.Q(wALUChannelY1)
|
.Q(wALUChannelY1)
|
);
|
);
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource1[31:0] ),
|
.D( iSource1[31:0] ),
|
.Q(wALUChannelZ1)
|
.Q(wALUChannelZ1)
|
);
|
);
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource0[95:64] ),
|
.D( iSource0[95:64] ),
|
.Q(wALUChannelX2)
|
.Q(wALUChannelX2)
|
);
|
);
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource0[63:32] ),
|
.D( iSource0[63:32] ),
|
.Q(wALUChannelY2)
|
.Q(wALUChannelY2)
|
);
|
);
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset),
|
.Reset( Reset),
|
.Enable( wLatchNow ),
|
.Enable( wLatchNow ),
|
.D( iSource0[31:0] ),
|
.D( iSource0[31:0] ),
|
.Q(wALUChannelZ2)
|
.Q(wALUChannelZ2)
|
);
|
);
|
|
|
|
|
always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
|
always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
|
begin
|
begin
|
`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
|
`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
|
end
|
end
|
|
|
always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
|
always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
|
begin
|
begin
|
if ( iALUOutputReady )
|
if ( iALUOutputReady )
|
begin
|
begin
|
|
|
|
|
if (iBranchTaken)
|
if (iBranchTaken)
|
`LOGME"<BT>");
|
`LOGME"<BT>");
|
|
|
if (iBranchNotTaken )
|
if (iBranchNotTaken )
|
`LOGME"<BNT>");
|
`LOGME"<BNT>");
|
|
|
if (oRAMWriteEnable)
|
if (oRAMWriteEnable)
|
`LOGME"<WE>");
|
`LOGME"<WE>");
|
|
|
`LOGME "(%dns ",$time);
|
`LOGME "(%dns ",$time);
|
case ( oALUOperation )
|
case ( oALUOperation )
|
`RETURN: `LOGME"RETURN");
|
`RETURN: `LOGME"RETURN");
|
`ADD: `LOGME"ADD");
|
`ADD: `LOGME"ADD");
|
`SUB: `LOGME"SUB");
|
`SUB: `LOGME"SUB");
|
`DIV: `LOGME"DIV");
|
`DIV: `LOGME"DIV");
|
`MUL: `LOGME"MUL");
|
`MUL: `LOGME"MUL");
|
`MAG: `LOGME"MAG");
|
`MAG: `LOGME"MAG");
|
`JGX: `LOGME"JGX");
|
`JGX: `LOGME"JGX");
|
`JLX: `LOGME"JLX");
|
`JLX: `LOGME"JLX");
|
`JGEX: `LOGME"JGEX");
|
`JGEX: `LOGME"JGEX");
|
`JGEY: `LOGME"JGEY");
|
`JGEY: `LOGME"JGEY");
|
`JGEZ: `LOGME"JGEZ");
|
`JGEZ: `LOGME"JGEZ");
|
`JLEX: `LOGME"JLEX");
|
`JLEX: `LOGME"JLEX");
|
`JLEY: `LOGME"JLEY");
|
`JLEY: `LOGME"JLEY");
|
`JLEZ: `LOGME"JLEZ");
|
`JLEZ: `LOGME"JLEZ");
|
`JMP: `LOGME"JMP");
|
`JMP: `LOGME"JMP");
|
`ZERO: `LOGME"ZERO");
|
`ZERO: `LOGME"ZERO");
|
`JNEX: `LOGME"JNEX");
|
`JNEX: `LOGME"JNEX");
|
`JNEY: `LOGME"JNEY");
|
`JNEY: `LOGME"JNEY");
|
`JNEZ: `LOGME"JNEZ");
|
`JNEZ: `LOGME"JNEZ");
|
`JEQX: `LOGME"JEQX");
|
`JEQX: `LOGME"JEQX");
|
`JEQY: `LOGME"JEQY");
|
`JEQY: `LOGME"JEQY");
|
`JEQZ: `LOGME"JEQZ");
|
`JEQZ: `LOGME"JEQZ");
|
`CROSS: `LOGME"CROSS");
|
`CROSS: `LOGME"CROSS");
|
`DOT: `LOGME"DOT");
|
`DOT: `LOGME"DOT");
|
`SETX: `LOGME"SETX");
|
`SETX: `LOGME"SETX");
|
`SETY: `LOGME"SETY");
|
`SETY: `LOGME"SETY");
|
`SETZ: `LOGME"SETZ");
|
`SETZ: `LOGME"SETZ");
|
`NOP: `LOGME"NOP");
|
`NOP: `LOGME"NOP");
|
`COPY: `LOGME"COPY");
|
`COPY: `LOGME"COPY");
|
`INC: `LOGME"INC");
|
`INC: `LOGME"INC");
|
`DEC: `LOGME"DEC");
|
`DEC: `LOGME"DEC");
|
`MOD: `LOGME"MOD");
|
`MOD: `LOGME"MOD");
|
`FRAC: `LOGME"FRAC");
|
`FRAC: `LOGME"FRAC");
|
`NEG: `LOGME"NEG");
|
`NEG: `LOGME"NEG");
|
`SWIZZLE3D: `LOGME"SWIZZLE3D");
|
`SWIZZLE3D: `LOGME"SWIZZLE3D");
|
`MULP: `LOGME"MULP");
|
`MULP: `LOGME"MULP");
|
`XCHANGEX: `LOGME"XCHANGEX");
|
`XCHANGEX: `LOGME"XCHANGEX");
|
`IMUL: `LOGME"IMUL");
|
`IMUL: `LOGME"IMUL");
|
`UNSCALE: `LOGME"UNSCALE");
|
`UNSCALE: `LOGME"UNSCALE");
|
`INCX: `LOGME"INCX");
|
`INCX: `LOGME"INCX");
|
`INCY: `LOGME"INCY");
|
`INCY: `LOGME"INCY");
|
`INCZ: `LOGME"INCZ");
|
`INCZ: `LOGME"INCZ");
|
`DEBUG_PRINT:
|
`DEBUG_PRINT:
|
begin
|
begin
|
`LOGME"DEBUG_PRINT");
|
`LOGME"DEBUG_PRINT");
|
|
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
`LOGME"**********ERROR UNKNOWN OP*********");
|
`LOGME"**********ERROR UNKNOWN OP*********");
|
$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
|
$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
|
// $stop();
|
// $stop();
|
end
|
end
|
endcase
|
endcase
|
|
|
`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
|
`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
|
oRAMWriteAddress,
|
oRAMWriteAddress,
|
wALUChannelX1,wALUChannelY1,wALUChannelZ1,
|
wALUChannelX1,wALUChannelY1,wALUChannelZ1,
|
wALUChannelX2,wALUChannelY2,wALUChannelZ2
|
wALUChannelX2,wALUChannelY2,wALUChannelZ2
|
|
|
);
|
);
|
|
|
if (oALUOperation == `RETURN)
|
if (oALUOperation == `RETURN)
|
`LOGME"\n\n\n");
|
`LOGME"\n\n\n");
|
|
|
end
|
end
|
end //always
|
end //always
|
|
|
always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
|
always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
|
begin
|
begin
|
if ( iALUOutputReady )
|
if ( iALUOutputReady )
|
`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
|
`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
|
end //always
|
end //always
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
