`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/**********************************************************************************
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`define IFU_AFTER_RESET 0
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Description:
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`define IFU_INITIAL_STATE 1
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This is the instruction fetch unit.
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`define IFU_WAIT_FOR_LAST_INSTRUCTION_LATCHED_BY_IDU 2
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It gets the next instruction from the IMEM module at the MEM unit.
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`define IFU_STALLED 3
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It increments the instruction pointer (IP) in such a way that EXE has always
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`define IFU_FETCH_NEXT 4
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one instruction per clock cycle (best pipeline performance). In order to achieve this,
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`define FU_WAIT_FOR_EXE_UNIT 5
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IFU has 2 instruction pointers, so that in case of 'branch' instructions,
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`define IFU_DONE 6
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two instructions pointer are generated and two different instructions are simultaneously
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`define IFU_CHECK_FOR_JUMP_PENDING 7
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fetched from IMEM: the branch-taken and branch-not-taken instructions, so that once the
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branch outcome is calculted in EXE, both possible outcomes are already pre-fetched.
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**********************************************************************************/
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`define IP_SET_VALUE_INITIAL_ADDRESS 0
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module InstructionFetch
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`define IP_SET_VALUE_BRANCH_ADDRESS 1
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//-----------------------------------------------------------------------------
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module InstructionFetchUnit
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iBranchTaken,
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input wire iBranchNotTaken,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iJumpIp,
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input wire iTrigger,
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input wire iTrigger,
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input wire iIDUBusy,
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input wire iExeBusy,
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input wire[`INSTRUCTION_WIDTH-1:0] iEncodedInstruction,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress,
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input wire iDecodeUnitLatchedValues,
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction1, //Branch not taken instruction
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output reg oExecutionDone,
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction2, //Branch taken instruction
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output wire oMicroCodeReturnValue,
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input wire iBranchTaken,
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output wire oInstructionAvalable,
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output wire oInstructionAvalable,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionPointer,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP,
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output wire[`INSTRUCTION_WIDTH-1:0] oCurrentInstruction
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP2, //calcule both decide later
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output wire[`INSTRUCTION_WIDTH-1:0] oCurrentInstruction,
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input wire iEXEDone,
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output wire oMicroCodeReturnValue,
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output wire oExecutionDone
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);
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);
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`define INSTRUCTION_OPCODE oCurrentInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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//iInstruction1[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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//Alling the Jump Signal to the negedge of Clock,
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assign oMicroCodeReturnValue = oCurrentInstruction[0];
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//I do this because I finded out the simulator
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assign oIP2 = oCurrentInstruction[47:32];//iInstruction1[47:32];
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//behaves funny if you change a value at the edge
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//of the clock and read from a bus that has changed
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wire rJumpNow;
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assign oCurrentInstruction = iEncodedInstruction;
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assign oMicroCodeReturnValue = iEncodedInstruction[0];
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wire [`ROM_ADDRESS_WIDTH-1:0] wInstructionPointer;
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reg rEnable;
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assign oInstructionPointer = wInstructionPointer;
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reg rPreviousInstructionIsJump;
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`define INSTRUCTION_OPCODE iEncodedInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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wire wTriggerDelay1,wTriggerDelay2,wIncrementIP_Delay1,wIncrementIP_Delay2,
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wLastInst_Delay1,wLastInst_Delay2;
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wire wIncrementIP,wLastInstruction;
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wire wLastInstruction;
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assign wLastInstruction =
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(`INSTRUCTION_OPCODE == 0) ? 1'b1 : 1'b0;
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wire rInstructionAvalable;
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assign wLastInstruction = (`INSTRUCTION_OPCODE == `RETURN);
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assign rInstructionAvalable = (iTrigger || iDecodeUnitLatchedValues) && rEnable;
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//Increment IP 2 cycles after trigger or everytime EXE is done, but stop if we get to the RETURN
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assign wIncrementIP = wTriggerDelay2 | (iEXEDone & ~wLastInstruction);
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//It takes 1 clock cycle to read the instruction back from IMEM
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assign oInstructionAvalable = wTriggerDelay2 | (iEXEDone & ~wLastInst_Delay2);
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//Once we reach the last instruction, wait until EXE says he is done, then assert oExecutionDone
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assign oExecutionDone = (wLastInstruction & iEXEDone);
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//if it is jump delay 1 cycle
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
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wire wInstructionAvalableDelayed_1Cycle;
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wire wInstructionAvalableDelayed_2Cycle;
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wire wInstructionAvalableDelayed_3Cycle;
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wire wInstructionAvalableDelayed_4Cycle;
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wire wJumpNow_Delayed_1Cycle,wJumpNow_Delayed_2Cycle,wJumpNow_Delayed_3Cycle;
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelayJump
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( rJumpNow ),
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.Enable(1'b1),
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.Q( wJumpNow_Delayed_1Cycle )
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.D( iTrigger ),
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);
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.Q( wTriggerDelay1 )
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelayJump2
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(
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.Clock( Clock ),
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.Clear( Reset ),
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.D( wJumpNow_Delayed_1Cycle ),
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.Q( wJumpNow_Delayed_2Cycle )
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);
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);
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelayJump3
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( wJumpNow_Delayed_2Cycle ),
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.Enable(1'b1),
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.Q( wJumpNow_Delayed_3Cycle )
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.D( wTriggerDelay1 ),
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.Q( wTriggerDelay2 )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelay1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( rInstructionAvalable ),
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.Enable(wLastInstruction),
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.Q( wInstructionAvalableDelayed_1Cycle )
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.D( oInstructionAvalable ),
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.Q( wLastInst_Delay1 )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelay2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( wInstructionAvalableDelayed_1Cycle ),
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.Enable(wLastInstruction),
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.Q( wInstructionAvalableDelayed_2Cycle )
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.D( wLastInst_Delay1 ),
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.Q( wLastInst_Delay2 )
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);
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);
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wire [`ROM_ADDRESS_WIDTH-1:0] oIP2_Next;
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/*
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In case the branch is taken:
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We point current instruction into the iInstruction2 (branch-taken) instruction
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that corresponds to oIP2.
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Then, in the next clock cycle we should use the oIP2 incremented by one,
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so we need to load UPCOUNTER_POSEDGE with oIP2+1
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*/
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelay3
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(
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.Clock( Clock ),
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.Clear( Reset ),
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.D( wInstructionAvalableDelayed_2Cycle ),
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.Q( wInstructionAvalableDelayed_3Cycle )
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);
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//If the branch was taken, then use the pre-fetched instruction (iInstruction2)
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelay4A
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wire[`INSTRUCTION_WIDTH-1:0] wCurrentInstruction_Delay1,wCurrentInstruction_BranchTaken;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDX
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( wInstructionAvalableDelayed_3Cycle ),
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.Enable(iBranchTaken),
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.Q( wInstructionAvalableDelayed_4Cycle )
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.D( oCurrentInstruction ),
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.Q( wCurrentInstruction_Delay1 )
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);
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);
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wire wBranchTaken_Delay1;
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assign oInstructionAvalable = (wInstructionAvalableDelayed_1Cycle && !rJumpNow) ||
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDY
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(wInstructionAvalableDelayed_3Cycle && wJumpNow_Delayed_2Cycle);
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wire wInstructionAvalableDelayed;
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FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFDelay4
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Clear( Reset ),
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.Reset( Reset ),
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.D( oInstructionAvalable ),
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.Enable(1'b1),
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.Q( wInstructionAvalableDelayed )
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.D( iBranchTaken ),
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);
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.Q( wBranchTaken_Delay1 )
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//----------------------------------------------
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assign rJumpNow = iBranchTaken && !iBranchNotTaken;
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//This sucks, should be improved
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wire JumpInstructinDetected;
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assign JumpInstructinDetected =
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(
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`INSTRUCTION_OPCODE == `JGEX || `INSTRUCTION_OPCODE == `JLEX ||
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`INSTRUCTION_OPCODE == `JGEY || `INSTRUCTION_OPCODE == `JLEY ||
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`INSTRUCTION_OPCODE == `JGEZ || `INSTRUCTION_OPCODE == `JLEZ ||
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`INSTRUCTION_OPCODE == `JEQX || `INSTRUCTION_OPCODE == `JNEX ||
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`INSTRUCTION_OPCODE == `JEQY || `INSTRUCTION_OPCODE == `JNEY ||
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`INSTRUCTION_OPCODE == `JEQZ || `INSTRUCTION_OPCODE == `JNEZ
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) ;
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) ;
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//Stall logic.
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assign wCurrentInstruction_BranchTaken = (iBranchTaken ) ? iInstruction2 : iInstruction1;
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//it basically tells IFU to stall on Branches.
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//The Stall begins when a Branch instruction
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//is detected, the Stall ends when EXE tells us it made
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//a branch taken or branch not taken decision
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wire wStall;
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assign wStall = JumpInstructinDetected && !iBranchTaken && !iBranchNotTaken;
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//Increment the IP everytime IDU tells us it has Latched the previous I we gave him,
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//except when we reached the last instruction in the flow, or we are in a Stall
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wire wIncrementInstructionPointer;
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assign wIncrementInstructionPointer = (wStall || wLastInstruction) ? 1'b0 : iDecodeUnitLatchedValues;
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assign oCurrentInstruction = (wBranchTaken_Delay1) ?
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wCurrentInstruction_Delay1 : wCurrentInstruction_BranchTaken;
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//-------------------------------------------------
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INCREMENT # (`ROM_ADDRESS_WIDTH) INC1
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wire wIP_AlternateValue;
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wire wIP_SetValueSelector;
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wire [`ROM_ADDRESS_WIDTH-1:0] wInstructionPointerAlternateValue;
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MUXFULLPARALELL_16bits_2SEL InstructionPointerSetValueMUX
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(
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.Sel( wIP_SetValueSelector ),
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.I1( iInitialCodeAddress ),
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.I2( iJumpIp ),
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.O1( wInstructionPointerAlternateValue )
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);
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reg rIpControl;
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MUXFULLPARALELL_1Bit_1SEL InstructionPointerControlMUX
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(
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(
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.Sel( rIpControl ),
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.Clock( Clock ),
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.I1( 1'b0 ),
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.Reset( Reset ),
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.I2( iBranchTaken ),
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.A( oIP2 ),
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.O1( wIP_SetValueSelector )
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.R( oIP2_Next )
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);
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);
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wire[`ROM_ADDRESS_WIDTH-1:0] wIPEntryPoint;
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assign wIPEntryPoint = (iBranchTaken) ? oIP2_Next : iInitialCodeAddress;
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UPCOUNTER_POSEDGE # (`ROM_ADDRESS_WIDTH) InstructionPointer
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UPCOUNTER_POSEDGE # (16) InstructionPointer
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(
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(
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.Clock(wIncrementInstructionPointer || wJumpNow_Delayed_1Cycle || iTrigger),
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.Clock( Clock ),
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.Reset(iTrigger || wJumpNow_Delayed_1Cycle ),
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.Reset(iTrigger | iBranchTaken),
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.Enable(1'b1),
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.Enable(wIncrementIP & ~iBranchTaken ),
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.Initial(wInstructionPointerAlternateValue),
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.Initial( wIPEntryPoint ),
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.Q(wInstructionPointer)
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.Q(oIP)
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);
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);
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reg [5:0] CurrentState, NextState;
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//------------------------------------------------
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always @(posedge Clock or posedge Reset)
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begin
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if (Reset)
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CurrentState <= `IFU_AFTER_RESET;
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else
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CurrentState <= NextState;
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end
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//------------------------------------------------
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always @ ( * )
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begin
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case ( CurrentState )
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//------------------------------------
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`IFU_AFTER_RESET:
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begin
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rEnable <= iTrigger;
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rIpControl <= `IP_SET_VALUE_INITIAL_ADDRESS;//0;
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oExecutionDone <= 0;
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if (iTrigger)
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NextState <= `IFU_INITIAL_STATE;
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else
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NextState <= `IFU_AFTER_RESET;
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end
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//------------------------------------
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`IFU_INITIAL_STATE:
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begin
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rEnable <= 1;
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rIpControl <= `IP_SET_VALUE_BRANCH_ADDRESS; //1;
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oExecutionDone <= 0;
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//We reached last instrcution (RETURN), and IDU latched the one before that
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if ( wLastInstruction && iDecodeUnitLatchedValues && !rJumpNow )
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NextState <= `IFU_WAIT_FOR_LAST_INSTRUCTION_LATCHED_BY_IDU;
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else
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NextState <= `IFU_INITIAL_STATE;
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end
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//------------------------------------
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//Here, we wait until IDU latches the last
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//instruction, ie. the RETURN instruction
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`IFU_WAIT_FOR_LAST_INSTRUCTION_LATCHED_BY_IDU:
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begin
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rEnable <= ~iDecodeUnitLatchedValues;
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rIpControl <= `IP_SET_VALUE_BRANCH_ADDRESS;
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oExecutionDone <= 0;
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if ( iDecodeUnitLatchedValues && !rJumpNow)//&& !iExeBusy && !iIDUBusy )
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NextState <= `IFU_DONE;
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else if ( rJumpNow )
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NextState <= `IFU_INITIAL_STATE;
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else
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NextState <= `IFU_WAIT_FOR_LAST_INSTRUCTION_LATCHED_BY_IDU;
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end
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//------------------------------------
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`IFU_DONE:
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begin
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rEnable <= 0;
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rIpControl <= `IP_SET_VALUE_BRANCH_ADDRESS;
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oExecutionDone <= !iExeBusy && !iIDUBusy;//1'b1;
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if (!iExeBusy && !iIDUBusy)
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NextState <= `IFU_AFTER_RESET;
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else
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NextState <= `IFU_DONE;
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end
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//------------------------------------
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default:
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begin
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rEnable <= 0;
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rIpControl <= `IP_SET_VALUE_INITIAL_ADDRESS; //0;
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oExecutionDone <= 0;
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NextState <= `IFU_AFTER_RESET;
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end
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//------------------------------------
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endcase
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end// always
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//------------------------------------------------------
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//
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//
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`ifdef DEBUG2
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always @ ( negedge iTrigger or negedge iDecodeUnitLatchedValues )
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begin
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$write("(%dns %d)",$time,oInstructionPointer);
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end
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always @ ( negedge wLastInstruction )
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begin
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$display(" %dns RETURN %d",$time,oMicroCodeReturnValue);
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end
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`endif
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`ifdef DEBUG2
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always @ (posedge wStall)
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begin
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$write("<S>");
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end
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`endif
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endmodule
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endmodule
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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