`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define TFU_AFTER_RESET 0
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`define TFU_AFTER_RESET 0
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`define TFU_IDLE 1
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`define TFU_IDLE 1
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`define TFU_REQUEST_VERTEX 2
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`define TFU_REQUEST_VERTEX 2
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`define TFU_WAIT_FOR_VERTEX 3
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`define TFU_WAIT_FOR_VERTEX 3
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`define TFU_REQUEST_NEXT_VERTEX_DIFFUSE 4
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`define TFU_REQUEST_NEXT_VERTEX_DIFFUSE 4
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`define TFU_REQUEST_DIFFUSE_COLOR 5
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`define TFU_REQUEST_DIFFUSE_COLOR 5
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`define TFU_WAIT_FOR_DIFFUSE_COLOR 6
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`define TFU_WAIT_FOR_DIFFUSE_COLOR 6
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`define TFU_SET_WBM_INITIAL_ADDRESS 7
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`define TFU_SET_WBM_INITIAL_ADDRESS 7
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`define TFU_CHECK_FOR_WBM_ADDRESS_SET 8
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`define TFU_CHECK_FOR_WBM_ADDRESS_SET 8
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`define TFU_SET_DIFFUSE_COLOR_ADDRESS 9
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`define TFU_SET_DIFFUSE_COLOR_ADDRESS 9
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`define TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE 10
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`define TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE 10
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`define TFU_INC_WRITE_ADDRESS_DIFFUSE 11
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`define TFU_INC_WRITE_ADDRESS_DIFFUSE 11
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`define TFU_DONE 12
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`define TFU_DONE 12
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*
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/*
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Warning: setting iTrigger while oBusy = 1 will reset the Up counters!
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Warning: setting iTrigger while oBusy = 1 will reset the Up counters!
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*/
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*/
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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module TriangleFetchUnit
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module TriangleFetchUnit
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iTrigger,
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input wire iTrigger,
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//output reg oBusy, //I am currently busy
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//output reg oBusy, //I am currently busy
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output reg oDone, //Done reading trinagle data
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output reg oDone, //Done reading trinagle data
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//Wires from GFSM
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//Wires from GFSM
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input wire iDataAvailable, //Data is ready
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input wire iDataAvailable, //Data is ready
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input wire[`WIDTH-1:0] iInitialAddress, //The initial address of the data
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input wire[`WIDTH-1:0] iInitialAddress, //The initial address of the data
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input wire iSetAddressOffset, //Set the iInitialAddress Now
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input wire iSetAddressOffset, //Set the iInitialAddress Now
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//Wires from Control Register
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//Wires from Control Register
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input wire iCR_TextureMappingEnabled, //Is the texture map fearure enable?
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input wire iCR_TextureMappingEnabled, //Is the texture map fearure enable?
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|
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//Wires to WBM
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//Wires to WBM
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output reg oTriggerWBM,
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output reg oTriggerWBM,
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output wire[`WIDTH-1:0] oAddressWBM,
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output wire[`WIDTH-1:0] oAddressWBM,
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output reg oSetAddressWBM,
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output reg oSetAddressWBM,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress,
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`ifdef DEBUG
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`ifdef DEBUG
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input wire[`MAX_CORES-1:0] iDebug_CoreID,
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input wire[`MAX_CORES-1:0] iDebug_CoreID,
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`endif
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`endif
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output reg oRAMWriteEnable
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output reg oRAMWriteEnable
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|
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);
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);
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assign oAddressWBM = iInitialAddress;///Must change or will always read first triangle in the list....
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assign oAddressWBM = iInitialAddress;///Must change or will always read first triangle in the list....
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reg [4:0] CurrentState,NextState;
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reg [4:0] CurrentState,NextState;
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reg IncWriteAddress,IncVertexCount;
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reg IncWriteAddress,IncVertexCount;
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wire [2:0] wVertexCount;
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wire [2:0] wVertexCount;
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//-----------------------------
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//-----------------------------
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UpCounter_3 TNF_VC1
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UpCounter_3 TNF_VC1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( iTrigger ),
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.Reset( iTrigger ),
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.Initial( 3'b0 ),
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.Initial( 3'b0 ),
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.Enable( IncVertexCount ),
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.Enable( IncVertexCount ),
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.Q( wVertexCount )
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.Q( wVertexCount )
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);
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);
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//-----------------------------
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//-----------------------------
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UpCounter_16E TNF_TFU_2
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UpCounter_16E TNF_TFU_2
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(
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(
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|
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( iTrigger ),
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.Reset( iTrigger ),
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.Initial( `CREG_V0 ),//iRAMWriteOffset ),
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.Initial( `CREG_V0 ),//iRAMWriteOffset ),
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.Enable( IncWriteAddress ),
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.Enable( IncWriteAddress ),
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.Q( oRAMWriteAddress )
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.Q( oRAMWriteAddress )
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|
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);
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);
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//------------------------------------------------
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//------------------------------------------------
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always @(posedge Clock or posedge Reset)
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always @(posedge Clock or posedge Reset)
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begin
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begin
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|
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if (Reset)
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if (Reset)
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CurrentState <= `TFU_AFTER_RESET;
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CurrentState <= `TFU_AFTER_RESET;
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else
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else
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CurrentState <= NextState;
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CurrentState <= NextState;
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end
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end
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//------------------------------------
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//------------------------------------
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always @( * )
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always @( * )
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begin
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begin
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case (CurrentState)
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case (CurrentState)
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//------------------------------------
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//------------------------------------
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`TFU_AFTER_RESET:
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`TFU_AFTER_RESET:
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begin
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begin
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|
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 0;
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// oBusy <= 0;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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NextState <= `TFU_IDLE;
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NextState <= `TFU_IDLE;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_IDLE:
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`TFU_IDLE:
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begin
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begin
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|
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 0;
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// oBusy <= 0;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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if ( iTrigger )
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if ( iTrigger )
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NextState <= `TFU_CHECK_FOR_WBM_ADDRESS_SET;
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NextState <= `TFU_CHECK_FOR_WBM_ADDRESS_SET;
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else
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else
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NextState <= `TFU_IDLE;
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NextState <= `TFU_IDLE;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_CHECK_FOR_WBM_ADDRESS_SET:
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`TFU_CHECK_FOR_WBM_ADDRESS_SET:
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begin
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begin
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 0;
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// oBusy <= 0;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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if ( iSetAddressOffset )
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if ( iSetAddressOffset )
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NextState <= `TFU_SET_WBM_INITIAL_ADDRESS;
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NextState <= `TFU_SET_WBM_INITIAL_ADDRESS;
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else
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else
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NextState <= `TFU_REQUEST_VERTEX;
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NextState <= `TFU_REQUEST_VERTEX;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_SET_WBM_INITIAL_ADDRESS:
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`TFU_SET_WBM_INITIAL_ADDRESS:
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begin
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begin
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`ifdef DEBUG
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`ifdef DEBUG
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$display("TFU: TFU_SET_WBM_INITIAL_ADDRESS");
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$display("TFU: TFU_SET_WBM_INITIAL_ADDRESS");
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`endif
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`endif
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 1; //*
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oSetAddressWBM <= 1; //*
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1; //*
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// oBusy <= 1; //*
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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NextState <= `TFU_REQUEST_VERTEX;
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NextState <= `TFU_REQUEST_VERTEX;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_REQUEST_VERTEX:
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`TFU_REQUEST_VERTEX:
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begin
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begin
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oTriggerWBM <= 1; //*
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oTriggerWBM <= 1; //*
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 1; //*
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IncVertexCount <= 1; //*
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 1; //*
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oRAMWriteEnable <= 1; //*
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//$display("TFU_REQUEST_VERTEX %d to wirte to %d\n",oAddressWBM,oRAMWriteAddress);
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//$display("TFU_REQUEST_VERTEX %d to wirte to %d\n",oAddressWBM,oRAMWriteAddress);
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NextState <= `TFU_WAIT_FOR_VERTEX;
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NextState <= `TFU_WAIT_FOR_VERTEX;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_WAIT_FOR_VERTEX:
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`TFU_WAIT_FOR_VERTEX:
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begin
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begin
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|
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oTriggerWBM <= 1;
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oTriggerWBM <= 1;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1; //*
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// oBusy <= 1; //*
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 1;
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oRAMWriteEnable <= 1;
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if ( iDataAvailable && iCR_TextureMappingEnabled == 1'b0)
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if ( iDataAvailable && iCR_TextureMappingEnabled == 1'b0)
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NextState <= `TFU_REQUEST_NEXT_VERTEX_DIFFUSE;
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NextState <= `TFU_REQUEST_NEXT_VERTEX_DIFFUSE;
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else if ( iDataAvailable && iCR_TextureMappingEnabled == 1'b1)
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else if ( iDataAvailable && iCR_TextureMappingEnabled == 1'b1)
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NextState <= `TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE;
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NextState <= `TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE;
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else
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else
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NextState <= `TFU_WAIT_FOR_VERTEX;
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NextState <= `TFU_WAIT_FOR_VERTEX;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_REQUEST_NEXT_VERTEX_DIFFUSE:
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`TFU_REQUEST_NEXT_VERTEX_DIFFUSE:
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begin
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begin
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 1; //*
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IncWriteAddress <= 1; //*
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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//if ( wVertexCount == 3)
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//if ( wVertexCount == 3)
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// NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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// NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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//else
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//else
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NextState <= `TFU_INC_WRITE_ADDRESS_DIFFUSE;
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NextState <= `TFU_INC_WRITE_ADDRESS_DIFFUSE;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE:
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`TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE:
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begin
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begin
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 1; //*
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IncWriteAddress <= 1; //*
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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//$display("TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE, count = %d",wVertexCount);
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//$display("TFU_REQUEST_NEXT_VERTEX_UV_DIFFUSE, count = %d",wVertexCount);
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if ( wVertexCount == 6)
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if ( wVertexCount == 6)
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NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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else
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else
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NextState <= `TFU_REQUEST_VERTEX;
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NextState <= `TFU_REQUEST_VERTEX;
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end
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end
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//------------------------------------
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//------------------------------------
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`TFU_INC_WRITE_ADDRESS_DIFFUSE:
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`TFU_INC_WRITE_ADDRESS_DIFFUSE:
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begin
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begin
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oTriggerWBM <= 0;
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oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 1; //*
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IncWriteAddress <= 1; //*
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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|
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// $display(":) TFU_REQUEST_NEXT_VERTEX_DIFFUSE, count = %d",wVertexCount);
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// $display(":) TFU_REQUEST_NEXT_VERTEX_DIFFUSE, count = %d",wVertexCount);
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if ( wVertexCount == 3)
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if ( wVertexCount == 3)
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NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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NextState <= `TFU_REQUEST_DIFFUSE_COLOR;
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else
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else
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NextState <= `TFU_REQUEST_VERTEX;
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NextState <= `TFU_REQUEST_VERTEX;
|
end
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end
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//------------------------------------
|
//------------------------------------
|
`TFU_REQUEST_DIFFUSE_COLOR:
|
`TFU_REQUEST_DIFFUSE_COLOR:
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begin
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begin
|
|
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// $display("TFU_REQUEST_DIFFUSE_COLOR: Writting to %d",oRAMWriteAddress);
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// $display("TFU_REQUEST_DIFFUSE_COLOR: Writting to %d",oRAMWriteAddress);
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oTriggerWBM <= 1;
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oTriggerWBM <= 1;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0;
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oDone <= 0;
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oRAMWriteEnable <= 1;
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oRAMWriteEnable <= 1;
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|
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NextState <= `TFU_WAIT_FOR_DIFFUSE_COLOR;
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NextState <= `TFU_WAIT_FOR_DIFFUSE_COLOR;
|
|
|
end
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end
|
//------------------------------------
|
//------------------------------------
|
`TFU_WAIT_FOR_DIFFUSE_COLOR:
|
`TFU_WAIT_FOR_DIFFUSE_COLOR:
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begin
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begin
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oTriggerWBM <= 1;
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oTriggerWBM <= 1;
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oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
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IncWriteAddress <= 0;
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IncWriteAddress <= 0;
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IncVertexCount <= 0;
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IncVertexCount <= 0;
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// oBusy <= 1;
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// oBusy <= 1;
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oDone <= 0; //*
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oDone <= 0; //*
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oRAMWriteEnable <= 1;
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oRAMWriteEnable <= 1;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TFU_DONE;
|
NextState <= `TFU_DONE;
|
else
|
else
|
NextState <= `TFU_WAIT_FOR_DIFFUSE_COLOR;
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NextState <= `TFU_WAIT_FOR_DIFFUSE_COLOR;
|
|
|
end
|
end
|
|
|
//------------------------------------
|
//------------------------------------
|
`TFU_DONE:
|
`TFU_DONE:
|
begin
|
begin
|
oTriggerWBM <= 0;
|
oTriggerWBM <= 0;
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oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
IncWriteAddress <= 0;
|
IncWriteAddress <= 0;
|
IncVertexCount <= 0;
|
IncVertexCount <= 0;
|
// oBusy <= 0; //*
|
// oBusy <= 0; //*
|
oDone <= 1; //*
|
oDone <= 1; //*
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
|
|
NextState <= `TFU_IDLE;
|
NextState <= `TFU_IDLE;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
default:
|
default:
|
begin
|
begin
|
oTriggerWBM <= 0;
|
oTriggerWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
IncWriteAddress <= 0;
|
IncWriteAddress <= 0;
|
IncVertexCount <= 0;
|
IncVertexCount <= 0;
|
// oBusy <= 0;
|
// oBusy <= 0;
|
oDone <= 0;
|
oDone <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
|
|
NextState <= `TFU_IDLE;
|
NextState <= `TFU_IDLE;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
endcase
|
endcase
|
|
|
end //always
|
end //always
|
endmodule
|
endmodule
|
|
|
