`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*
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/*
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The memory unit has all the memory related modules for THEIA.
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The memory unit has all the memory related modules for THEIA.
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There a 3 memories in the core:
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There a 3 memories in the core:
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DMEM: The data memory, it is a R/W dual channel RAM, stores the data locations.
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DMEM: The data memory, it is a R/W dual channel RAM, stores the data locations.
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IMEM: The instruction memory, R/W dual channel RAM, stores user shaders.
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IMEM: The instruction memory, R/W dual channel RAM, stores user shaders.
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IROM: RO instruction memory, stores default shaders and other internal code.
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IROM: RO instruction memory, stores default shaders and other internal code.
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I use two ROMs with the same data, so that simulates dual channel.
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I use two ROMs with the same data, so that simulates dual channel.
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This unit also has a Control register.
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This unit also has a Control register.
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*/
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*/
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`define USER_CODE_ENABLED 2
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`define USER_CODE_ENABLED 2
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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module MemoryUnit
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module MemoryUnit
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iFlipMemory,
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input wire iFlipMemory,
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|
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//Data bus for EXE Unit
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//Data bus for EXE Unit
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input wire iDataWriteEnable_EXE,
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input wire iDataWriteEnable_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_EXE,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_EXE,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_EXE,
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input wire[`DATA_ROW_WIDTH-1:0] iData_EXE,
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input wire[`DATA_ROW_WIDTH-1:0] iData_EXE,
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|
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//Data bus for IO Unit
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//Data bus for IO Unit
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input wire iDataWriteEnable_IO,
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input wire iDataWriteEnable_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData1_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_IO,
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output wire[`DATA_ROW_WIDTH-1:0] oData2_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_IO,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_IO,
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input wire[`DATA_ROW_WIDTH-1:0] iData_IO,
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input wire[`DATA_ROW_WIDTH-1:0] iData_IO,
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|
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//Instruction bus
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//Instruction bus
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input wire iInstructionWriteEnable,
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input wire iInstructionWriteEnable,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2,
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|
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//Control Register
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//Control Register
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input wire[15:0] iControlRegister,
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input wire[15:0] iControlRegister,
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output wire[15:0] oControlRegister
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output wire[15:0] oControlRegister
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);
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);
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|
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut1,wIMEM2_IMUX__DataOut2,
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut1,wIMEM2_IMUX__DataOut2,
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wIROM2_IMUX__DataOut1,wIROM2_IMUX__DataOut2;
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wIROM2_IMUX__DataOut1,wIROM2_IMUX__DataOut2;
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|
|
|
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wire wInstructionSelector;
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wire wInstructionSelector;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(Reset),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-1] ),
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.D( iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-1] ),
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.Q( wInstructionSelector )
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.Q( wInstructionSelector )
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);
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);
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|
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assign oInstruction1 = (wInstructionSelector == 1) ?
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assign oInstruction1 = (wInstructionSelector == 1) ?
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wIMEM2_IMUX__DataOut1 : wIROM2_IMUX__DataOut1;
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wIMEM2_IMUX__DataOut1 : wIROM2_IMUX__DataOut1;
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|
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assign oInstruction2 = (wInstructionSelector == 1) ?
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assign oInstruction2 = (wInstructionSelector == 1) ?
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wIMEM2_IMUX__DataOut2 : wIROM2_IMUX__DataOut2;
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wIMEM2_IMUX__DataOut2 : wIROM2_IMUX__DataOut2;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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/*
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/*
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Data memory.
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Data memory.
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*/
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*/
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`define SMEM_START_ADDR `DATA_ADDRESS_WIDTH'd32
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`define SMEM_START_ADDR `DATA_ADDRESS_WIDTH'd32
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`define RMEM_START_ADDR `DATA_ADDRESS_WIDTH'd64
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`define RMEM_START_ADDR `DATA_ADDRESS_WIDTH'd64
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`define OMEM_START_ADDR `DATA_ADDRESS_WIDTH'd128
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`define OMEM_START_ADDR `DATA_ADDRESS_WIDTH'd128
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|
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wire wDataWriteEnable_RMEM,wDataWriteEnable_SMEM,wDataWriteEnable_IMEM,wDataWriteEnable_OMEM;
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wire wDataWriteEnable_RMEM,wDataWriteEnable_SMEM,wDataWriteEnable_IMEM,wDataWriteEnable_OMEM;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataWriteAddress_RMEM,wDataWriteAddress_SMEM;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataWriteAddress_RMEM,wDataWriteAddress_SMEM;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_RMEM1,wDataReadAddress_RMEM2;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_RMEM1,wDataReadAddress_RMEM2;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_SMEM1,wDataReadAddress_SMEM2;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_SMEM1,wDataReadAddress_SMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wData_SMEM1,wData_SMEM2,wData_RMEM1,wData_RMEM2,wData_IMEM1,wData_IMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wData_SMEM1,wData_SMEM2,wData_RMEM1,wData_RMEM2,wData_IMEM1,wData_IMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2,wData_OMEM1,wData_OMEM2;
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wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2,wData_OMEM1,wData_OMEM2;
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/*
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/*
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always @ (posedge Clock)
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always @ (posedge Clock)
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begin
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begin
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if (wDataWriteEnable_OMEM)
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if (wDataWriteEnable_OMEM)
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$display("%dns OMEM Writting %h to Addr %d (%h)",
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$display("%dns OMEM Writting %h to Addr %d (%h)",
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$time,iData_EXE,iDataWriteAddress_EXE,iDataWriteAddress_EXE);
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$time,iData_EXE,iDataWriteAddress_EXE,iDataWriteAddress_EXE);
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|
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//if (iDataReadAddress1_IO >= 130)
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//if (iDataReadAddress1_IO >= 130)
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//$display("%dns OMEM Readin %h from %d (%h)",
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//$display("%dns OMEM Readin %h from %d (%h)",
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//$time,wData_OMEM1,iDataReadAddress1_IO,iDataReadAddress1_IO);
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//$time,wData_OMEM1,iDataReadAddress1_IO,iDataReadAddress1_IO);
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|
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end
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end
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*/
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*/
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assign wDataWriteEnable_OMEM =
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assign wDataWriteEnable_OMEM =
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(iDataWriteAddress_EXE >= `OMEM_START_ADDR )
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(iDataWriteAddress_EXE >= `OMEM_START_ADDR )
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? iDataWriteEnable_EXE : 1'b0;
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? iDataWriteEnable_EXE : 1'b0;
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|
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assign wDataWriteEnable_IMEM =
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assign wDataWriteEnable_IMEM =
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(iDataWriteAddress_IO < `SMEM_START_ADDR )
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(iDataWriteAddress_IO < `SMEM_START_ADDR )
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? iDataWriteEnable_IO : 1'b0;
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? iDataWriteEnable_IO : 1'b0;
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|
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assign wDataWriteEnable_SMEM =
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assign wDataWriteEnable_SMEM =
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(iDataWriteAddress_EXE >= `SMEM_START_ADDR && iDataWriteAddress_EXE < `RMEM_START_ADDR)
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(iDataWriteAddress_EXE >= `SMEM_START_ADDR && iDataWriteAddress_EXE < `RMEM_START_ADDR)
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? iDataWriteEnable_EXE : 1'b0;
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? iDataWriteEnable_EXE : 1'b0;
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|
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assign wDataWriteEnable_RMEM =
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assign wDataWriteEnable_RMEM =
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(iDataWriteAddress_EXE >= `RMEM_START_ADDR && iDataWriteAddress_EXE < `OMEM_START_ADDR)
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(iDataWriteAddress_EXE >= `RMEM_START_ADDR && iDataWriteAddress_EXE < `OMEM_START_ADDR)
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? iDataWriteEnable_EXE : 1'b0;
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? iDataWriteEnable_EXE : 1'b0;
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|
|
|
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assign wDataWriteAddress_RMEM = iDataWriteAddress_EXE;
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assign wDataWriteAddress_RMEM = iDataWriteAddress_EXE;
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assign wDataReadAddress_RMEM1 = iDataReadAddress1_EXE;
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assign wDataReadAddress_RMEM1 = iDataReadAddress1_EXE;
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assign wDataReadAddress_RMEM2 = iDataReadAddress2_EXE;
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assign wDataReadAddress_RMEM2 = iDataReadAddress2_EXE;
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assign wDataWriteAddress_SMEM = iDataWriteAddress_EXE;
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assign wDataWriteAddress_SMEM = iDataWriteAddress_EXE;
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assign wDataReadAddress_SMEM1 = iDataReadAddress1_EXE;
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assign wDataReadAddress_SMEM1 = iDataReadAddress1_EXE;
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assign wDataReadAddress_SMEM2 = iDataReadAddress2_EXE;
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assign wDataReadAddress_SMEM2 = iDataReadAddress2_EXE;
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|
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//assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ? wData_SMEM1 : wData_RMEM1;
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//assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ? wData_SMEM1 : wData_RMEM1;
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assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ?
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assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ?
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( ( iDataReadAddress1_EXE < `SMEM_START_ADDR ) ? wData_IMEM1 : wData_SMEM1 )
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( ( iDataReadAddress1_EXE < `SMEM_START_ADDR ) ? wData_IMEM1 : wData_SMEM1 )
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: wData_RMEM1;
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: wData_RMEM1;
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|
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//assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ? wData_SMEM2 : wData_RMEM2;
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//assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ? wData_SMEM2 : wData_RMEM2;
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assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ?
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assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ?
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( ( iDataReadAddress2_EXE < `SMEM_START_ADDR ) ? wData_IMEM2 : wData_SMEM2 )
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( ( iDataReadAddress2_EXE < `SMEM_START_ADDR ) ? wData_IMEM2 : wData_SMEM2 )
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: wData_RMEM2;
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: wData_RMEM2;
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|
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|
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assign oData1_IO = ( iDataReadAddress1_IO < `OMEM_START_ADDR ) ? wIOData_SMEM1 : wData_OMEM1;
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assign oData1_IO = ( iDataReadAddress1_IO < `OMEM_START_ADDR ) ? wIOData_SMEM1 : wData_OMEM1;
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assign oData2_IO = ( iDataReadAddress2_IO < `OMEM_START_ADDR ) ? wIOData_SMEM2 : wData_OMEM2;
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assign oData2_IO = ( iDataReadAddress2_IO < `OMEM_START_ADDR ) ? wIOData_SMEM2 : wData_OMEM2;
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|
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//assign oData1_IO = wIOData_SMEM1;
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//assign oData1_IO = wIOData_SMEM1;
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//assign oData2_IO = wIOData_SMEM2;
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//assign oData2_IO = wIOData_SMEM2;
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|
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//Output registers written by EXE, Read by IO
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//Output registers written by EXE, Read by IO
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RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) OMEM
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RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) OMEM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( wDataWriteEnable_OMEM ),
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.iWriteEnable( wDataWriteEnable_OMEM ),
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.iReadAddress0( iDataReadAddress1_IO ),
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.iReadAddress0( iDataReadAddress1_IO ),
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.iReadAddress1( iDataReadAddress2_IO ),
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.iReadAddress1( iDataReadAddress2_IO ),
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.iWriteAddress( iDataWriteAddress_EXE ),
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.iWriteAddress( iDataWriteAddress_EXE ),
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.iDataIn( iData_EXE ),
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.iDataIn( iData_EXE ),
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.oDataOut0( wData_OMEM1 ),
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.oDataOut0( wData_OMEM1 ),
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.oDataOut1( wData_OMEM2 )
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.oDataOut1( wData_OMEM2 )
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);
|
);
|
|
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//Input Registers, Written by IO, Read by EXE
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//Input Registers, Written by IO, Read by EXE
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RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,42) IMEM
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RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,42) IMEM
|
(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( wDataWriteEnable_IMEM ),
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.iWriteEnable( wDataWriteEnable_IMEM ),
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.iReadAddress0( iDataReadAddress1_EXE ),
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.iReadAddress0( iDataReadAddress1_EXE ),
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.iReadAddress1( iDataReadAddress2_EXE ),
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.iReadAddress1( iDataReadAddress2_EXE ),
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.iWriteAddress( iDataWriteAddress_IO ),
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.iWriteAddress( iDataWriteAddress_IO ),
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.iDataIn( iData_IO ),
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.iDataIn( iData_IO ),
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.oDataOut0( wData_IMEM1 ),
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.oDataOut0( wData_IMEM1 ),
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.oDataOut1( wData_IMEM2 )
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.oDataOut1( wData_IMEM2 )
|
);
|
);
|
|
|
//Swap registers, while IO writes/write values, EXE reads/write values
|
//Swap registers, while IO writes/write values, EXE reads/write values
|
//the pointers get filped in the next iteration
|
//the pointers get filped in the next iteration
|
SWAP_MEM # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) SMEM
|
SWAP_MEM # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) SMEM
|
(
|
(
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.Clock( Clock ),
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.Clock( Clock ),
|
.iSelect( wFlipSelect ),
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.iSelect( wFlipSelect ),
|
|
|
.iWriteEnableA( wDataWriteEnable_SMEM ),
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.iWriteEnableA( wDataWriteEnable_SMEM ),
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.iReadAddressA0( wDataReadAddress_SMEM1 ),
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.iReadAddressA0( wDataReadAddress_SMEM1 ),
|
.iReadAddressA1( wDataReadAddress_SMEM2 ),
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.iReadAddressA1( wDataReadAddress_SMEM2 ),
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.iWriteAddressA( wDataWriteAddress_SMEM ),
|
.iWriteAddressA( wDataWriteAddress_SMEM ),
|
.iDataInA( iData_EXE ),
|
.iDataInA( iData_EXE ),
|
.oDataOutA0( wData_SMEM1 ),
|
.oDataOutA0( wData_SMEM1 ),
|
.oDataOutA1( wData_SMEM2 ),
|
.oDataOutA1( wData_SMEM2 ),
|
|
|
.iWriteEnableB( iDataWriteEnable_IO ),
|
.iWriteEnableB( iDataWriteEnable_IO ),
|
.iReadAddressB0( iDataReadAddress1_IO ),
|
.iReadAddressB0( iDataReadAddress1_IO ),
|
.iReadAddressB1( iDataReadAddress2_IO ),
|
.iReadAddressB1( iDataReadAddress2_IO ),
|
.iWriteAddressB( iDataWriteAddress_IO ),
|
.iWriteAddressB( iDataWriteAddress_IO ),
|
.iDataInB( iData_IO ),
|
.iDataInB( iData_IO ),
|
.oDataOutB0( wIOData_SMEM1 ),
|
.oDataOutB0( wIOData_SMEM1 ),
|
.oDataOutB1( wIOData_SMEM2 )
|
.oDataOutB1( wIOData_SMEM2 )
|
|
|
);
|
);
|
|
|
//General purpose registers, EXE can R/W, IO can not see these sections
|
//General purpose registers, EXE can R/W, IO can not see these sections
|
//of the memory
|
//of the memory
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,256) RMEM
|
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,256) RMEM
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( wDataWriteEnable_RMEM ),
|
.iWriteEnable( wDataWriteEnable_RMEM ),
|
.iReadAddress0( wDataReadAddress_RMEM1 ),
|
.iReadAddress0( wDataReadAddress_RMEM1 ),
|
.iReadAddress1( wDataReadAddress_RMEM2 ),
|
.iReadAddress1( wDataReadAddress_RMEM2 ),
|
.iWriteAddress( wDataWriteAddress_RMEM ),
|
.iWriteAddress( wDataWriteAddress_RMEM ),
|
.iDataIn( iData_EXE ),
|
.iDataIn( iData_EXE ),
|
.oDataOut0( wData_RMEM1 ),
|
.oDataOut0( wData_RMEM1 ),
|
.oDataOut1( wData_RMEM2 )
|
.oDataOut1( wData_RMEM2 )
|
);
|
);
|
|
|
wire wFlipSelect;
|
wire wFlipSelect;
|
UPCOUNTER_POSEDGE # (1) UPC1
|
UPCOUNTER_POSEDGE # (1) UPC1
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.Initial(1'b0),
|
.Initial(1'b0),
|
.Enable(iFlipMemory),
|
.Enable(iFlipMemory),
|
.Q(wFlipSelect)
|
.Q(wFlipSelect)
|
);
|
);
|
|
|
|
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
/*
|
/*
|
Instruction memory.
|
Instruction memory.
|
*/
|
*/
|
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH,512) INST_MEM
|
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH,512) INST_MEM
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.iWriteEnable( iInstructionWriteEnable ),
|
.iWriteEnable( iInstructionWriteEnable ),
|
.iReadAddress0( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress0( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress1( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iReadAddress1( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.iWriteAddress( iInstructionWriteAddress ),
|
.iWriteAddress( iInstructionWriteAddress ),
|
.iDataIn( iInstruction ),
|
.iDataIn( iInstruction ),
|
.oDataOut0( wIMEM2_IMUX__DataOut1 ),
|
.oDataOut0( wIMEM2_IMUX__DataOut1 ),
|
.oDataOut1( wIMEM2_IMUX__DataOut2 )
|
.oDataOut1( wIMEM2_IMUX__DataOut2 )
|
|
|
);
|
);
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
/*
|
/*
|
Default code stored in ROM.
|
Default code stored in ROM.
|
*/
|
*/
|
wire [`INSTRUCTION_WIDTH-1:0] wRomDelay1,wRomDelay2;
|
wire [`INSTRUCTION_WIDTH-1:0] wRomDelay1,wRomDelay2;
|
//In real world ROM will take at least 1 clock cycle,
|
//In real world ROM will take at least 1 clock cycle,
|
//since ROMs are not syhtethizable, I won't hurt to put
|
//since ROMs are not syhtethizable, I won't hurt to put
|
//this delay
|
//this delay
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDA
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDA
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset(Reset),
|
.Reset(Reset),
|
.Enable(1'b1),
|
.Enable(1'b1),
|
.D(wRomDelay1),
|
.D(wRomDelay1),
|
.Q(wIROM2_IMUX__DataOut1 )
|
.Q(wIROM2_IMUX__DataOut1 )
|
);
|
);
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDB
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDB
|
(
|
(
|
.Clock(Clock),
|
.Clock(Clock),
|
.Reset(Reset),
|
.Reset(Reset),
|
.Enable(1'b1),
|
.Enable(1'b1),
|
.D(wRomDelay2),
|
.D(wRomDelay2),
|
.Q(wIROM2_IMUX__DataOut2 )
|
.Q(wIROM2_IMUX__DataOut2 )
|
);
|
);
|
|
|
//The reason I put two ROMs is because I need to read 2 different Instruction
|
//The reason I put two ROMs is because I need to read 2 different Instruction
|
//addresses at the same time (branch-taken and branch-not-taken) and not sure
|
//addresses at the same time (branch-taken and branch-not-taken) and not sure
|
//hpw to write dual read channel ROM this way...
|
//hpw to write dual read channel ROM this way...
|
|
|
ROM IROM
|
ROM IROM
|
(
|
(
|
.Address( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.Address( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.I( wRomDelay1 )
|
.I( wRomDelay1 )
|
);
|
);
|
|
|
ROM IROM2
|
ROM IROM2
|
(
|
(
|
.Address( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.Address( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
.I( wRomDelay2 )
|
.I( wRomDelay2 )
|
);
|
);
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
ControlRegister CR
|
ControlRegister CR
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iControlRegister( iControlRegister ),
|
.iControlRegister( iControlRegister ),
|
.oControlRegister( oControlRegister )
|
.oControlRegister( oControlRegister )
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
