`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*******************************************************************************
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/*******************************************************************************
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Module Description:
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Module Description:
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WIP
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WIP
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*******************************************************************************/
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*******************************************************************************/
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`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
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`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define SELECT_INST_MEM 3'b00
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`define SELECT_INST_MEM 3'b00
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`define SELECT_SCENE_MEM 3'b01
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`define SELECT_SCENE_MEM 3'b01
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`define SELECT_GEO_MEM 3'b10
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`define SELECT_GEO_MEM 3'b10
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`define HOST_IDLE 0
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`define HOST_IDLE 0
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WAIT_INSTRUCTION 2
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`define HOST_WAIT_INSTRUCTION 2
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`define HOST_WRITE_SCENE_PARAMS 3
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`define HOST_WRITE_SCENE_PARAMS 3
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`define HOST_WAIT_SCENE_PARAMS 4
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`define HOST_WAIT_SCENE_PARAMS 4
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`define HOST_PREPARE_CORE_CONFIG 5
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`define HOST_PREPARE_CORE_CONFIG 5
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`define HOST_UNICAST_CORE_CONFIG 6
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`define HOST_UNICAST_CORE_CONFIG 6
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`define HOST_WAIT_CORE_CONFIG 7
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`define HOST_WAIT_CORE_CONFIG 7
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`define HOST_PREPARE_NEXT_CORE_CONFIG 8
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`define HOST_PREPARE_NEXT_CORE_CONFIG 8
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`define HOST_WAIT_DATA_READ_CONFIRMATION 10
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`define HOST_WAIT_DATA_READ_CONFIRMATION 10
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`define HOST_BROADCAST_NEXT_VERTEX 11
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`define HOST_BROADCAST_NEXT_VERTEX 11
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`define HOST_WAIT_FOR_VERTEX 12
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`define HOST_WAIT_FOR_VERTEX 12
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`define HOST_INITIAL_SCENE_PARAMS_STAGE 13
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`define HOST_INITIAL_SCENE_PARAMS_STAGE 13
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`define HOST_PREPARE_FOR_GEO_REQUESTS 14
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`define HOST_PREPARE_FOR_GEO_REQUESTS 14
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`define HOST_ACK_GEO_REQUEST 15
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`define HOST_ACK_GEO_REQUEST 15
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`define HOST_GET_PRIMITIVE_COUNT 16
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`define HOST_GET_PRIMITIVE_COUNT 16
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`define HOST_LAST_PRIMITIVE_REACHED 17
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`define HOST_LAST_PRIMITIVE_REACHED 17
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`define HOST_GPU_EXECUTION_DONE 18
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`define HOST_GPU_EXECUTION_DONE 18
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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module Module_Host
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module Module_Host
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire iHostDataReadConfirmed,
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input wire iHostDataReadConfirmed,
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input wire [`WB_WIDTH-1:0] iMemorySize,
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input wire [`WB_WIDTH-1:0] iMemorySize,
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input wire [`WB_WIDTH-1:0] iPrimitiveCount,
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input wire [`WB_WIDTH-1:0] iPrimitiveCount,
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//To Memory
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//To Memory
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output wire [`WB_WIDTH-1:0] oReadAddress,
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output wire [`WB_WIDTH-1:0] oReadAddress,
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input wire [`WB_WIDTH-1:0] iReadData,
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input wire [`WB_WIDTH-1:0] iReadData,
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input wire iGPUCommitedResults,
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input wire iGPUCommitedResults,
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//To Hub/Switch
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//To Hub/Switch
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output wire [`MAX_CORES-1:0] oCoreSelectMask,
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output wire [`MAX_CORES-1:0] oCoreSelectMask,
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output reg [2:0] oMemSelect,
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output reg [2:0] oMemSelect,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output reg[1:0] TGA_O,
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output reg[1:0] TGA_O,
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output reg[`MAX_CORES-1:0] RENDREN_O,
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output reg[`MAX_CORES-1:0] RENDREN_O,
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output wire CYC_O,
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output wire CYC_O,
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output wire STB_O,
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output wire STB_O,
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output reg MST_O,
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output reg MST_O,
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output wire WE_O,
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output wire WE_O,
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input wire GRDY_I, //This means all the cores are done rading the primitive we send
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input wire GRDY_I, //This means all the cores are done rading the primitive we send
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output reg GACK_O, //We set this to ACK that the cored read the primitive
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output reg GACK_O, //We set this to ACK that the cored read the primitive
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output wire STDONE_O,
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output wire STDONE_O,
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output reg oHostDataAvailable,
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output reg oHostDataAvailable,
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input wire iGPUDone,
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input wire iGPUDone,
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`ifndef NO_DISPLAY_STATS
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`ifndef NO_DISPLAY_STATS
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input wire [`WIDTH-1:0] iDebugWidth,
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input wire [`WIDTH-1:0] iDebugWidth,
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`endif
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`endif
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input wire ACK_I
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input wire ACK_I
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);
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);
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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wire wLastPrimitive;
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wire wLastPrimitive;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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assign STDONE_O = wLastPrimitive;
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assign STDONE_O = wLastPrimitive;
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wire wWBMDone;
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wire wWBMDone;
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reg rWBMEnable,rWBMReset,rCoreBroadCast;
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reg rWBMEnable,rWBMReset,rCoreBroadCast;
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reg [`WB_WIDTH-1:0] rInitiaReadAddr;
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reg [`WB_WIDTH-1:0] rInitiaReadAddr;
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wire [`MAX_CORES-1:0] wCoreSelect;
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wire [`MAX_CORES-1:0] wCoreSelect;
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wire wLastValidReadAddress;
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wire wLastValidReadAddress;
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wire [`WB_WIDTH-1:0] wWriteAddress;
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wire [`WB_WIDTH-1:0] wWriteAddress;
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wire [`WIDTH-1:0] wVertexCount;
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wire [`WIDTH-1:0] wVertexCount;
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reg [`WB_WIDTH-1:0] rInitialWriteAddress;
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reg [`WB_WIDTH-1:0] rInitialWriteAddress;
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reg rSetWriteAddr;
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reg rSetWriteAddr;
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reg rIncCoreSelect,rResetVertexCount;
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reg rIncCoreSelect,rResetVertexCount;
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//--------------------------------------------------------
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//--------------------------------------------------------
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assign WE_O = MST_O;
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assign WE_O = MST_O;
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assign oCoreSelectMask =
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assign oCoreSelectMask =
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(rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
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(rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
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assign wLastValidReadAddress =
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assign wLastValidReadAddress =
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(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
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(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
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wire wLastParameter;
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wire wLastParameter;
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assign wLastParameter = (oReadAddress >= 32'h12) ? 1'b1 : 1'b0;
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assign wLastParameter = (oReadAddress >= 32'h12) ? 1'b1 : 1'b0;
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//--------------------------------------------------------
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//--------------------------------------------------------
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UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
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UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rSetWriteAddr ),
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.Reset( Reset | rSetWriteAddr ),
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.Enable( iEnable & wWBMDone ),
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.Enable( iEnable & wWBMDone ),
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.Initial( rInitialWriteAddress ),
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.Initial( rInitialWriteAddress ),
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.Q( wWriteAddress )
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.Q( wWriteAddress )
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);
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);
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UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
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UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rResetVertexCount ),
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.Reset( Reset | rResetVertexCount ),
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.Enable( iEnable & wWBMDone ),
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.Enable( iEnable & wWBMDone ),
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.Initial( `WIDTH'b1 ),
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.Initial( `WIDTH'b1 ),
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.Q( wVertexCount )
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.Q( wVertexCount )
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);
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);
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//--------------------------------------------------------
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//--------------------------------------------------------
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Initial( `MAX_CORES'b1 ),
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.Initial( `MAX_CORES'b1 ),
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.Enable( rIncCoreSelect ),
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.Enable( rIncCoreSelect ),
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.O( wCoreSelect )
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.O( wCoreSelect )
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);
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);
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//--------------------------------------------------------
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//--------------------------------------------------------
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wire wShortCycle;
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wire wShortCycle;
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//For instruction we send 2 packets per cycle
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//For instruction we send 2 packets per cycle
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//for the other we send 3 packets per cycle
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//for the other we send 3 packets per cycle
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assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
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assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
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WBMaster WBM
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WBMaster WBM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rWBMReset ),
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.Reset( Reset | rWBMReset ),
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.iEnable( rWBMEnable ),
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.iEnable( rWBMEnable ),
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.iInitialReadAddr( rInitiaReadAddr ),
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.iInitialReadAddr( rInitiaReadAddr ),
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.iWriteAddr( wWriteAddress ),
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.iWriteAddr( wWriteAddress ),
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.oReadAddress( oReadAddress ),
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.oReadAddress( oReadAddress ),
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.iReadData( iReadData ),
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.iReadData( iReadData ),
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.iShortFlow( wShortCycle ),
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.iShortFlow( wShortCycle ),
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.STB_O( STB_O ),
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.STB_O( STB_O ),
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.ACK_I( ACK_I ),
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.ACK_I( ACK_I ),
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.CYC_O( CYC_O ),
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.CYC_O( CYC_O ),
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.DAT_O( DAT_O ),
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.DAT_O( DAT_O ),
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.ADR_O( ADR_O ),
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.ADR_O( ADR_O ),
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.oDone( wWBMDone )
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.oDone( wWBMDone )
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);
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);
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//--------------------------------------------------------
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//--------------------------------------------------------
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// Current State Logic //
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// Current State Logic //
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reg [7:0] rHostCurrentState,rHostNextState;
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reg [7:0] rHostCurrentState,rHostNextState;
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always @(posedge Clock or posedge Reset)
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always @(posedge Clock or posedge Reset)
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begin
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begin
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if( Reset!=1 )
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if( Reset!=1 )
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rHostCurrentState <= rHostNextState;
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rHostCurrentState <= rHostNextState;
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else
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else
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rHostCurrentState <= `HOST_IDLE;
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rHostCurrentState <= `HOST_IDLE;
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end
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end
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//--------------------------------------------------------
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//--------------------------------------------------------
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reg [63:0] i;
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reg [63:0] i;
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reg [63:0] RenderedPixels;
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reg [63:0] RenderedPixels;
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wire wLastVertexInFrame;
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wire wLastVertexInFrame;
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assign wLastVertexInFrame =
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assign wLastVertexInFrame =
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
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// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
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reg [31:0] StartTime;
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reg [31:0] StartTime;
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// Host Finite State Machine //
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// Host Finite State Machine //
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always @( * )
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always @( * )
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begin
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begin
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case (rHostCurrentState)
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case (rHostCurrentState)
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//----------------------------------------
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//----------------------------------------
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//Wait for reset sequence to complete,
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//Wait for reset sequence to complete,
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//Or until we are enabled
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//Or until we are enabled
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`HOST_IDLE:
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`HOST_IDLE:
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begin
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begin
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RenderedPixels <= 0;
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RenderedPixels <= 0;
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rWBMEnable <= 0;
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rWBMEnable <= 0;
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rWBMReset <= 0;
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rWBMReset <= 0;
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oMemSelect <= 0;
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oMemSelect <= 0;
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TGA_O <= 0;
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TGA_O <= 0;
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MST_O <= 0;
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MST_O <= 0;
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rInitialWriteAddress <= 0;
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rInitialWriteAddress <= 0;
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rSetWriteAddr <= 0;
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rSetWriteAddr <= 0;
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rCoreBroadCast <= 0;
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rCoreBroadCast <= 0;
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rIncCoreSelect <= 0;
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rIncCoreSelect <= 0;
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RENDREN_O <= 0;
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RENDREN_O <= 0;
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rResetVertexCount <= 0;
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rResetVertexCount <= 0;
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GACK_O <= 0;
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GACK_O <= 0;
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//STDONE_O <= 0;
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//STDONE_O <= 0;
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oHostDataAvailable <= 0;
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oHostDataAvailable <= 0;
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if ( ~Reset & iEnable )
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if ( ~Reset & iEnable )
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rHostNextState <= `HOST_WRITE_INSTRUCTION;
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rHostNextState <= `HOST_WRITE_INSTRUCTION;
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else
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else
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rHostNextState <= `HOST_IDLE;
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rHostNextState <= `HOST_IDLE;
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end
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end
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//----------------------------------------
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//----------------------------------------
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//Broadcast the instructions to all the cores
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//Broadcast the instructions to all the cores
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`HOST_WRITE_INSTRUCTION:
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`HOST_WRITE_INSTRUCTION:
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begin
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begin
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StartTime <= $time;
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StartTime <= $time;
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rWBMEnable <= 1; //Enable Wish bone master
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rWBMEnable <= 1; //Enable Wish bone master
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rWBMReset <= 0; //No need to reset since we just came from reset
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rWBMReset <= 0; //No need to reset since we just came from reset
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oMemSelect <= `SELECT_INST_MEM; //Start by sending the instructions
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oMemSelect <= `SELECT_INST_MEM; //Start by sending the instructions
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TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
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TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O <= 1;
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MST_O <= 1;
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rInitialWriteAddress <= 0;
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rInitialWriteAddress <= 0;
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rSetWriteAddr <= 0;
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rSetWriteAddr <= 0;
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rCoreBroadCast <= 1;
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rCoreBroadCast <= 1;
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rIncCoreSelect <= 0;
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rIncCoreSelect <= 0;
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RENDREN_O <= 0;
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RENDREN_O <= 0;
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rResetVertexCount <= 0;
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rResetVertexCount <= 0;
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GACK_O <= 0;
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GACK_O <= 0;
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//STDONE_O <= 0;
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//STDONE_O <= 0;
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oHostDataAvailable <= 0;
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oHostDataAvailable <= 0;
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rHostNextState <= `HOST_WAIT_INSTRUCTION;
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rHostNextState <= `HOST_WAIT_INSTRUCTION;
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end
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end
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//----------------------------------------
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//----------------------------------------
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`HOST_WAIT_INSTRUCTION:
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`HOST_WAIT_INSTRUCTION:
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begin
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begin
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rWBMEnable <= ~wWBMDone;
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rWBMEnable <= ~wWBMDone;
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rInitiaReadAddr <= 0;
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rInitiaReadAddr <= 0;
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rWBMReset <= 0;
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rWBMReset <= 0;
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oMemSelect <= `SELECT_INST_MEM;
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oMemSelect <= `SELECT_INST_MEM;
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TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
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TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O <= 1;
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MST_O <= 1;
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rInitialWriteAddress <= 0;
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rInitialWriteAddress <= 0;
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rSetWriteAddr <= 0;
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rSetWriteAddr <= 0;
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rCoreBroadCast <= 1;
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rCoreBroadCast <= 1;
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rIncCoreSelect <= 0;
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rIncCoreSelect <= 0;
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RENDREN_O <= 0;
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RENDREN_O <= 0;
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rResetVertexCount <= 0;
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rResetVertexCount <= 0;
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GACK_O <= 0;
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GACK_O <= 0;
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//STDONE_O <= 0;
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//STDONE_O <= 0;
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oHostDataAvailable <= 0;
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oHostDataAvailable <= 0;
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if ( wWBMDone && ~wLastValidReadAddress )
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if ( wWBMDone && ~wLastValidReadAddress )
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rHostNextState <= `HOST_WRITE_INSTRUCTION;
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rHostNextState <= `HOST_WRITE_INSTRUCTION;
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else if (wWBMDone && wLastValidReadAddress )
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else if (wWBMDone && wLastValidReadAddress )
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rHostNextState <= `HOST_INITIAL_SCENE_PARAMS_STAGE;
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rHostNextState <= `HOST_INITIAL_SCENE_PARAMS_STAGE;
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else
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else
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rHostNextState <= `HOST_WAIT_INSTRUCTION;
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rHostNextState <= `HOST_WAIT_INSTRUCTION;
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end
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end
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//----------------------------------------
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//----------------------------------------
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/*
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/*
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Make sure to read-pointer points to the
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Make sure to read-pointer points to the
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first memory address at te params memory
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first memory address at te params memory
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*/
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*/
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`HOST_INITIAL_SCENE_PARAMS_STAGE:
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`HOST_INITIAL_SCENE_PARAMS_STAGE:
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begin
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begin
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rWBMEnable <= 0;
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rWBMEnable <= 0;
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rWBMReset <= 1;
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rWBMReset <= 1;
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oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
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oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
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TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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MST_O <= 1; //Keep master signal in 1 for now
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MST_O <= 1; //Keep master signal in 1 for now
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rInitialWriteAddress <= 0; //We start writing from address zero now
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rInitialWriteAddress <= 0; //We start writing from address zero now
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rSetWriteAddr <= 1;
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rSetWriteAddr <= 1;
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rCoreBroadCast <= 1; //Set to zero to unicast, starting from core 0
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rCoreBroadCast <= 1; //Set to zero to unicast, starting from core 0
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rIncCoreSelect <= 0; //Set to unicast to the next core
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rIncCoreSelect <= 0; //Set to unicast to the next core
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RENDREN_O <= 0;
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RENDREN_O <= 0;
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rResetVertexCount <= 0;
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rResetVertexCount <= 0;
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GACK_O <= 0;
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GACK_O <= 0;
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//STDONE_O <= 0;
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//STDONE_O <= 0;
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oHostDataAvailable <= 0;
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oHostDataAvailable <= 0;
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rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
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rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
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end
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end
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//----------------------------------------
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//----------------------------------------
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//Broadcast the instructions to all the cores
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//Broadcast the instructions to all the cores
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`HOST_WRITE_SCENE_PARAMS:
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`HOST_WRITE_SCENE_PARAMS:
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begin
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begin
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rWBMEnable <= 1;
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rWBMEnable <= 1;
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rInitiaReadAddr <= 0;
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rInitiaReadAddr <= 0;
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rWBMReset <= 0;
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rWBMReset <= 0;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1;
|
MST_O <= 1;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_WAIT_SCENE_PARAMS:
|
`HOST_WAIT_SCENE_PARAMS:
|
begin
|
begin
|
rWBMEnable <= ~wWBMDone;
|
rWBMEnable <= ~wWBMDone;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1;
|
MST_O <= 1;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
if ( wWBMDone && ~wLastParameter )
|
if ( wWBMDone && ~wLastParameter )
|
rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
|
rHostNextState <= `HOST_WRITE_SCENE_PARAMS;
|
else if (wWBMDone && wLastParameter )
|
else if (wWBMDone && wLastParameter )
|
rHostNextState <= `HOST_PREPARE_CORE_CONFIG;
|
rHostNextState <= `HOST_PREPARE_CORE_CONFIG;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
rHostNextState <= `HOST_WAIT_SCENE_PARAMS;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
/*
|
/*
|
This state set the read Write Address pointer to
|
This state set the read Write Address pointer to
|
CREG_PIXEL_2D_INITIAL_POSITION memory position,
|
CREG_PIXEL_2D_INITIAL_POSITION memory position,
|
also selects the scene MEM from the external MEM
|
also selects the scene MEM from the external MEM
|
MUX.
|
MUX.
|
*/
|
*/
|
`HOST_PREPARE_CORE_CONFIG:
|
`HOST_PREPARE_CORE_CONFIG:
|
begin
|
begin
|
rWBMEnable <= 0;
|
rWBMEnable <= 0;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
|
oMemSelect <= `SELECT_SCENE_MEM; //We are reading from the scene memory
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
|
MST_O <= 1; //Keep master signal in 1 for now
|
MST_O <= 1; //Keep master signal in 1 for now
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rCoreBroadCast <= 0; //Set to zero to unicast, starting from core 0
|
rCoreBroadCast <= 0; //Set to zero to unicast, starting from core 0
|
rIncCoreSelect <= 0; //Set to unicast to the next core
|
rIncCoreSelect <= 0; //Set to unicast to the next core
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
|
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
end
|
end
|
|
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_UNICAST_CORE_CONFIG:
|
`HOST_UNICAST_CORE_CONFIG:
|
begin
|
begin
|
rWBMEnable <= 1;
|
rWBMEnable <= 1;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1;
|
MST_O <= 1;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 0;
|
rCoreBroadCast <= 0;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_WAIT_CORE_CONFIG:
|
`HOST_WAIT_CORE_CONFIG:
|
begin
|
begin
|
rWBMEnable <= ~wWBMDone;
|
rWBMEnable <= ~wWBMDone;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
oMemSelect <= `SELECT_SCENE_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1;
|
MST_O <= 1;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 0;
|
rCoreBroadCast <= 0;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
|
|
if (wWBMDone && !(oReadAddress % 2))
|
if (wWBMDone && !(oReadAddress % 2))
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
else if (wWBMDone && (oReadAddress % 2) )
|
else if (wWBMDone && (oReadAddress % 2) )
|
rHostNextState <= `HOST_PREPARE_NEXT_CORE_CONFIG;
|
rHostNextState <= `HOST_PREPARE_NEXT_CORE_CONFIG;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
rHostNextState <= `HOST_WAIT_CORE_CONFIG;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
/*
|
/*
|
Reset the WBM to tell it to start reading
|
Reset the WBM to tell it to start reading
|
from address 0 at the Geometry memory.
|
from address 0 at the Geometry memory.
|
*/
|
*/
|
`HOST_PREPARE_NEXT_CORE_CONFIG:
|
`HOST_PREPARE_NEXT_CORE_CONFIG:
|
begin
|
begin
|
rWBMEnable <= 0;
|
rWBMEnable <= 0;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_GEO_MEM;
|
oMemSelect <= `SELECT_GEO_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 0; //The master signal goes to zero until request
|
MST_O <= 0; //The master signal goes to zero until request
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
|
rInitialWriteAddress <= `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rCoreBroadCast <= 0;
|
rCoreBroadCast <= 0;
|
rIncCoreSelect <= 1; //Moving to configure the next core now
|
rIncCoreSelect <= 1; //Moving to configure the next core now
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
if (wCoreSelect[`MAX_CORES-1] == 1)
|
if (wCoreSelect[`MAX_CORES-1] == 1)
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
else
|
else
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
rHostNextState <= `HOST_UNICAST_CORE_CONFIG;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
/*
|
/*
|
Prepare the write address for the next primitive.
|
Prepare the write address for the next primitive.
|
|
|
*/
|
*/
|
`HOST_PREPARE_FOR_GEO_REQUESTS:
|
`HOST_PREPARE_FOR_GEO_REQUESTS:
|
begin
|
begin
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rInitiaReadAddr <= 32'hA; //Start reading from addr 0 @ GEO MEM
|
rInitiaReadAddr <= 32'hA; //Start reading from addr 0 @ GEO MEM
|
rWBMReset <= 1; //Tell WBM to start reading from the addr bellow
|
rWBMReset <= 1; //Tell WBM to start reading from the addr bellow
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
MST_O <= 0; //The master signal goes to zero until request
|
MST_O <= 0; //The master signal goes to zero until request
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 1;
|
rResetVertexCount <= 1;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
if (iGPUDone)
|
if (iGPUDone)
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
else
|
else
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_ACK_GEO_REQUEST:
|
`HOST_ACK_GEO_REQUEST:
|
begin
|
begin
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rInitiaReadAddr <= 0; //Ignored
|
rInitiaReadAddr <= 0; //Ignored
|
rWBMReset <= 0; //Ignored
|
rWBMReset <= 0; //Ignored
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
MST_O <= 0; //The master signal goes to zero until request
|
MST_O <= 0; //The master signal goes to zero until request
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 1;
|
GACK_O <= 1;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
|
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
/*
|
/*
|
Send the next primitive to the HUB/SWITCH unit
|
Send the next primitive to the HUB/SWITCH unit
|
so that it gets broadcasted to all the cores
|
so that it gets broadcasted to all the cores
|
*/
|
*/
|
`HOST_BROADCAST_NEXT_VERTEX:
|
`HOST_BROADCAST_NEXT_VERTEX:
|
begin
|
begin
|
rWBMEnable <= 1; //Start the Transmition
|
rWBMEnable <= 1; //Start the Transmition
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_GEO_MEM;
|
oMemSelect <= `SELECT_GEO_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1; //Start the Transmition
|
MST_O <= 1; //Start the Transmition
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_WAIT_FOR_VERTEX:
|
`HOST_WAIT_FOR_VERTEX:
|
begin
|
begin
|
rWBMEnable <= ~wWBMDone; //Disable WBM when it is donw
|
rWBMEnable <= ~wWBMDone; //Disable WBM when it is donw
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_GEO_MEM;
|
oMemSelect <= `SELECT_GEO_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1; //Start the Transmition
|
MST_O <= 1; //Start the Transmition
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
|
|
if (wWBMDone & ~wLastVertexInFrame )
|
if (wWBMDone & ~wLastVertexInFrame )
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
rHostNextState <= `HOST_BROADCAST_NEXT_VERTEX;
|
else if (wWBMDone & wLastVertexInFrame )
|
else if (wWBMDone & wLastVertexInFrame )
|
rHostNextState <= `HOST_GET_PRIMITIVE_COUNT;
|
rHostNextState <= `HOST_GET_PRIMITIVE_COUNT;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
|
|
|
|
/*
|
/*
|
if (wWBMDone)
|
if (wWBMDone)
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
rHostNextState <= `HOST_WAIT_FOR_VERTEX;
|
*/
|
*/
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_GET_PRIMITIVE_COUNT:
|
`HOST_GET_PRIMITIVE_COUNT:
|
begin
|
begin
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= `SELECT_GEO_MEM;
|
oMemSelect <= `SELECT_GEO_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1; //Start the Transmition
|
MST_O <= 1; //Start the Transmition
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;//1;
|
oHostDataAvailable <= 0;//1;
|
|
|
if (wVertexCount >= iPrimitiveCount)
|
if (wVertexCount >= iPrimitiveCount)
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
/*
|
/*
|
we wait until all the cores are ready for the next primitive,
|
we wait until all the cores are ready for the next primitive,
|
this happens when the iHostDataReadConfirmed signal
|
this happens when the iHostDataReadConfirmed signal
|
gets asserted
|
gets asserted
|
*/
|
*/
|
`HOST_WAIT_DATA_READ_CONFIRMATION:
|
`HOST_WAIT_DATA_READ_CONFIRMATION:
|
begin
|
begin
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rWBMEnable <= 0; //Do not enable until we are resquested
|
rInitiaReadAddr <= 0; //Ignored
|
rInitiaReadAddr <= 0; //Ignored
|
rWBMReset <= 0; //Continue from previous read address
|
rWBMReset <= 0; //Continue from previous read address
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
oMemSelect <= `SELECT_GEO_MEM; //Use external GEO mem for reading
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
MST_O <= 0; //The master signal goes to zero until request
|
MST_O <= 0; //The master signal goes to zero until request
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rInitialWriteAddress <= `CREG_V0; //Write starting from this location on the cores
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rSetWriteAddr <= 1; //Set to use the initial write address bellow
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rCoreBroadCast <= 1; //From now on we only broadcast
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
rIncCoreSelect <= 0; //Ignored during broadcasts
|
RENDREN_O <= `SELECT_ALL_CORES;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 1;
|
oHostDataAvailable <= 1;
|
|
|
if ( iHostDataReadConfirmed )
|
if ( iHostDataReadConfirmed )
|
rHostNextState <= `HOST_ACK_GEO_REQUEST;
|
rHostNextState <= `HOST_ACK_GEO_REQUEST;
|
else
|
else
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
rHostNextState <= `HOST_WAIT_DATA_READ_CONFIRMATION;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_LAST_PRIMITIVE_REACHED:
|
`HOST_LAST_PRIMITIVE_REACHED:
|
begin
|
begin
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
rWBMEnable <= 0; //Disable WBM when it is donw
|
rInitiaReadAddr <= 32'hA; //Reset primitive counter to first primitive
|
rInitiaReadAddr <= 32'hA; //Reset primitive counter to first primitive
|
rWBMReset <= 1; //Reset primitive counter to first primitive
|
rWBMReset <= 1; //Reset primitive counter to first primitive
|
oMemSelect <= `SELECT_GEO_MEM;
|
oMemSelect <= `SELECT_GEO_MEM;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
MST_O <= 1;
|
MST_O <= 1;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 1;
|
rCoreBroadCast <= 1;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
RENDREN_O <= `SELECT_ALL_CORES;
|
rResetVertexCount <= 0; //Reset the vertex count to zero
|
rResetVertexCount <= 0; //Reset the vertex count to zero
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 1;
|
//STDONE_O <= 1;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
|
|
|
|
if (iGPUCommitedResults)
|
if (iGPUCommitedResults)
|
begin
|
begin
|
|
|
`ifndef NO_DISPLAY_STATS
|
`ifndef NO_DISPLAY_STATS
|
for (i = 0; i < `MAX_CORES; i = i + 1)
|
for (i = 0; i < `MAX_CORES; i = i + 1)
|
begin
|
begin
|
$write(".");
|
$write(".");
|
end
|
end
|
RenderedPixels = RenderedPixels + `MAX_CORES;
|
RenderedPixels = RenderedPixels + `MAX_CORES;
|
if ( RenderedPixels % iDebugWidth == 0)
|
if ( RenderedPixels % iDebugWidth == 0)
|
$write("]%d\n[",RenderedPixels / iDebugWidth);
|
$write("]%d\n[",RenderedPixels / iDebugWidth);
|
`endif
|
`endif
|
|
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
|
end
|
end
|
else
|
else
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_GPU_EXECUTION_DONE:
|
`HOST_GPU_EXECUTION_DONE:
|
begin
|
begin
|
$display("THEIA Execution done in %dns\n",$time-StartTime);
|
$display("THEIA Execution done in %dns\n",$time-StartTime);
|
rWBMEnable <= 0;
|
rWBMEnable <= 0;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= 0;
|
oMemSelect <= 0;
|
TGA_O <= 0;
|
TGA_O <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 0;
|
rCoreBroadCast <= 0;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
rHostNextState <= `HOST_GPU_EXECUTION_DONE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
default:
|
default:
|
begin
|
begin
|
|
|
rWBMEnable <= 0;
|
rWBMEnable <= 0;
|
rInitiaReadAddr <= 0;
|
rInitiaReadAddr <= 0;
|
rWBMReset <= 0;
|
rWBMReset <= 0;
|
oMemSelect <= 0;
|
oMemSelect <= 0;
|
TGA_O <= 0;
|
TGA_O <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
rInitialWriteAddress <= 0;
|
rInitialWriteAddress <= 0;
|
rSetWriteAddr <= 0;
|
rSetWriteAddr <= 0;
|
rCoreBroadCast <= 0;
|
rCoreBroadCast <= 0;
|
rIncCoreSelect <= 0;
|
rIncCoreSelect <= 0;
|
RENDREN_O <= 0;
|
RENDREN_O <= 0;
|
rResetVertexCount <= 0;
|
rResetVertexCount <= 0;
|
GACK_O <= 0;
|
GACK_O <= 0;
|
//STDONE_O <= 0;
|
//STDONE_O <= 0;
|
oHostDataAvailable <= 0;
|
oHostDataAvailable <= 0;
|
|
|
rHostNextState <= `HOST_IDLE;
|
rHostNextState <= `HOST_IDLE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
