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/**********************************************************************************
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Theaia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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/*******************************************************************************
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Module Description:
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This module defines constants that are going to be used
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all over the code. By now you have may noticed that all
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constants are pre-compilation define directives. This is
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for simulation perfomance reasons mainly.
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*******************************************************************************/
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`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
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`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
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`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
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`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
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//---------------------------------------------------------------------------------
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//Verilog provides a `default_nettype none compiler directive. When
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//this directive is set, implicit data types are disabled, which will make any
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//undeclared signal name a syntax error.This is very usefull to avoid annoying
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//automatic 1 bit long wire declaration where you don't want them to be!
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`default_nettype none
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//The clock cycle
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`define CLOCK_CYCLE 5
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`define CLOCK_PERIOD 10
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//---------------------------------------------------------------------------------
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//Defines the Scale. This very important because it sets the fixed point precision.
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//The Scale defines the number bits that are used as the decimal part of the number.
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//The code has been written in such a way that allows you to change the value of the
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//Scale, so that it is possible to experiment with different scenarios. SCALE can be
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//no smaller that 1 and no bigger that WIDTH.
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`define SCALE 17
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//The next section defines the length of the registers, buses and other structures,
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//do not change this valued unless you really know what you are doing (seriously!)
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`define WIDTH 32
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`define WB_WIDTH 32 //width of wish-bone buses
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`define LONG_WIDTH 64
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`define WB_SIMPLE_READ_CYCLE 0
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`define WB_SIMPLE_WRITE_CYCLE 1
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//---------------------------------------------------------------------------------
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//Next are the constants that define the size of the instructions.
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//instructions are formed like this:
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// Tupe I:
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// Operand (of size INSTRUCTION_OP_LENGTH )
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// DestinationAddr (of size DATA_ADDRESS_WIDTH )
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// SourceAddrr1 (of size DATA_ADDRESS_WIDTH )
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// SourceAddrr2 (of size DATA_ADDRESS_WIDTH )
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//Type II:
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// Operand (of size INSTRUCTION_OP_LENGTH )
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// DestinationAddr (of size DATA_ADDRESS_WIDTH )
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// InmeadiateValue (of size WIDTH = DATA_ADDRESS_WIDTH * 2 )
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//
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//You can play around with the size of instuctions, but keep
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//in mind that Bits 3 and 4 of the Operand have a special meaning
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//that is used for the jump familiy of instructions (see Documentation).
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//Also the MSB of Operand is used by the decoder to distinguish
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//between Type I and Type II instructions.
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`define INSTRUCTION_WIDTH 64
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`define INSTRUCTION_OP_LENGTH 16
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`define INSTRUCTION_IMM_BITPOS 54
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`define INSTRUCTION_IMM_BIT 6 //don't change this!
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//Defines the Lenght of Memory blocks
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`define DATA_ROW_WIDTH 96
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`define DATA_ADDRESS_WIDTH 16
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`define ROM_ADDRESS_WIDTH 16
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`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
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//---------------------------------------------------------------------------------
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//The next section defines the code memory entry point for the various code routines
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//Please keep this syntax ENTRYPOINT_ADDR_* because the perl script that
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//parses the user code expects this pattern in order to read in the tokens
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//Internal Entry points (default ROM Address)
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`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
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`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd44
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`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd47
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`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd69
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`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd157
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`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd232
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`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd248
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`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd190
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`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd55
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//User Entry points (default ROM Address)
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`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd276
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`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd278
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`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37
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//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
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//parses the user code expects this pattern in order to read in the tokens
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//Internal subroutines
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`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
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`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
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`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
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`define ENTRYPOINT_INDEX_AABBIU `ROM_ADDRESS_WIDTH'h8003
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`define ENTRYPOINT_INDEX_BIU `ROM_ADDRESS_WIDTH'h8004
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`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
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`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
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`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
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`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
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//User defined subroutines
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`define ENTRYPOINT_INDEX_USERCONSTANTS `ROM_ADDRESS_WIDTH'h8009
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`define ENTRYPOINT_INDEX_PIXELSHADER `ROM_ADDRESS_WIDTH'h800A
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`define ENTRYPOINT_INDEX_MAIN `ROM_ADDRESS_WIDTH'h800B
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`define USER_AABBIU_UCODE_ADDRESS `ROM_ADDRESS_WIDTH'b1000000000000000
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//---------------------------------------------------------------------------------
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//This handy little macro allows me to print stuff either to STDOUT or a file.
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//Notice that the compilation vairable DUMP_CODE must be set if you want to print
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//to a file. In XILINX right click 'Simulate Beahvioral Model' -> Properties and
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//under 'Specify `define macro name and value' type 'DEBUG=1|DUMP_CODE=1|DEBUG_CORE=<core you want to dump>'
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`ifdef DUMP_CODE
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`define LOGME $fwrite(ucode_file,
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`else
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`define LOGME $write(
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`endif
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//---------------------------------------------------------------------------------
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`define TRUE 32'h1
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`define FALSE 32'h0
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`define RT_TRUE 48'b1
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`define RT_FALSE 48'b0
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//---------------------------------------------------------------------------------
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`define GENERAL_PURPOSE_REG_ADDR_MASK `DATA_ADDRESS_WIDTH'h1F
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`define VOID `DATA_ADDRESS_WIDTH'd0 //0000
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//** Control register bits **//
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`define CR_EN_LIGHTS 0
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`define CR_EN_TEXTURE 1
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`define CR_USER_AABBIU 2
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/** Swapping registers **/
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//** Configuration Registers **//
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`define CREG_LIGHT_INFO `DATA_ADDRESS_WIDTH'd0
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`define CREG_CAMERA_POSITION `DATA_ADDRESS_WIDTH'd1
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`define CREG_PROJECTION_WINDOW_MIN `DATA_ADDRESS_WIDTH'd2
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`define CREG_PROJECTION_WINDOW_MAX `DATA_ADDRESS_WIDTH'd3
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`define CREG_RESOLUTION `DATA_ADDRESS_WIDTH'd4
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`define CREG_TEXTURE_SIZE `DATA_ADDRESS_WIDTH'd5
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`define CREG_PIXEL_2D_INITIAL_POSITION `DATA_ADDRESS_WIDTH'd6
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`define CREG_PIXEL_2D_FINAL_POSITION `DATA_ADDRESS_WIDTH'd7
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`define CREG_FIRST_LIGTH `DATA_ADDRESS_WIDTH'd8
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`define CREG_FIRST_LIGTH_DIFFUSE `DATA_ADDRESS_WIDTH'd8
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//OK, so from address 0x06 to 0x0F is where the lights are,watch out values are harcoded
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//for now!! (look in ROM.v for hardcoded values!!!)
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//Don't change the order of the registers. CREG_V* and CREG_UV* registers
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//need to be in that specific order for the triangle fetcher to work
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//correctly!
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`define CREG_AABBMIN `DATA_ADDRESS_WIDTH'd42
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`define CREG_AABBMAX `DATA_ADDRESS_WIDTH'd43
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`define CREG_V0 `DATA_ADDRESS_WIDTH'd44
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`define CREG_UV0 `DATA_ADDRESS_WIDTH'd45
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`define CREG_V1 `DATA_ADDRESS_WIDTH'd46
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`define CREG_UV1 `DATA_ADDRESS_WIDTH'd47
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`define CREG_V2 `DATA_ADDRESS_WIDTH'd48
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`define CREG_UV2 `DATA_ADDRESS_WIDTH'd49
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`define CREG_TRI_DIFFUSE `DATA_ADDRESS_WIDTH'd50
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`define CREG_TEX_COLOR1 `DATA_ADDRESS_WIDTH'd53
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`define CREG_TEX_COLOR2 `DATA_ADDRESS_WIDTH'd54
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`define CREG_TEX_COLOR3 `DATA_ADDRESS_WIDTH'd55
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`define CREG_TEX_COLOR4 `DATA_ADDRESS_WIDTH'd56
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`define CREG_TEX_COLOR5 `DATA_ADDRESS_WIDTH'd57
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`define CREG_TEX_COLOR6 `DATA_ADDRESS_WIDTH'd58
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`define CREG_TEX_COLOR7 `DATA_ADDRESS_WIDTH'd59
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/** Non-Swapping registers **/
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// ** User Registers **//
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//General Purpose registers, the user may put what ever he/she
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//wants in here...
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`define C1 `DATA_ADDRESS_WIDTH'd64
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`define C2 `DATA_ADDRESS_WIDTH'd65
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`define C3 `DATA_ADDRESS_WIDTH'd66
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`define C4 `DATA_ADDRESS_WIDTH'd67
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`define C5 `DATA_ADDRESS_WIDTH'd68
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`define C6 `DATA_ADDRESS_WIDTH'd69
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`define C7 `DATA_ADDRESS_WIDTH'd70
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`define R1 `DATA_ADDRESS_WIDTH'd71
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`define R2 `DATA_ADDRESS_WIDTH'd72
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`define R3 `DATA_ADDRESS_WIDTH'd73
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`define R4 `DATA_ADDRESS_WIDTH'd74
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`define R5 `DATA_ADDRESS_WIDTH'd75
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`define R6 `DATA_ADDRESS_WIDTH'd76
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`define R7 `DATA_ADDRESS_WIDTH'd77
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`define R8 `DATA_ADDRESS_WIDTH'd78
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`define R9 `DATA_ADDRESS_WIDTH'd79
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`define R10 `DATA_ADDRESS_WIDTH'd80
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`define R11 `DATA_ADDRESS_WIDTH'd81
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`define R12 `DATA_ADDRESS_WIDTH'd82
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//** Internal Registers **//
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`define CREG_PROJECTION_WINDOW_SCALE `DATA_ADDRESS_WIDTH'd83
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`define CREG_UNORMALIZED_DIRECTION `DATA_ADDRESS_WIDTH'd84
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`define CREG_RAY_DIRECTION `DATA_ADDRESS_WIDTH'd85
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`define CREG_E1_LAST `DATA_ADDRESS_WIDTH'd86
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`define CREG_E2_LAST `DATA_ADDRESS_WIDTH'd87
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`define CREG_T `DATA_ADDRESS_WIDTH'd88
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`define CREG_P `DATA_ADDRESS_WIDTH'd89
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`define CREG_Q `DATA_ADDRESS_WIDTH'd90
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`define CREG_UV0_LAST `DATA_ADDRESS_WIDTH'd91
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`define CREG_UV1_LAST `DATA_ADDRESS_WIDTH'd92
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`define CREG_UV2_LAST `DATA_ADDRESS_WIDTH'd93
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`define CREG_TRI_DIFFUSE_LAST `DATA_ADDRESS_WIDTH'd94
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`define CREG_LAST_t `DATA_ADDRESS_WIDTH'd95
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`define CREG_LAST_u `DATA_ADDRESS_WIDTH'd96
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`define CREG_LAST_v `DATA_ADDRESS_WIDTH'd97
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`define CREG_COLOR_ACC `DATA_ADDRESS_WIDTH'd98
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`define CREG_t `DATA_ADDRESS_WIDTH'd99
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`define CREG_E1 `DATA_ADDRESS_WIDTH'd100
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`define CREG_E2 `DATA_ADDRESS_WIDTH'd101
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`define CREG_DELTA `DATA_ADDRESS_WIDTH'd102
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`define CREG_u `DATA_ADDRESS_WIDTH'd103
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`define CREG_v `DATA_ADDRESS_WIDTH'd104
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`define CREG_H1 `DATA_ADDRESS_WIDTH'd105
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`define CREG_H2 `DATA_ADDRESS_WIDTH'd106
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`define CREG_H3 `DATA_ADDRESS_WIDTH'd107
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`define CREG_PIXEL_PITCH `DATA_ADDRESS_WIDTH'd108
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`define CREG_LAST_COL `DATA_ADDRESS_WIDTH'd109 //the last valid column, simply CREG_RESOLUTIONX - 1
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`define CREG_TEXTURE_COLOR `DATA_ADDRESS_WIDTH'd110
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`define CREG_PIXEL_2D_POSITION `DATA_ADDRESS_WIDTH'd111
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`define CREG_TEXWEIGHT1 `DATA_ADDRESS_WIDTH'd112
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`define CREG_TEXWEIGHT2 `DATA_ADDRESS_WIDTH'd113
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`define CREG_TEXWEIGHT3 `DATA_ADDRESS_WIDTH'd114
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`define CREG_TEXWEIGHT4 `DATA_ADDRESS_WIDTH'd115
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`define CREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd116
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`define CREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd117
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`define R99 `DATA_ADDRESS_WIDTH'd118
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`define CREG_ZERO `DATA_ADDRESS_WIDTH'd119
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`define CREG_CURRENT_OUTPUT_PIXEL `DATA_ADDRESS_WIDTH'd120
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`define CREG_3 `DATA_ADDRESS_WIDTH'd121
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`define CREG_012 `DATA_ADDRESS_WIDTH'd122
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//** Ouput registers **//
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`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd128
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`define OREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd129
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`define OREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd130
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`define OREG_ADDR_O `DATA_ADDRESS_WIDTH'd131
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//-------------------------------------------------------------
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//*** Instruction Set ***
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//The order of the instructions is important here!. Don't change
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//it unless you know what you are doing. For example all the 'SET'
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//family of instructions have the MSB bit in 1. This means that
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//if you add an instruction and the MSB=1, this instruction will treated
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//as type II (see manual) meaning the second 32bit argument is expected to be
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//an inmediate value instead of a register address!
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//Another example is that in the JUMP family Bits 3 and 4 have a special
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//meaning: b4b3 = 01 => X jump type, b4b3 = 10 => Y jump type, finally
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//b4b3 = 11 means Z jump type.
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//All this is just to tell you: Don't play with these values!
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// *** Type I Instructions (OP DST REG1 REG2) ***
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`define NOP `INSTRUCTION_OP_LENGTH'b0_000000 //0
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`define ADD `INSTRUCTION_OP_LENGTH'b0_000001 //1
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`define SUB `INSTRUCTION_OP_LENGTH'b0_000010 //2
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`define DIV `INSTRUCTION_OP_LENGTH'b0_000011 //3
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`define MUL `INSTRUCTION_OP_LENGTH'b0_000100 //4
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`define MAG `INSTRUCTION_OP_LENGTH'b0_000101 //5
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`define COPY `INSTRUCTION_OP_LENGTH'b0_000111 //7
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`define JGX `INSTRUCTION_OP_LENGTH'b0_001_000 //8
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`define JLX `INSTRUCTION_OP_LENGTH'b0_001_001 //9
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`define JEQX `INSTRUCTION_OP_LENGTH'b0_001_010 //10 - A
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`define JNEX `INSTRUCTION_OP_LENGTH'b0_001_011 //11 - B
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`define JGEX `INSTRUCTION_OP_LENGTH'b0_001_100 //12 - C
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`define JLEX `INSTRUCTION_OP_LENGTH'b0_001_101 //13 - D
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`define INC `INSTRUCTION_OP_LENGTH'b0_001_110 //14 - E
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`define ZERO `INSTRUCTION_OP_LENGTH'b0_001_111 //15 - F
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`define JGY `INSTRUCTION_OP_LENGTH'b0_010_000 //16
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`define JLY `INSTRUCTION_OP_LENGTH'b0_010_001 //17
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`define JEQY `INSTRUCTION_OP_LENGTH'b0_010_010 //18
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`define JNEY `INSTRUCTION_OP_LENGTH'b0_010_011 //19
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`define JGEY `INSTRUCTION_OP_LENGTH'b0_010_100 //20
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`define JLEY `INSTRUCTION_OP_LENGTH'b0_010_101 //21
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`define CROSS `INSTRUCTION_OP_LENGTH'b0_010_110 //22
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`define DOT `INSTRUCTION_OP_LENGTH'b0_010_111 //23
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`define JGZ `INSTRUCTION_OP_LENGTH'b0_011_000 //24
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`define JLZ `INSTRUCTION_OP_LENGTH'b0_011_001 //25
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`define JEQZ `INSTRUCTION_OP_LENGTH'b0_011_010 //26
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`define JNEZ `INSTRUCTION_OP_LENGTH'b0_011_011 //27
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`define JGEZ `INSTRUCTION_OP_LENGTH'b0_011_100 //28
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`define JLEZ `INSTRUCTION_OP_LENGTH'b0_011_101 //29
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//The next instruction is for simulation debug only
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//not to be synthetized! Pretty much behaves the same
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//as a NOP, only that prints the register value to
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//a log file called 'Registers.log'
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`ifdef DEBUG
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`define DEBUG_PRINT `INSTRUCTION_OP_LENGTH'b0_011_110 //30
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`endif
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`define MULP `INSTRUCTION_OP_LENGTH'b0_011_111 //31 R1.z = S1.x * S1.y
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`define MOD `INSTRUCTION_OP_LENGTH'b0_100_000 //32 R = MODULO( S1,S2 )
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`define FRAC `INSTRUCTION_OP_LENGTH'b0_100_001 //33 R =FractionalPart( S1 )
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`define INTP `INSTRUCTION_OP_LENGTH'b0_100_010 //34 R =IntergerPart( S1 )
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`define NEG `INSTRUCTION_OP_LENGTH'b0_100_011 //35 R = -S1
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`define DEC `INSTRUCTION_OP_LENGTH'b0_100_100 //36 R = S1--
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`define XCHANGEX `INSTRUCTION_OP_LENGTH'b0_100_101 // R.x = S2.x, R.y = S1.y, R.z = S1.z
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`define XCHANGEY `INSTRUCTION_OP_LENGTH'b0_100_110 // R.x = S1.x, R.y = S2.y, R.z = S1.z
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`define XCHANGEZ `INSTRUCTION_OP_LENGTH'b0_100_111 // R.x = S1.x, R.y = S1.y, R.z = S2.z
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`define IMUL `INSTRUCTION_OP_LENGTH'b0_101_000 // R = INTEGER( S1 * S2 )
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`define UNSCALE `INSTRUCTION_OP_LENGTH'b0_101_001 // R = S1 >> SCALE
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`define RESCALE `INSTRUCTION_OP_LENGTH'b0_101_010 // R = S1 << SCALE
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`define INCX `INSTRUCTION_OP_LENGTH'b0_101_011 // R.X = S1.X + 1
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`define INCY `INSTRUCTION_OP_LENGTH'b0_101_100 // R.Y = S1.Y + 1
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`define INCZ `INSTRUCTION_OP_LENGTH'b0_101_101 // R.Z = S1.Z + 1
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`define OMWRITE `INSTRUCTION_OP_LENGTH'b0_101_111 //47 IO write to O memory
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`define TMREAD `INSTRUCTION_OP_LENGTH'b0_110_000 //48 IO read from T memory
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`define LEA `INSTRUCTION_OP_LENGTH'b0_110_001 //49 Load effective address
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//*** Type II Instructions (OP DST REG1 IMM) ***
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`define RETURN `INSTRUCTION_OP_LENGTH'b1_000000 //64 0x40
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`define SETX `INSTRUCTION_OP_LENGTH'b1_000001 //65 0x41
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`define SETY `INSTRUCTION_OP_LENGTH'b1_000010 //66
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`define SETZ `INSTRUCTION_OP_LENGTH'b1_000011 //67
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`define SWIZZLE3D `INSTRUCTION_OP_LENGTH'b1_000100 //68
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`define JMP `INSTRUCTION_OP_LENGTH'b1_011000 //56
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`define CALL `INSTRUCTION_OP_LENGTH'b1_011001 //57
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`define RET `INSTRUCTION_OP_LENGTH'b1_011010 //58
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//-------------------------------------------------------------
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//All the posible values for the SWIZZLE3D instruction are defined next
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`define SWIZZLE_XXX 32'd0
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`define SWIZZLE_YYY 32'd1
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`define SWIZZLE_ZZZ 32'd2
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`define SWIZZLE_XYY 32'd3
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`define SWIZZLE_XXY 32'd4
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`define SWIZZLE_XZZ 32'd5
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`define SWIZZLE_XXZ 32'd6
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`define SWIZZLE_YXX 32'd7
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`define SWIZZLE_YYX 32'd8
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`define SWIZZLE_YZZ 32'd9
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`define SWIZZLE_YYZ 32'd10
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`define SWIZZLE_ZXX 32'd11
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`define SWIZZLE_ZZX 32'd12
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`define SWIZZLE_ZYY 32'd13
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`define SWIZZLE_ZZY 32'd14
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`define SWIZZLE_XZX 32'd15
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`define SWIZZLE_XYX 32'd16
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`define SWIZZLE_YXY 32'd17
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`define SWIZZLE_YZY 32'd18
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`define SWIZZLE_ZXZ 32'd19
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`define SWIZZLE_ZYZ 32'd20
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`define SWIZZLE_YXZ 32'd21
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