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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/*******************************************************************************
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/*******************************************************************************
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Module Description:
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Module Description:
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This is the Main test bench of the GPU. It simulates the behavior of
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This is the Main test bench of the GPU. It simulates the behavior of
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an external control unit or CPU that sends configuration information into DUT.
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an external control unit or CPU that sends configuration information into DUT.
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It also implements a second processs that simulates a Wishbone slave that sends
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It also implements a second processs that simulates a Wishbone slave that sends
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data from an external memory. These blocks are just behavioral CTE and therefore
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data from an external memory. These blocks are just behavioral CTE and therefore
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are not meant to be synthethized.
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are not meant to be synthethized.
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*******************************************************************************/
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*******************************************************************************/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define CONFIGURATION_PHASE 0
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`define RESOLUTION_WIDTH (rSceneParameters[13] >> `SCALE)
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`define CTE_INITIAL_STATE 0
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`define RESOLUTION_HEIGHT (rSceneParameters[14] >> `SCALE)
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`define CTE_IDLE 1
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`define CTE_START_EU_CONFIGURATION_SEQUENCE 2
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`define CTE_SEND_CONFIGURATION_PACKET 3
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`define CTE_ACK_CONFIGURATION_PACKET 8
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`define CTE_SEND_LIGHT_PACKET 13
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`define CTE_ACK_LIGTH_PACKET 14
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`define CTE_SEND_RAY_I_TASK 15
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`define CTE_WAIT_FOR_TASK_ACK 16
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`define WAIT_FOR_TASK_COMPLETE 17
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`define CTE_PREPARE_NEW_TASK 18
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`define CTE_RENDER_DONE 19
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`define CTE_READ_COLOR_DATA 20
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`define CTE_GRANT_BUS_WRITE_PERMISION 21
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`define CTE_ACK_GRANT_BUS_PERMISION 22
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`define CTE_ACK_READ_COLOR_DATA 23
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`define CTE_SEND_TEXTURE_DIMENSIONS 24
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`define CTE_ACK_TEXTURE_DIMENSIONS 25
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`define RESOLUTION_WIDTH (rSceneParameters[12] >> `SCALE)
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`define RESOLUTION_HEIGHT (rSceneParameters[13] >> `SCALE)
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`define RAYI_TASK 1
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`define DELTA_ROW (32'h1 << `SCALE)
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`define DELTA_ROW (32'h1 << `SCALE)
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`define DELTA_COL (32'h1 << `SCALE)
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`define DELTA_COL (32'h1 << `SCALE)
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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`define SELECT_ALL_CORES `MAX_CORES'b1111;
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`define MAX_WIDTH 200
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`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
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module TestBench_Theia;
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module TestBench_Theia;
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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//**WARNING: Declare all of your varaibles at the begining
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//**WARNING: Declare all of your varaibles at the begining
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//of the file. I hve noticed that sometimes the verilog
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//of the file. I hve noticed that sometimes the verilog
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//simulator allows you to use some regs even if they have not been
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//simulator allows you to use some regs even if they have not been
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//previously declared, leadeing to crahses or unexpected behavior
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//previously declared, leadeing to crahses or unexpected behavior
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// Inputs
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// Inputs
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reg Clock;
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reg Clock;
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reg Reset;
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reg Reset;
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reg ExternalBus_DataReady;
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// Outputs
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wire ExternalBus_Acknowledge;
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wire TaskCompleted;
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//CTE state machin logic
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reg[31:0] CurrentState,NextState;
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reg[3:0] LightCount;
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reg[31:0] rLaneA,rLaneB,rLaneC,rLaneD;
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reg[16:0] CurrentTaskId;
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reg[31:0] CurrentPixelRow, CurrentPixelCol,CurrentRayType;
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reg CTE_WriteEnable;
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wire [`WB_WIDTH-1:0] DAT_O;
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wire [`WB_WIDTH-1:0] DAT_O;
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reg ACK_O;
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reg ACK_O;
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wire ACK_I;
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wire ACK_I;
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wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
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wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
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wire WE_I,STB_I;
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wire WE_I,STB_I;
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reg CYC_O,WE_O,TGC_O,STB_O;
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wire CYC_O,WE_O,TGC_O,STB_O;
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wire [1:0] TGC_I;
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//wire [1:0] TGC_I;
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reg [1:0] TGA_O;
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wire [1:0] TGA_O;
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wire [1:0] TGA_I;
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wire [1:0] TGA_I;
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wire [31:0] DAT_I;
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//wire [`WB_WIDTH-1:0] DAT_I;
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integer ucode_file;
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reg [`WB_WIDTH-1:0] TMADR_O,TMDAT_O;
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reg [`MAX_TMEM_BANKS-1:0] TMSEL_O;
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reg TMWE_O;
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reg [31:0] rInitialCol,rInitialRow;
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reg [31:0] rControlRegister[2:0];
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reg [31:0] rControlRegister[2:0];
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integer file, log;
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integer file, log, r, a, b;
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reg [31:0] rSceneParameters[64:0];
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reg [31:0] rSceneParameters[64:0];
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reg [31:0] rVertexBuffer[6000:0];
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reg [31:0] rVertexBuffer[6000:0];
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reg [31:0] rInstructionBuffer[512:0];
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reg [31:0] rInstructionBuffer[512:0];
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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integer i,j;
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`define MAX_WIDTH 200
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`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
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reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
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reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
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//------------------------------------------------------------------------
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//Debug registers
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`define TASK_TIMEOUTMAX 150000//50000
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//------------------------------------------------------------------------
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reg MST_O;
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//---------------------------------------------------------------
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reg rIncCoreSelect;
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wire [`MAX_CORES-1:0] wCoreSelect;
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wire [`MAX_CORES-1:0] wCoreSelect;
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.Initial(`MAX_CORES'b1),
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.Enable(rIncCoreSelect),
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.O(wCoreSelect)
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);
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wire [3:0] CYC_I,GNT_O;
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wire [3:0] CYC_I,GNT_O;
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wire MST_O;
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wire wDone;
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wire wDone;
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reg [`MAX_CORES-1:0] rCoreSelectMask,rRenderEnable;
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wire [`MAX_CORES-1:0] RENDREN_O;
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reg [`MAX_CORE_BITS-1:0] wOMEMBankSelect;
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reg [`WB_WIDTH-1:0] wOMEMReadAddr; //Output adress (relative to current bank)
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wire [`WB_WIDTH-1:0] wOMEMData; //Output data bus (Wishbone)
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reg rHostEnable;
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integer k,out2;
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wire GRDY_I;
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wire GACK_O;
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wire STDONE_O;
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wire wGPUCommitedResults;
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wire wHostDataAvailable;
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THEIA GPU
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THEIA GPU
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(
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(
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.CLK_I( Clock ),
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.CLK_I( Clock ),
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.RST_I( Reset ),
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.RST_I( Reset ),
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.RENDREN_I( rRenderEnable ),
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.RENDREN_I( RENDREN_O ),
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.DAT_I( DAT_O ),
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.DAT_I( DAT_O ),
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.ADR_O( ADR_I ),
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// .ADR_O( ADR_I ),
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.ACK_I( ACK_O ),
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.ACK_I( ACK_O ),
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.WE_O ( WE_I ),
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//.WE_O ( WE_I ),
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.STB_O( STB_I ),
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//.STB_O( STB_I ),
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.CYC_I( CYC_O ),
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.CYC_I( CYC_O ),
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.TGC_O( TGC_I ),
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// .TGC_O( TGC_I ),
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.MST_I( MST_O ),
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.MST_I( MST_O ),
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.TGA_I( TGA_O ),
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.TGA_I( TGA_O ),
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.ACK_O( ACK_I ),
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.ACK_O( ACK_I ),
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.ADR_I( ADR_O ),
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.ADR_I( ADR_O ),
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.DAT_O( DAT_I ),
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// .DAT_O( DAT_I ),
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.WE_I( WE_O ),
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.WE_I( WE_O ),
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.SEL_I( wCoreSelect | rCoreSelectMask),//4'b0001 ),
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.SEL_I( wCoreSelect ),
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.STB_I( STB_O ),
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.STB_I( STB_O ),
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.TGA_O(TGA_I),
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// .TGA_O(TGA_I),
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//Output memory
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.OMBSEL_I( wOMEMBankSelect ),
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.OMADR_I( wOMEMReadAddr ),
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.OMEM_O( wOMEMData ),
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.TMDAT_I( TMDAT_O ),
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.TMADR_I( TMADR_O ),
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.TMWE_I( TMWE_O ),
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.TMSEL_I( TMSEL_O ),
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.GRDY_O( GRDY_I ),
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.GACK_I( GACK_O ),
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.STDONE_I( STDONE_O ),
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.RCOMMIT_O( wGPUCommitedResults ),
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.HDA_I( wHostDataAvailable ),
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//Control register
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//Control register
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.CREG_I( rControlRegister[0][15:0] ),
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.CREG_I( rControlRegister[0][15:0] ),
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//Other stuff
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//Other stuff
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.DONE_O( wDone )
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.DONE_O( wDone )
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);
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);
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wire[`WB_WIDTH-1:0] wHostReadAddress;
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wire[`WB_WIDTH-1:0] wHostReadData;
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wire[`WB_WIDTH-1:0] wMemorySize;
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wire[1:0] wMemSelect;
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX1
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(
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.Sel( wMemSelect ),
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.I1( rInstructionBuffer[wHostReadAddress] ),
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.I2( rSceneParameters[wHostReadAddress] ),
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.I3( rVertexBuffer[wHostReadAddress] ),
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.I4(0),
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.O1(wHostReadData)
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);
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX2
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(
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.Sel( wMemSelect ),
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.I1( rInstructionBuffer[0] ),
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.I2( rSceneParameters[0] ),
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.I3( rVertexBuffer[0] ),
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.I4(0),
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.O1(wMemorySize)
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);
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Module_Host HOST
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iEnable( rHostEnable ),
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.oHostDataAvailable( wHostDataAvailable ),
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.iHostDataReadConfirmed( GRDY_I ),
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.iMemorySize( wMemorySize ),
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.iPrimitiveCount( (rVertexBuffer[6]+1) *7 ),
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.iGPUCommitedResults( wGPUCommitedResults ),
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.STDONE_O( STDONE_O ),
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.iGPUDone( wDone ),
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//To Memory
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.oReadAddress( wHostReadAddress ),
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.iReadData( wHostReadData ),
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//To Hub/Switch
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.oCoreSelectMask( wCoreSelect ),
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.oMemSelect( wMemSelect ),
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.DAT_O( DAT_O),
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.ADR_O( ADR_O ),
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.TGA_O( TGA_O ),
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.RENDREN_O( RENDREN_O ),
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.CYC_O( CYC_O ),
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.STB_O( STB_O ),
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.MST_O( MST_O ),
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.GRDY_I( GRDY_I ),
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.GACK_O( GACK_O ),
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.WE_O( WE_O ),
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.ACK_I( ACK_I )
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);
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//---------------------------------------------
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//---------------------------------------------
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//generate the clock signal here
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//generate the clock signal here
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always begin
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always begin
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#`CLOCK_CYCLE Clock = ! Clock;
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#`CLOCK_CYCLE Clock = ! Clock;
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end
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end
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//---------------------------------------------
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//---------------------------------------------
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`define PARTITION_SIZE `RESOLUTION_HEIGHT/`MAX_CORES
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integer i,j,kk;
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reg [31:0] R;
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always @ ( * )
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begin
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if (wDone == 1'b1)
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begin
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$display("Partition Size = %d",`PARTITION_SIZE);
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for (kk = 0; kk < 4; kk = kk+1)
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begin
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wOMEMBankSelect = kk;
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$display("wOMEMBankSelect = %d\n",wOMEMBankSelect);
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for (j=0; j < `PARTITION_SIZE; j=j+1)//for (j = 0; j < 15; j = j+1) //LOOK OUT 15 is hardcoded!!!!!!!!
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begin
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for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
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begin
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wOMEMReadAddr = i+j*`RESOLUTION_WIDTH*3;
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#`CLOCK_PERIOD;
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#1;
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R = ((wOMEMData >> (`SCALE-8)) > 255) ? 255 : (wOMEMData >> (`SCALE-8));
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$fwrite(out2,"%d " , R );
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if ((i %3) == 0)
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$fwrite(out2,"\n# %d %d\n",i/3,j);
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end
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end
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end
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$fclose(out2);
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$fwrite(log, "Simulation end time : %dns\n",$time);
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$fclose(log);
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$stop();
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end
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end
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reg [15:0] rTimeOut;
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reg [15:0] rTimeOut;
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`define MAX_INSTRUCTIONS 2
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`define MAX_INSTRUCTIONS 2
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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Clock = 0;
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Clock = 0;
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Reset = 0;
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Reset = 0;
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CTE_WriteEnable = 0;
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rLaneA = 32'b0;
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rLaneB = 32'b0;
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rLaneC = 32'b0;
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rLaneD = 32'b0;
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ExternalBus_DataReady = 0;
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rTimeOut = 0;
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rTimeOut = 0;
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rHostEnable = 0;
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`ifdef DUMP_CODE
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$write("Opening TestBench.log.... ");
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ucode_file = $fopen("TestBench.log","w");
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$display("Done");
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`endif
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//Read Config register values
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//Read Config register values
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$write("Loading control register.... ");
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$write("Loading control register.... ");
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$readmemh("Creg.mem",rControlRegister);
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$readmemh("Creg.mem",rControlRegister);
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$display("Done");
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$display("Done");
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//Read configuration Data
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//Read configuration Data
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$write("Loading scene parameters.... ");
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$write("Loading scene parameters.... ");
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$readmemh("Params.mem", rSceneParameters );
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$readmemh("Params.mem", rSceneParameters );
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$display("Done");
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$display("Done");
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rInitialRow = rSceneParameters[18];
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rInitialCol = rSceneParameters[19];
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//Read Scene Data
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//Read Scene Data
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$write("Loading scene geometry.... ");
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$write("Loading scene geometry.... ");
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$readmemh("Vertex.mem",rVertexBuffer);
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$readmemh("Vertex.mem",rVertexBuffer);
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$display("Done");
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$display("Done");
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//Read Texture Data
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//Read Texture Data
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$write("Loading scene texture.... ");
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$write("Loading scene texture.... ");
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$readmemh("Textures.mem",rTextures);
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$readmemh("Textures.mem",rTextures);
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$display("Done");
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$display("Done");
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//Read instruction data
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//Read instruction data
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$write("Loading code allocation table and user shaders.... ");
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$write("Loading code allocation table and user shaders.... ");
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$readmemh("Instructions.mem",rInstructionBuffer);
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$readmemh("Instructions.mem",rInstructionBuffer);
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$display("Done");
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$display("Done");
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$display("Control Register : %b",rControlRegister[0]);
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$display("Control Register : %b",rControlRegister[0]);
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$display("Initial Row : %h",rInitialRow);
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$display("Initial Column : %h",rInitialCol);
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$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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//Open output file
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//Open output file
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file = $fopen("Output.ppm");
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// file = $fopen("Output.ppm");
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log = $fopen("Simulation.log");
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log = $fopen("Simulation.log");
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$fwrite(log, "Simulation start time : %dns\n",$time);
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$fwrite(log, "Simulation start time : %dns\n",$time);
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$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
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$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
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$fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
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$fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
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$fwrite(file,"P3\n");
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// $fwrite(file,"P3\n");
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$fwrite(file,"#This file was generated by Theia's RTL simulation\n");
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// $fwrite(file,"#This file was generated by Theia's RTL simulation\n");
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$fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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// $fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$fwrite(file,"255\n");
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// $fwrite(file,"255\n");
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//Open output file
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out2 = $fopen("Output.ppm");
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$fwrite(out2,"P3\n");
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$fwrite(out2,"#This file was generated by Theia's RTL simulation\n");
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$fwrite(out2,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
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$fwrite(out2,"255\n");
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CurrentPixelRow = 0;
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CurrentPixelCol = 0;
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#10
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#10
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Reset = 1;
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Reset = 1;
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ExternalBus_DataReady = 0;
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|
|
// Wait 100 ns for global reset to finish
|
// Wait 100 ns for global reset to finish
|
|
TMWE_O = 1;
|
#100 Reset = 0;
|
#100 Reset = 0;
|
|
TMWE_O = 1;
|
|
|
end
|
$display("Intilializing TMEM @ %dns",$time);
|
|
//starts in 2 to skip Width and Height
|
reg [5:0] DataIndex;
|
for (k = 0;k < `TEXTURE_BUFFER_SIZE; k = k + 1)
|
reg [31:0] ConfigurationPacketSize;
|
|
|
|
reg [7:0] R,G,B;
|
|
|
|
|
|
//---------------------------------------------
|
|
|
|
always @ (posedge Clock)
|
|
begin
|
begin
|
rTimeOut = rTimeOut+1'b1;
|
|
if (rTimeOut > `TASK_TIMEOUTMAX)
|
|
begin
|
|
$display("%dns ERROR: THEIA Timed out after %d of inactivity\n",
|
|
$time(),rTimeOut);
|
|
$stop();
|
|
end
|
|
end
|
|
|
|
reg [31:0] rSlaveData_O;
|
|
//reg [31:0] rOutputFrameBuffer[39000:0];
|
|
reg [31:0] rColor;
|
|
|
|
reg [7:0] Thingy;
|
|
//Wish-Bone Slave logic.
|
|
//
|
|
//This logic represents a WBS FSM. It will provide
|
|
//the memory for Vertex and Texture data.
|
|
//Vertex/Tetxure data is stored in a 4GB RAM.
|
|
//Vertex data starts at address 0 and ends at address 0x80_000_000.
|
|
//Texture data starts at address 0x80_000_000 and ends at address
|
|
//0xFFFFFFFF.
|
|
//The Bit 31, indcates wheather we look for vertex (b=0)
|
|
//or texture (b=1)
|
|
|
|
`define WBS_AFTER_RESET 0
|
|
`define WBS_MOINTOR_STB_I 1
|
|
`define WBS_ACK_O 2
|
|
`define WBS_MOINTOR_STB_I_NEG 3
|
|
`define WBS_DONE 4
|
|
|
|
reg [7:0] WBSCurrentState,WBSNextState;
|
TMADR_O <= (k >> (`MAX_TMEM_BANKS/2));
|
reg [31:0] rAddress;
|
TMSEL_O <= (k & (`MAX_TMEM_BANKS-1));
|
|
TMDAT_O <= rTextures[k];
|
always @(negedge Clock)
|
#10;
|
begin
|
|
if( Reset!=1 )
|
|
WBSCurrentState = WBSNextState;
|
|
else
|
|
WBSCurrentState = `WBS_AFTER_RESET;
|
|
end
|
end
|
|
$display("Done Intilializing TMEM @ %dns",$time);
|
|
TMWE_O = 0;
|
|
rHostEnable = 1;
|
|
|
|
|
|
|
reg [31:0] rConvertedTextureAddress;
|
|
//----------------------------------------------------------
|
|
always @(posedge Clock)
|
|
begin
|
|
case (WBSCurrentState)
|
|
//----------------------------------------
|
|
`WBS_AFTER_RESET:
|
|
begin
|
|
ACK_O = 0;
|
|
rSlaveData_O = 32'b0;
|
|
|
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
|
end
|
end
|
//----------------------------------------
|
|
`WBS_MOINTOR_STB_I:
|
|
begin
|
|
if ( STB_I == 1 && wDone == 0)
|
|
WBSNextState = `WBS_ACK_O;
|
|
else if (STB_I == 0 && wDone == 0)
|
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
|
else
|
|
WBSNextState = `WBS_DONE;
|
|
end
|
|
//----------------------------------------
|
|
`WBS_ACK_O:
|
|
begin
|
|
if (WE_I == 0)
|
|
begin
|
|
|
|
rAddress = ADR_I;
|
|
if (TGA_I == 2'b01) //replace this by TGA_I
|
|
begin
|
|
//Multiply pithc (3), Add 2 because the first 2 bytes are text Width, Height
|
|
rConvertedTextureAddress = {1'b0,rAddress[30:0]} + 2;
|
|
if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)
|
|
rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;
|
|
|
|
|
|
rSlaveData_O = rTextures[ rConvertedTextureAddress ];
|
|
`ifdef DEBUG_WBM
|
|
|
|
`LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
|
|
`endif
|
|
end
|
|
else
|
|
begin
|
|
// Thingy = 0; //THIS IS NOT RE-ENTRANT!!!
|
|
rSlaveData_O = rVertexBuffer[ rAddress ];
|
|
`ifdef DEBUG_WBM
|
|
`LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
|
|
`endif
|
|
end
|
|
|
|
end
|
|
else
|
|
begin
|
|
// $display("%d Theia Writes value: %h @ %d (Time to process pixel %d Clock cycle)",$time, DAT_I,ADR_I,rTimeOut);
|
|
|
|
|
|
// if (Thingy == 0)
|
|
// begin
|
|
|
|
// end
|
|
|
|
// Thingy = Thingy + 1;
|
|
if (CurrentPixelCol >= (`RESOLUTION_WIDTH*3))
|
|
begin
|
|
CurrentPixelCol = 0;
|
|
CurrentPixelRow = CurrentPixelRow + 1;
|
|
$display("]- %d (%d)",CurrentPixelRow,ADR_I);
|
|
$write("[");
|
|
end
|
|
|
|
// if (Thingy == 3)
|
|
// begin
|
|
CurrentPixelCol = CurrentPixelCol + 1;
|
|
if ( CurrentPixelCol % 3 == 0)
|
|
begin
|
|
// $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);
|
|
$write(".");
|
|
end
|
|
//Thingy = 0;
|
|
// end
|
|
rTimeOut = 0;
|
|
R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >> (`SCALE-8));
|
|
rScreen[ ADR_I ] = R;
|
|
// $fwrite(file,"%d " , R );
|
|
|
|
end
|
|
|
|
|
|
ACK_O = 1;
|
|
|
|
// if (CurrentPixelRow >= `RESOLUTION_HEIGHT)
|
|
if (wDone)
|
|
WBSNextState = `WBS_DONE;
|
|
else
|
|
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
|
end
|
|
//----------------------------------------
|
|
`WBS_MOINTOR_STB_I_NEG:
|
|
begin
|
|
if ( STB_I == 0 )
|
|
begin
|
|
ACK_O = 0;
|
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
|
end
|
|
else
|
|
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
|
end
|
|
//----------------------------------------
|
|
`WBS_DONE:
|
|
begin
|
|
for (j = 0; j < `RESOLUTION_WIDTH; j = j+1)
|
|
begin
|
|
|
|
for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
|
|
begin
|
|
|
|
$fwrite(file,"%d " , rScreen[i+j*`RESOLUTION_WIDTH*3] );
|
|
if ((i %3) == 0)
|
|
$fwrite(file,"\n# %d %d\n",i,j);
|
|
|
|
end
|
|
end
|
|
$display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",
|
|
`RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);
|
|
$display("ADR_I = %d\n",ADR_I);
|
|
`LOGME"RENDER COMPLETE");
|
|
`LOGME"Closing File");
|
|
$fclose(file);
|
|
$fwrite(log, "Simulation end time : %dns\n",$time);
|
|
$fclose(log);
|
|
`LOGME"File Closed");
|
|
$stop();
|
|
$fclose(ucode_file);
|
|
end
|
|
//----------------------------------------
|
|
default:
|
|
begin
|
|
$display("WBS Undefined state");
|
|
end
|
|
endcase
|
|
end //end always
|
|
//----------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
`define TAG_BLOCK_WRITE_CYCLE 2'b01
|
|
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
|
|
`define TAG_DATA_ADDRESS_TYPE 2'b10
|
|
|
|
`define WBM_AFTER_RESET 0
|
|
`define WBM_WRITE_INSTRUCTION_PHASE1 1
|
|
`define WBM_ACK_INSTRUCTION_PHASE1 2
|
|
`define WBM_WRITE_INSTRUCTION_PHASE2 3
|
|
`define WBM_ACK_INSTRUCTION_PHASE2 4
|
|
`define WBM_END_INSTRUCTION_WRITE_CYCLE 5
|
|
`define WBM_SEND_DATA_PHASE1 6
|
|
`define WBM_ACK_DATA_PHASE1 7
|
|
`define WBM_SEND_DATA_PHASE2 8
|
|
`define WBM_ACK_DATA_PHASE2 9
|
|
`define WBM_SEND_DATA_PHASE3 10
|
|
`define WBM_ACK_DATA_PHASE3 11
|
|
`define WBM_END_DATA_WRITE_CYCLE 12
|
|
`define WBM_DONE 13
|
|
`define WBM_CONFIGURE_CORE0_PHASE1 14
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE1 15
|
|
`define WBM_CONFIGURE_CORE0_PHASE2 16
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE2 17
|
|
`define WBM_CONFIGURE_CORE0_PHASE3 18
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE3 19
|
|
`define WBM_CONFIGURE_CORE1_PHASE1 20
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE1 21
|
|
`define WBM_CONFIGURE_CORE1_PHASE2 22
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE2 23
|
|
`define WBM_CONFIGURE_CORE1_PHASE3 24
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE3 25
|
|
`define WBM_END_CORE0_WRITE_CYCLE 26
|
|
`define WBM_END_CORE1_WRITE_CYCLE 27
|
|
|
|
`define WBM_CONFIGURE_CORE2_PHASE1 28
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE1 29
|
|
`define WBM_CONFIGURE_CORE2_PHASE2 30
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE2 31
|
|
`define WBM_CONFIGURE_CORE2_PHASE3 32
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE3 33
|
|
`define WBM_CONFIGURE_CORE3_PHASE1 34
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE1 35
|
|
`define WBM_CONFIGURE_CORE3_PHASE2 36
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE2 37
|
|
`define WBM_CONFIGURE_CORE3_PHASE3 38
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE3 39
|
|
`define WBM_END_CORE2_WRITE_CYCLE 40
|
|
`define WBM_END_CORE3_WRITE_CYCLE 41
|
|
`define WBM_CONFIGURE_NEXT_CORE 42
|
|
|
|
|
|
reg[31:0] rInstructionPointer;
|
|
reg[31:0] rAddressToSend;
|
|
reg[31:0] rDataAddress;
|
|
reg[31:0] rDataPointer;
|
|
|
|
reg IncIP,IncIA,IncDP;
|
|
reg rPrepateWriteAddressForNextCore;
|
|
reg rClearOutAddress;
|
|
//-----------------------------------------------------
|
|
always @ (posedge Clock or posedge rClearOutAddress)
|
|
begin
|
|
|
|
if ( IncIA && ~rClearOutAddress)
|
|
rAddressToSend = rAddressToSend + 1;
|
|
else if (rClearOutAddress)
|
|
begin
|
|
if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
|
|
rAddressToSend = {16'd1,16'd0};
|
|
else if (rPrepateWriteAddressForNextCore)
|
|
rAddressToSend = `CREG_PIXEL_2D_INITIAL_POSITION;
|
|
else
|
|
rAddressToSend = 0;
|
|
end
|
|
|
|
|
|
end
|
|
//-----------------------------------------------------
|
|
always @ (posedge ACK_I or posedge Reset )
|
|
begin
|
|
|
|
if ( ACK_I && ~Reset)
|
|
rInstructionPointer = rInstructionPointer + 1;
|
|
else if (Reset)
|
|
rInstructionPointer = 0;
|
|
|
|
|
|
|
|
end
|
|
//-----------------------------------------------------
|
|
reg rResetDp;
|
|
|
|
always @ (posedge Clock or posedge rResetDp )
|
|
begin
|
|
|
|
if ( ACK_I && ~rResetDp)//IncDP && ~Reset)
|
|
rDataPointer = rDataPointer + 1;
|
|
else if (rResetDp)
|
|
rDataPointer = 32'b0;
|
|
|
|
|
|
end
|
|
|
|
reg rIncPacketCount;
|
|
reg [`WIDTH-1:0] rPacketCount;
|
|
|
|
always @ (posedge Clock)
|
|
begin
|
|
if (Reset)
|
|
rPacketCount = 0;
|
|
else
|
|
begin
|
|
if ( rIncPacketCount )
|
|
rPacketCount = rPacketCount + 1;
|
|
end
|
|
end
|
|
//-----------------------------------------------------
|
|
|
|
|
|
|
|
|
|
assign DAT_O = ( MST_O == 1'b1 ) ? wMasteData_O : rSlaveData_O;
|
|
|
|
wire[31:0] wMasteData_O;
|
|
|
|
|
|
|
|
assign wMasteData_O = (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE) ? rInstructionBuffer[rInstructionPointer+1] : rSceneParameters[ rDataPointer ];
|
|
|
|
|
|
always @ (posedge STB_O)
|
|
begin
|
|
if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
|
|
begin
|
|
//$display("-- %x\n",wMasteData_O);
|
|
end
|
|
end
|
|
assign ADR_O = rAddressToSend;
|
|
|
|
reg [7:0] WBMCurrentState,WBMNextState;
|
|
reg [31:0] rWriteAddress;
|
|
|
|
always @(posedge Clock or posedge Reset)
|
|
begin
|
|
if( Reset!=1 )
|
|
WBMCurrentState = WBMNextState;
|
|
else
|
|
WBMCurrentState = `WBM_AFTER_RESET;
|
|
end
|
|
|
|
wire[31:0] wConfigurationPacketSize;
|
|
assign wConfigurationPacketSize = rSceneParameters[2];
|
|
|
|
reg [31:0] InstructionIndex;
|
|
reg [31:0] InstructionWriteAddress;
|
|
//Send the instructions now...
|
|
//----------------------------------------------------------
|
|
always @(posedge Clock)
|
|
begin
|
|
case (WBMCurrentState)
|
|
//----------------------------------------
|
|
|
|
//Wait until the reset secuence is complete to
|
|
//begin sending stuff.
|
|
|
|
`WBM_AFTER_RESET:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0;
|
|
TGC_O <= 0;
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
|
STB_O <= 0;
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 0;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rClearOutAddress <= 1;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if (Reset == 0)
|
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_AFTER_RESET;
|
|
end
|
|
//----------------------------------------
|
|
|
|
//CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()]
|
|
//MASTER presents valid data on [DAT_O()]
|
|
//MASTER asserts [WE_O] to indicate a WRITE cycle.
|
|
//MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle.
|
|
//MASTER asserts [STB_O] to indicate the start of the phase.
|
|
|
|
`WBM_WRITE_INSTRUCTION_PHASE1:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_INSTRUCTION_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_WRITE_INSTRUCTION_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
|
STB_O <= ~ACK_I;
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_INSTRUCTION_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 0;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
|
|
STB_O <= 0; //*
|
|
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if (rInstructionPointer >= rInstructionBuffer[0])
|
|
begin
|
|
IncIA <= 0;//*
|
|
rClearOutAddress <= 1;
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
|
end
|
|
else
|
|
begin
|
|
IncIA <= 1;//*
|
|
rClearOutAddress <= 0;
|
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
|
end
|
|
|
|
end
|
|
//****************************************
|
|
`WBM_SEND_DATA_PHASE1:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_DATA_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_SEND_DATA_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= ~ACK_I;
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_DATA_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //*
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;//*
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_SEND_DATA_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= ~ACK_I;
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_DATA_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_DATA_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //*
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 1;//*
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
|
WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_END_DATA_WRITE_CYCLE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0; //*
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 1;//*
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
|
if (rDataPointer > 3*5)//wConfigurationPacketSize*3)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE1:
|
|
begin
|
|
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE2:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE3:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 1;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_END_CORE0_WRITE_CYCLE;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_END_CORE0_WRITE_CYCLE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0; //*
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 1;//*
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if ((rPacketCount %2) == 0) //Two packets per Core
|
|
begin
|
|
rClearOutAddress <= 1;
|
|
rPrepateWriteAddressForNextCore <= 1;
|
|
WBMNextState <= `WBM_CONFIGURE_NEXT_CORE;
|
|
end
|
|
else
|
|
begin
|
|
rClearOutAddress <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
|
|
end
|
|
|
|
//------------------------------------------
|
|
|
|
`WBM_CONFIGURE_NEXT_CORE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0;
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
|
|
rCoreSelectMask <= 0;
|
|
rIncCoreSelect <= 1;
|
|
rRenderEnable <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
if (wCoreSelect[`MAX_CORES-1] == 1)
|
|
WBMNextState <= `WBM_DONE;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
|
|
|
|
end
|
|
|
|
|
|
|
|
//----------------------------------------
|
|
//Here everything is ready so just start!
|
|
|
|
`WBM_DONE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0;
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 0;
|
|
IncDP <= 0;
|
|
rResetDp <= 1;
|
|
rClearOutAddress <= 1;
|
|
rCoreSelectMask <= 0;
|
|
rRenderEnable <= 4'b1111;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
WBMNextState <= `WBM_DONE;
|
|
end
|
|
//----------------------------------------
|
|
|
|
|
|
endcase
|
|
end //end always
|
|
//----------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
