Subversion Repositories theia_gpu

/**********************************************************************************

/**********************************************************************************

Theia, Ray Cast Programable graphic Processing Unit.

Theia, Ray Cast Programable graphic Processing Unit.

Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)

Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)

This program is free software; you can redistribute it and/or

This program is free software; you can redistribute it and/or

modify it under the terms of the GNU General Public License

modify it under the terms of the GNU General Public License

as published by the Free Software Foundation; either version 2

as published by the Free Software Foundation; either version 2

of the License, or (at your option) any later version.

of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful,

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

along with this program; if not, write to the Free Software

Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

***********************************************************************************/

***********************************************************************************/

/*******************************************************************************

/*******************************************************************************

Module Description:

Module Description:

This is the Main test bench of the GPU. It simulates the behavior of

This is the Main test bench of the GPU. It simulates the behavior of

an external control unit or CPU that sends configuration information into DUT.

an external control unit or CPU that sends configuration information into DUT.

It also implements a second processs that simulates a Wishbone slave that sends

It also implements a second processs that simulates a Wishbone slave that sends

data from an external memory. These blocks are just behavioral CTE and therefore

data from an external memory. These blocks are just behavioral CTE and therefore

are not meant to be synthethized.

are not meant to be synthethized.

*******************************************************************************/

*******************************************************************************/

`timescale 1ns / 1ps

`timescale 1ns / 1ps

`include "aDefinitions.v"

`include "aDefinitions.v"

`define CONFIGURATION_PHASE                                             0

`define CONFIGURATION_PHASE                                             0

`define CTE_INITIAL_STATE                                                       0

`define CTE_INITIAL_STATE                                                       0

`define CTE_IDLE                                                                                1

`define CTE_IDLE                                                                                1

`define CTE_START_EU_CONFIGURATION_SEQUENCE     2

`define CTE_START_EU_CONFIGURATION_SEQUENCE     2

`define CTE_SEND_CONFIGURATION_PACKET                   3

`define CTE_SEND_CONFIGURATION_PACKET                   3

`define CTE_ACK_CONFIGURATION_PACKET                    8

`define CTE_ACK_CONFIGURATION_PACKET                    8

`define CTE_SEND_LIGHT_PACKET                                           13

`define CTE_SEND_LIGHT_PACKET                                           13

`define CTE_ACK_LIGTH_PACKET                                            14

`define CTE_ACK_LIGTH_PACKET                                            14

`define CTE_SEND_RAY_I_TASK                                             15

`define CTE_SEND_RAY_I_TASK                                             15

`define CTE_WAIT_FOR_TASK_ACK                                           16

`define CTE_WAIT_FOR_TASK_ACK                                           16

`define WAIT_FOR_TASK_COMPLETE                                  17

`define WAIT_FOR_TASK_COMPLETE                                  17

`define CTE_PREPARE_NEW_TASK                                            18

`define CTE_PREPARE_NEW_TASK                                            18

`define CTE_RENDER_DONE                                                         19

`define CTE_RENDER_DONE                                                         19

`define CTE_READ_COLOR_DATA                                             20

`define CTE_READ_COLOR_DATA                                             20

`define CTE_GRANT_BUS_WRITE_PERMISION                   21

`define CTE_GRANT_BUS_WRITE_PERMISION                   21

`define CTE_ACK_GRANT_BUS_PERMISION                             22

`define CTE_ACK_GRANT_BUS_PERMISION                             22

`define CTE_ACK_READ_COLOR_DATA                                 23

`define CTE_ACK_READ_COLOR_DATA                                 23

`define CTE_SEND_TEXTURE_DIMENSIONS                             24

`define CTE_SEND_TEXTURE_DIMENSIONS                             24

`define CTE_ACK_TEXTURE_DIMENSIONS                              25

`define CTE_ACK_TEXTURE_DIMENSIONS                              25

`define RESOLUTION_WIDTH                                                        (rSceneParameters[12] >> `SCALE)

`define RESOLUTION_WIDTH                                                        (rSceneParameters[12] >> `SCALE)

`define RESOLUTION_HEIGHT                                                       (rSceneParameters[13] >> `SCALE)

`define RESOLUTION_HEIGHT                                                       (rSceneParameters[13] >> `SCALE)

`define RAYI_TASK                                                                               1

`define RAYI_TASK                                                                               1

`define DELTA_ROW                                                                       (32'h1 << `SCALE)

`define DELTA_ROW                                                                       (32'h1 << `SCALE)

`define DELTA_COL                                                                       (32'h1 << `SCALE)

`define DELTA_COL                                                                       (32'h1 << `SCALE)

module TestBench_Theia;

module TestBench_Theia;

        //------------------------------------------------------------------------

        //------------------------------------------------------------------------

        //**WARNING: Declare all of your varaibles at the begining

        //**WARNING: Declare all of your varaibles at the begining

        //of the file. I hve noticed that sometimes the verilog

        //of the file. I hve noticed that sometimes the verilog

        //simulator allows you to use some regs even if they have not been 

        //simulator allows you to use some regs even if they have not been 

        //previously declared, leadeing to crahses or unexpected behavior

        //previously declared, leadeing to crahses or unexpected behavior

        // Inputs

        // Inputs

        reg Clock;

        reg Clock;

        reg Reset;

        reg Reset;

        reg ExternalBus_DataReady;

        reg ExternalBus_DataReady;

        // Outputs

        // Outputs

        wire ExternalBus_Acknowledge;

        wire ExternalBus_Acknowledge;

        wire TaskCompleted;

        wire TaskCompleted;

        //CTE state machin logic

        //CTE state machin logic

        reg[31:0] CurrentState,NextState;

        reg[31:0] CurrentState,NextState;

        reg[3:0]  LightCount;

        reg[3:0]  LightCount;

        reg[31:0] rLaneA,rLaneB,rLaneC,rLaneD;

        reg[31:0] rLaneA,rLaneB,rLaneC,rLaneD;

        reg[16:0] CurrentTaskId;

        reg[16:0] CurrentTaskId;

        reg[31:0] CurrentPixelRow, CurrentPixelCol,CurrentRayType;

        reg[31:0] CurrentPixelRow, CurrentPixelCol,CurrentRayType;

        reg CTE_WriteEnable;

        reg CTE_WriteEnable;

        wire [`WB_WIDTH-1:0] DAT_O;

        wire [`WB_WIDTH-1:0] DAT_O;

        reg                                             ACK_O;

        reg                                             ACK_O;

        wire                                            ACK_I;

        wire                                            ACK_I;

        wire [`WB_WIDTH-1:0] ADR_I,ADR_O;

        wire [`WB_WIDTH-1:0] ADR_I,ADR_O;

        wire                                            WE_I,STB_I;

        wire                                            WE_I,STB_I;

        reg CYC_O,WE_O,TGC_O,STB_O;

        reg CYC_O,WE_O,TGC_O,STB_O;

        wire [1:0] TGC_I;

        wire [1:0] TGC_I;

        reg [1:0] TGA_O;

        reg [1:0] TGA_O;

        wire [1:0] TGA_I;

        wire [1:0] TGA_I;

        wire [31:0] DAT_I;

        wire [31:0] DAT_I;

        integer ucode_file;

        integer ucode_file;

        reg [31:0] rInitialCol,rInitialRow;

        reg [31:0] rInitialCol,rInitialRow;

        reg [31:0]       rControlRegister[2:0];

        reg [31:0]       rControlRegister[2:0];

        integer file, log, r, a, b;

        integer file, log, r, a, b;

        reg [31:0]       rVertexBuffer[6000:0];

        reg [31:0]       rVertexBuffer[6000:0];

        reg [31:0]       rInstructionBuffer[512:0];

        reg [31:0]       rInstructionBuffer[512:0];

        `define TEXTURE_BUFFER_SIZE (256*256*3)

        `define TEXTURE_BUFFER_SIZE (256*256*3)

        reg [31:0]  rTextures[`TEXTURE_BUFFER_SIZE:0];            //Lets asume we use 256*256 textures

        reg [31:0]  rTextures[`TEXTURE_BUFFER_SIZE:0];            //Lets asume we use 256*256 textures

        integer i,j;

        integer i,j;

        `define MAX_WIDTH 200

        `define MAX_WIDTH 200

        `define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)

        `define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)

        reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];

        reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];

        //------------------------------------------------------------------------

        //------------------------------------------------------------------------

        //Debug registers

        //Debug registers

        `define TASK_TIMEOUTMAX 150000//50000

        `define TASK_TIMEOUTMAX 150000//50000

        //------------------------------------------------------------------------

        //------------------------------------------------------------------------

                reg MST_O;

                reg MST_O;

//---------------------------------------------------------------       

//---------------------------------------------------------------       

wire [3:0] CYC_I,GNT_O;

wire [3:0] CYC_I,GNT_O;

wire wDone;

wire wDone;

THEIA GPU

THEIA GPU

                (

                (

                .CLK_I( Clock ),

                .CLK_I( Clock ),

                .RST_I( Reset ),

                .RST_I( Reset ),

                .RENDREN_I( rRenderEnable ),

                .RENDREN_I( rRenderEnable ),

                .DAT_I( DAT_O ),

                .DAT_I( DAT_O ),

                .ADR_O( ADR_I ),

                .ADR_O( ADR_I ),

                .ACK_I( ACK_O ),

                .ACK_I( ACK_O ),

                .WE_O ( WE_I ),

                .WE_O ( WE_I ),

                .STB_O( STB_I ),

                .STB_O( STB_I ),

                .CYC_I( CYC_O ),

                .CYC_I( CYC_O ),

                .TGC_O( TGC_I ),

                .TGC_O( TGC_I ),

                .MST_I( MST_O ),

                .MST_I( MST_O ),

                .TGA_I( TGA_O ),

                .TGA_I( TGA_O ),

                .ACK_O( ACK_I ),

                .ACK_O( ACK_I ),

                .ADR_I( ADR_O ),

                .ADR_I( ADR_O ),

                .DAT_O( DAT_I ),

                .DAT_O( DAT_I ),

                .WE_I(  WE_O  ),

                .WE_I(  WE_O  ),

                .STB_I( STB_O ),

                .STB_I( STB_O ),

                .TGA_O(TGA_I),

                .TGA_O(TGA_I),

                //Control register

                //Control register

                .CREG_I( rControlRegister[0][15:0] ),

                .CREG_I( rControlRegister[0][15:0] ),

                //Other stuff

                //Other stuff

                .DONE_O( wDone )

                .DONE_O( wDone )

        );

        );

        //---------------------------------------------

        //---------------------------------------------

        //generate the clock signal here

        //generate the clock signal here

        always begin

        always begin

                #`CLOCK_CYCLE  Clock =  ! Clock;

                #`CLOCK_CYCLE  Clock =  ! Clock;

        end

        end

        //---------------------------------------------

        //---------------------------------------------

reg [15:0] rTimeOut;

reg [15:0] rTimeOut;

                `define MAX_INSTRUCTIONS 2

                `define MAX_INSTRUCTIONS 2

        initial begin

        initial begin

                // Initialize Inputs

                // Initialize Inputs

                Clock                                   = 0;

                Clock                                   = 0;

                Reset                                   = 0;

                Reset                                   = 0;

                CTE_WriteEnable                 = 0;

                CTE_WriteEnable                 = 0;

                rLaneA                                  = 32'b0;

                rLaneA                                  = 32'b0;

                rLaneB                                  = 32'b0;

                rLaneB                                  = 32'b0;

                rLaneC                                  = 32'b0;

                rLaneC                                  = 32'b0;

                rLaneD                                  = 32'b0;

                rLaneD                                  = 32'b0;

                ExternalBus_DataReady = 0;

                ExternalBus_DataReady = 0;

                rTimeOut              = 0;

                rTimeOut              = 0;

        `ifdef DUMP_CODE

        `ifdef DUMP_CODE

                $write("Opening TestBench.log.... ");

                $write("Opening TestBench.log.... ");

                ucode_file = $fopen("TestBench.log","w");

                ucode_file = $fopen("TestBench.log","w");

                $display("Done");

                $display("Done");

        `endif

        `endif

                //Read Config register values

                //Read Config register values

                $write("Loading control register.... ");

                $write("Loading control register.... ");

                $readmemh("Creg.mem",rControlRegister);

                $readmemh("Creg.mem",rControlRegister);

                $display("Done");

                $display("Done");

                //Read configuration Data

                //Read configuration Data

                $write("Loading scene parameters.... ");

                $write("Loading scene parameters.... ");

                $readmemh("Params.mem", rSceneParameters        );

                $readmemh("Params.mem", rSceneParameters        );

                $display("Done");

                $display("Done");

                rInitialRow = rSceneParameters[18];

                rInitialRow = rSceneParameters[18];

                rInitialCol = rSceneParameters[19];

                rInitialCol = rSceneParameters[19];

                //Read Scene Data

                //Read Scene Data

                $write("Loading scene geometry.... ");

                $write("Loading scene geometry.... ");

                $readmemh("Vertex.mem",rVertexBuffer);

                $readmemh("Vertex.mem",rVertexBuffer);

                $display("Done");

                $display("Done");

                //Read Texture Data

                //Read Texture Data

                $write("Loading scene texture.... ");

                $write("Loading scene texture.... ");

                $readmemh("Textures.mem",rTextures);

                $readmemh("Textures.mem",rTextures);

                $display("Done");

                $display("Done");

                //Read instruction data

                //Read instruction data

                $write("Loading code allocation table and user shaders.... ");

                $write("Loading code allocation table and user shaders.... ");

                $readmemh("Instructions.mem",rInstructionBuffer);

                $readmemh("Instructions.mem",rInstructionBuffer);

                $display("Done");

                $display("Done");

                $display("Control Register : %b",rControlRegister[0]);

                $display("Control Register : %b",rControlRegister[0]);

                $display("Initial Row      : %h",rInitialRow);

                $display("Initial Row      : %h",rInitialRow);

                $display("Initial Column   : %h",rInitialCol);

                $display("Initial Column   : %h",rInitialCol);

                $display("Resolution       : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );

                $display("Resolution       : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );

                //Open output file

                //Open output file

                file = $fopen("Output.ppm");

                file = $fopen("Output.ppm");

                log  = $fopen("Simulation.log");

                log  = $fopen("Simulation.log");

                $fwrite(log, "Simulation start time : %dns\n",$time);

                $fwrite(log, "Simulation start time : %dns\n",$time);

                $fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);

                $fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);

                $fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);

                $fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);

                $fwrite(file,"P3\n");

                $fwrite(file,"P3\n");

                $fwrite(file,"#This file was generated by Theia's RTL simulation\n");

                $fwrite(file,"#This file was generated by Theia's RTL simulation\n");

                $fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );

                $fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );

                $fwrite(file,"255\n");

                $fwrite(file,"255\n");

                CurrentPixelRow = 0;

                CurrentPixelRow = 0;

                CurrentPixelCol = 0;

                CurrentPixelCol = 0;

                #10

                #10

                Reset = 1;

                Reset = 1;

                ExternalBus_DataReady = 0;

                ExternalBus_DataReady = 0;

                // Wait 100 ns for global reset to finish

                // Wait 100 ns for global reset to finish

                #100  Reset = 0;

                #100  Reset = 0;

        end

        end

        reg [5:0] DataIndex;

        reg [5:0] DataIndex;

        reg [31:0] ConfigurationPacketSize;

        reg [31:0] ConfigurationPacketSize;

        reg [7:0] R,G,B;

        reg [7:0] R,G,B;

//---------------------------------------------

//---------------------------------------------

always @ (posedge Clock)

always @ (posedge Clock)

begin

begin

        rTimeOut = rTimeOut+1'b1;

        rTimeOut = rTimeOut+1'b1;

        if (rTimeOut > `TASK_TIMEOUTMAX)

        if (rTimeOut > `TASK_TIMEOUTMAX)

        begin

        begin

                 $display("%dns ERROR: THEIA Timed out after %d of inactivity\n",

                 $display("%dns ERROR: THEIA Timed out after %d of inactivity\n",

                 $time(),rTimeOut);

                 $time(),rTimeOut);

                 $stop();

                 $stop();

        end

        end

end

end

reg [31:0] rSlaveData_O;

reg [31:0] rSlaveData_O;

//reg [31:0] rOutputFrameBuffer[39000:0];

//reg [31:0] rOutputFrameBuffer[39000:0];

reg [31:0] rColor;

reg [31:0] rColor;

reg [7:0] Thingy;

reg [7:0] Thingy;

//Wish-Bone Slave logic.

//Wish-Bone Slave logic.

//

//

//This logic represents a WBS FSM. It will provide

//This logic represents a WBS FSM. It will provide

//the memory for Vertex and Texture data.

//the memory for Vertex and Texture data.

//Vertex/Tetxure data is stored in a 4GB RAM.

//Vertex/Tetxure data is stored in a 4GB RAM.

//Vertex data starts at address 0 and ends at address 0x80_000_000.

//Vertex data starts at address 0 and ends at address 0x80_000_000.

//Texture data starts at address 0x80_000_000 and ends at address

//Texture data starts at address 0x80_000_000 and ends at address

//0xFFFFFFFF.

//0xFFFFFFFF.

//The Bit 31, indcates wheather we look for vertex (b=0)

//The Bit 31, indcates wheather we look for vertex (b=0)

//or texture (b=1)

//or texture (b=1)

`define WBS_AFTER_RESET                                 0

`define WBS_AFTER_RESET                                 0

`define WBS_MOINTOR_STB_I                               1

`define WBS_MOINTOR_STB_I                               1

`define WBS_ACK_O                                                       2

`define WBS_ACK_O                                                       2

`define WBS_MOINTOR_STB_I_NEG                   3

`define WBS_MOINTOR_STB_I_NEG                   3

`define WBS_DONE                    4

`define WBS_DONE                    4

        reg [7:0]                        WBSCurrentState,WBSNextState;

        reg [7:0]                        WBSCurrentState,WBSNextState;

        reg [31:0]                       rAddress;

        reg [31:0]                       rAddress;

        always @(negedge Clock)

        always @(negedge Clock)

        begin

        begin

        if( Reset!=1 )

        if( Reset!=1 )

           WBSCurrentState = WBSNextState;

           WBSCurrentState = WBSNextState;

                  else

                  else

                          WBSCurrentState = `WBS_AFTER_RESET;

                          WBSCurrentState = `WBS_AFTER_RESET;

        end

        end

        reg [31:0] rConvertedTextureAddress;

        reg [31:0] rConvertedTextureAddress;

        //----------------------------------------------------------    

        //----------------------------------------------------------    

        always @(posedge Clock)

        always @(posedge Clock)

        begin

        begin

                case (WBSCurrentState)

                case (WBSCurrentState)

                //----------------------------------------

                //----------------------------------------

                `WBS_AFTER_RESET:

                `WBS_AFTER_RESET:

                begin

                begin

                        ACK_O = 0;

                        ACK_O = 0;

                        rSlaveData_O = 32'b0;

                        rSlaveData_O = 32'b0;

                        WBSNextState = `WBS_MOINTOR_STB_I;

                        WBSNextState = `WBS_MOINTOR_STB_I;

                end

                end

                //----------------------------------------

                //----------------------------------------

                `WBS_MOINTOR_STB_I:

                `WBS_MOINTOR_STB_I:

                begin

                begin

                                if ( STB_I == 1 && wDone == 0)

                                if ( STB_I == 1 && wDone == 0)

                                WBSNextState = `WBS_ACK_O;

                                WBSNextState = `WBS_ACK_O;

                        else if (STB_I == 0 && wDone == 0)

                        else if (STB_I == 0 && wDone == 0)

                                WBSNextState = `WBS_MOINTOR_STB_I;

                                WBSNextState = `WBS_MOINTOR_STB_I;

                        else

                        else

                                WBSNextState = `WBS_DONE;

                                WBSNextState = `WBS_DONE;

                end

                end

                //----------------------------------------

                //----------------------------------------

                `WBS_ACK_O:

                `WBS_ACK_O:

                begin

                begin

                        if (WE_I == 0)

                        if (WE_I == 0)

                        begin

                        begin

                                rAddress = ADR_I;

                                rAddress = ADR_I;

                                if (TGA_I == 2'b01) //replace this by TGA_I

                                if (TGA_I == 2'b01) //replace this by TGA_I

                                begin

                                begin

                                 //Multiply pithc (3), Add 2 because the first 2 bytes are text Width, Height

                                 //Multiply pithc (3), Add 2 because the first 2 bytes are text Width, Height

                                rConvertedTextureAddress = {1'b0,rAddress[30:0]} + 2;

                                rConvertedTextureAddress = {1'b0,rAddress[30:0]} + 2;

                                if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)

                                if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)

                                        rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;

                                        rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;

                                        rSlaveData_O = rTextures[  rConvertedTextureAddress ];

                                        rSlaveData_O = rTextures[  rConvertedTextureAddress ];

                                        `LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );

                                        `LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );

                                        `endif

                                        `endif

                                end

                                end

                                else

                                else

                                begin

                                begin

                        //              Thingy = 0;  //THIS IS NOT RE-ENTRANT!!!

                        //              Thingy = 0;  //THIS IS NOT RE-ENTRANT!!!

                                        rSlaveData_O = rVertexBuffer[ rAddress ];

                                        rSlaveData_O = rVertexBuffer[ rAddress ];

                                        `LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);

                                        `LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);

                                        `endif

                                        `endif

                                end

                                end

                        end

                        end

                        else

                        else

                        begin

                        begin

                        //      $display("%d Theia Writes value: %h @ %d (Time to process pixel %d Clock cycle)",$time, DAT_I,ADR_I,rTimeOut);

                        //      $display("%d Theia Writes value: %h @ %d (Time to process pixel %d Clock cycle)",$time, DAT_I,ADR_I,rTimeOut);

                //      if (Thingy == 0)

                //      if (Thingy == 0)

                //      begin

                //      begin

                //      end     

                //      end     

                //      Thingy = Thingy + 1;

                //      Thingy = Thingy + 1;

                        if (CurrentPixelCol >=  (`RESOLUTION_WIDTH*3))

                        if (CurrentPixelCol >=  (`RESOLUTION_WIDTH*3))

                        begin

                        begin

                                CurrentPixelCol = 0;

                                CurrentPixelCol = 0;

                                CurrentPixelRow = CurrentPixelRow + 1;

                                CurrentPixelRow = CurrentPixelRow + 1;

                                $display("]- %d (%d)",CurrentPixelRow,ADR_I);

                                $display("]- %d (%d)",CurrentPixelRow,ADR_I);

                                $write("[");

                                $write("[");

                        end

                        end

                //      if (Thingy == 3)

                //      if (Thingy == 3)

                //      begin

                //      begin

                                CurrentPixelCol = CurrentPixelCol + 1;

                                CurrentPixelCol = CurrentPixelCol + 1;

                                if ( CurrentPixelCol % 3  == 0)

                                if ( CurrentPixelCol % 3  == 0)

                                begin

                                begin

                        //      $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);

                        //      $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);

                                $write(".");

                                $write(".");

                                end

                                end

                                //Thingy = 0;

                                //Thingy = 0;

                //      end     

                //      end     

                                rTimeOut = 0;

                                rTimeOut = 0;

                                R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >>  (`SCALE-8));

                                R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >>  (`SCALE-8));

                                rScreen[ ADR_I ] = R;

                                rScreen[ ADR_I ] = R;

                        //      $fwrite(file,"%d " , R );

                        //      $fwrite(file,"%d " , R );

                        end

                        end

                        ACK_O = 1;

                        ACK_O = 1;

                //      if (CurrentPixelRow >= `RESOLUTION_HEIGHT)

                //      if (CurrentPixelRow >= `RESOLUTION_HEIGHT)

                if (wDone)

                if (wDone)

                                WBSNextState = `WBS_DONE;

                                WBSNextState = `WBS_DONE;

                        else

                        else

                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;

                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;

                end

                end

                //----------------------------------------

                //----------------------------------------

                `WBS_MOINTOR_STB_I_NEG:

                `WBS_MOINTOR_STB_I_NEG:

                begin

                begin

                        if ( STB_I == 0 )

                        if ( STB_I == 0 )

                        begin

                        begin

                                ACK_O = 0;

                                ACK_O = 0;

                                WBSNextState = `WBS_MOINTOR_STB_I;

                                WBSNextState = `WBS_MOINTOR_STB_I;

                        end

                        end

                        else

                        else

                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;

                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;

                end

                end

                //----------------------------------------

                //----------------------------------------

                `WBS_DONE:

                `WBS_DONE:

                begin

                begin

                for (j = 0; j < `RESOLUTION_WIDTH; j = j+1)

                for (j = 0; j < `RESOLUTION_WIDTH; j = j+1)

                begin

                begin

                        for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)

                        for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)

                        begin

                        begin

                        $fwrite(file,"%d " , rScreen[i+j*`RESOLUTION_WIDTH*3] );

                        $fwrite(file,"%d " , rScreen[i+j*`RESOLUTION_WIDTH*3] );

                                if ((i %3) == 0)

                                if ((i %3) == 0)

                                                $fwrite(file,"\n# %d %d\n",i,j);

                                                $fwrite(file,"\n# %d %d\n",i,j);

                        end

                        end

                end

                end

                $display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",

                $display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",

                `RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);

                `RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);

                $display("ADR_I = %d\n",ADR_I);

                $display("ADR_I = %d\n",ADR_I);

                        `LOGME"RENDER COMPLETE");

                        `LOGME"RENDER COMPLETE");

                        `LOGME"Closing File");

                        `LOGME"Closing File");

                        $fclose(file);

                        $fclose(file);

                        $fwrite(log, "Simulation end time : %dns\n",$time);

                        $fwrite(log, "Simulation end time : %dns\n",$time);

                        $fclose(log);

                        $fclose(log);

                        `LOGME"File Closed");

                        `LOGME"File Closed");

                        $stop();

                        $stop();

                        $fclose(ucode_file);

                        $fclose(ucode_file);

                end

                end

                //----------------------------------------

                //----------------------------------------

                default:

                default:

                begin

                begin

                $display("WBS Undefined state");

                $display("WBS Undefined state");

                end

                end

                endcase

                endcase

        end     //end always

        end     //end always

        //----------------------------------------------------------    

        //----------------------------------------------------------    

`define TAG_BLOCK_WRITE_CYCLE    2'b01

`define TAG_BLOCK_WRITE_CYCLE    2'b01

`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01

`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01

`define TAG_DATA_ADDRESS_TYPE        2'b10

`define TAG_DATA_ADDRESS_TYPE        2'b10

`define WBM_AFTER_RESET                                                 0

`define WBM_AFTER_RESET                                                 0

`define WBM_WRITE_INSTRUCTION_PHASE1            1

`define WBM_WRITE_INSTRUCTION_PHASE1            1

`define WBM_ACK_INSTRUCTION_PHASE1                      2

`define WBM_ACK_INSTRUCTION_PHASE1                      2

`define WBM_WRITE_INSTRUCTION_PHASE2            3

`define WBM_WRITE_INSTRUCTION_PHASE2            3

`define WBM_ACK_INSTRUCTION_PHASE2                      4

`define WBM_ACK_INSTRUCTION_PHASE2                      4

`define WBM_END_INSTRUCTION_WRITE_CYCLE   5

`define WBM_END_INSTRUCTION_WRITE_CYCLE   5

`define WBM_SEND_DATA_PHASE1                          6

`define WBM_SEND_DATA_PHASE1                          6

`define WBM_ACK_DATA_PHASE1                           7

`define WBM_ACK_DATA_PHASE1                           7

`define WBM_SEND_DATA_PHASE2                          8

`define WBM_SEND_DATA_PHASE2                          8

`define WBM_ACK_DATA_PHASE2                           9

`define WBM_ACK_DATA_PHASE2                           9

`define WBM_SEND_DATA_PHASE3                          10

`define WBM_SEND_DATA_PHASE3                          10

`define WBM_ACK_DATA_PHASE3                           11

`define WBM_ACK_DATA_PHASE3                           11

`define WBM_END_DATA_WRITE_CYCLE          12

`define WBM_END_DATA_WRITE_CYCLE          12

`define WBM_DONE                          13

`define WBM_DONE                          13

`define WBM_CONFIGURE_CORE0_PHASE1        14

`define WBM_CONFIGURE_CORE0_PHASE1        14

`define WBM_ACK_CONFIGURE_CORE0_PHASE1    15

`define WBM_ACK_CONFIGURE_CORE0_PHASE1    15

`define WBM_CONFIGURE_CORE0_PHASE2        16

`define WBM_CONFIGURE_CORE0_PHASE2        16

`define WBM_ACK_CONFIGURE_CORE0_PHASE2    17

`define WBM_ACK_CONFIGURE_CORE0_PHASE2    17

`define WBM_CONFIGURE_CORE0_PHASE3        18

`define WBM_CONFIGURE_CORE0_PHASE3        18

`define WBM_ACK_CONFIGURE_CORE0_PHASE3    19

`define WBM_ACK_CONFIGURE_CORE0_PHASE3    19

`define WBM_CONFIGURE_CORE1_PHASE1        20

`define WBM_CONFIGURE_CORE1_PHASE1        20

`define WBM_ACK_CONFIGURE_CORE1_PHASE1    21

`define WBM_ACK_CONFIGURE_CORE1_PHASE1    21

`define WBM_CONFIGURE_CORE1_PHASE2        22

`define WBM_CONFIGURE_CORE1_PHASE2        22

`define WBM_ACK_CONFIGURE_CORE1_PHASE2    23

`define WBM_ACK_CONFIGURE_CORE1_PHASE2    23

`define WBM_CONFIGURE_CORE1_PHASE3        24

`define WBM_CONFIGURE_CORE1_PHASE3        24

`define WBM_ACK_CONFIGURE_CORE1_PHASE3    25

`define WBM_ACK_CONFIGURE_CORE1_PHASE3    25

`define WBM_END_CORE0_WRITE_CYCLE         26

`define WBM_END_CORE0_WRITE_CYCLE         26

`define WBM_END_CORE1_WRITE_CYCLE         27

`define WBM_END_CORE1_WRITE_CYCLE         27

reg[31:0] rInstructionPointer;

reg[31:0] rInstructionPointer;

reg[31:0] rAddressToSend;

reg[31:0] rAddressToSend;

reg[31:0] rDataAddress;

reg[31:0] rDataAddress;

reg[31:0] rDataPointer;

reg[31:0] rDataPointer;

reg IncIP,IncIA,IncDP;

reg IncIP,IncIA,IncDP;

reg rPrepateWriteAddressForNextCore;

reg rPrepateWriteAddressForNextCore;

reg rClearOutAddress;

reg rClearOutAddress;

//-----------------------------------------------------

//-----------------------------------------------------

always @ (posedge Clock or posedge rClearOutAddress)

always @ (posedge Clock or posedge rClearOutAddress)

begin

begin

        if ( IncIA && ~rClearOutAddress)

        if ( IncIA && ~rClearOutAddress)

                rAddressToSend = rAddressToSend + 1;

                rAddressToSend = rAddressToSend + 1;

        else if (rClearOutAddress)

        else if (rClearOutAddress)

        begin

        begin

                if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)

                if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)

                        rAddressToSend =  {16'd1,16'd0};

                        rAddressToSend =  {16'd1,16'd0};