// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_fetchbuf.v
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// FT64_fetchbuf.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "FT64_config.vh"
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`include "FT64_config.vh"
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`include "FT64_defines.vh"
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`include "FT64_defines.vh"
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// FETCH
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// FETCH
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//
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//
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// fetch exactly two instructions from memory into the fetch buffer
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// fetch exactly two instructions from memory into the fetch buffer
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// unless either one of the buffers is still full, in which case we
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// unless either one of the buffers is still full, in which case we
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// do nothing (kinda like alpha approach)
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// do nothing (kinda like alpha approach)
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// Like to turn this into an independent module at some point.
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// Like to turn this into an independent module at some point.
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//
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//
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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module FT64_fetchbuf(rst, clk4x, clk, fcu_clk,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
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cmpgrp,
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cmpgrp,
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freezePC, thread_en,
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freezePC, thread_en,
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regLR,
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regLR,
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insn0, insn1, phit,
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insn0, insn1, phit,
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threadx,
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threadx,
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branchmiss, misspc, branchmiss_thrd, predict_taken0, predict_taken1,
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branchmiss, misspc, branchmiss_thrd, predict_taken0, predict_taken1,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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queued1, queued2, queuedNop,
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queued1, queued2, queuedNop,
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pc0, pc1, fetchbuf, fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v,
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pc0, pc1, fetchbuf, fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v,
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fetchbufA_instr, fetchbufA_pc,
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fetchbufA_instr, fetchbufA_pc,
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fetchbufB_instr, fetchbufB_pc,
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fetchbufB_instr, fetchbufB_pc,
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fetchbufC_instr, fetchbufC_pc,
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fetchbufC_instr, fetchbufC_pc,
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fetchbufD_instr, fetchbufD_pc,
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fetchbufD_instr, fetchbufD_pc,
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fetchbuf0_instr, fetchbuf1_instr, fetchbuf0_insln, fetchbuf1_insln,
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fetchbuf0_instr, fetchbuf1_instr, fetchbuf0_insln, fetchbuf1_insln,
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fetchbuf0_thrd, fetchbuf1_thrd,
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fetchbuf0_thrd, fetchbuf1_thrd,
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fetchbuf0_pc, fetchbuf1_pc,
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fetchbuf0_pc, fetchbuf1_pc,
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fetchbuf0_v, fetchbuf1_v,
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fetchbuf0_v, fetchbuf1_v,
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codebuf0, codebuf1,
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codebuf0, codebuf1,
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btgtA, btgtB, btgtC, btgtD,
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btgtA, btgtB, btgtC, btgtD,
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nop_fetchbuf,
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nop_fetchbuf,
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take_branch0, take_branch1,
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take_branch0, take_branch1,
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stompedRets,
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stompedRets,
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panic
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panic
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);
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);
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parameter AMSB = `AMSB;
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parameter AMSB = `AMSB;
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parameter RSTPC = 32'hFFFC0100;
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parameter RSTPC = 32'hFFFC0100;
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parameter TRUE = 1'b1;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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parameter FALSE = 1'b0;
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input rst;
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input rst;
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input clk4x;
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input clk4x;
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input clk;
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input clk;
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input fcu_clk;
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input fcu_clk;
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input cs_i;
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input cs_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output ack_o;
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output ack_o;
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input we_i;
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input we_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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input [47:0] dat_i;
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input [47:0] dat_i;
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input [2:0] cmpgrp;
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input [2:0] cmpgrp;
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input freezePC;
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input freezePC;
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input thread_en;
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input thread_en;
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input [4:0] regLR;
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input [4:0] regLR;
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input [47:0] insn0;
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input [47:0] insn0;
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input [47:0] insn1;
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input [47:0] insn1;
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input phit;
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input phit;
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output threadx;
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output threadx;
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input branchmiss;
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input branchmiss;
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input [AMSB:0] misspc;
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input [AMSB:0] misspc;
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input branchmiss_thrd;
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input branchmiss_thrd;
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output predict_taken0;
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output predict_taken0;
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output predict_taken1;
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output predict_taken1;
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input predict_takenA;
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input predict_takenA;
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input predict_takenB;
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input predict_takenB;
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input predict_takenC;
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input predict_takenC;
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input predict_takenD;
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input predict_takenD;
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input queued1;
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input queued1;
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input queued2;
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input queued2;
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input queuedNop;
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input queuedNop;
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output reg [AMSB:0] pc0;
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output reg [AMSB:0] pc0;
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output reg [AMSB:0] pc1;
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output reg [AMSB:0] pc1;
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output reg fetchbuf;
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output reg fetchbuf;
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output reg fetchbufA_v;
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output reg fetchbufA_v;
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output reg fetchbufB_v;
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output reg fetchbufB_v;
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output reg fetchbufC_v;
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output reg fetchbufC_v;
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output reg fetchbufD_v;
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output reg fetchbufD_v;
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output fetchbuf0_thrd;
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output fetchbuf0_thrd;
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output fetchbuf1_thrd;
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output fetchbuf1_thrd;
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output reg [47:0] fetchbufA_instr;
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output reg [47:0] fetchbufA_instr;
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output reg [47:0] fetchbufB_instr;
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output reg [47:0] fetchbufB_instr;
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output reg [47:0] fetchbufC_instr;
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output reg [47:0] fetchbufC_instr;
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output reg [47:0] fetchbufD_instr;
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output reg [47:0] fetchbufD_instr;
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output reg [AMSB:0] fetchbufA_pc;
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output reg [AMSB:0] fetchbufA_pc;
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output reg [AMSB:0] fetchbufB_pc;
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output reg [AMSB:0] fetchbufB_pc;
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output reg [AMSB:0] fetchbufC_pc;
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output reg [AMSB:0] fetchbufC_pc;
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output reg [AMSB:0] fetchbufD_pc;
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output reg [AMSB:0] fetchbufD_pc;
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output [47:0] fetchbuf0_instr;
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output [47:0] fetchbuf0_instr;
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output [47:0] fetchbuf1_instr;
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output [47:0] fetchbuf1_instr;
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output [AMSB:0] fetchbuf0_pc;
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output [AMSB:0] fetchbuf0_pc;
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output [AMSB:0] fetchbuf1_pc;
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output [AMSB:0] fetchbuf1_pc;
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output [2:0] fetchbuf0_insln;
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output [2:0] fetchbuf0_insln;
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output [2:0] fetchbuf1_insln;
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output [2:0] fetchbuf1_insln;
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output fetchbuf0_v;
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output fetchbuf0_v;
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output fetchbuf1_v;
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output fetchbuf1_v;
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input [47:0] codebuf0;
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input [47:0] codebuf0;
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input [47:0] codebuf1;
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input [47:0] codebuf1;
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input [AMSB:0] btgtA;
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input [AMSB:0] btgtA;
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input [AMSB:0] btgtB;
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input [AMSB:0] btgtB;
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input [AMSB:0] btgtC;
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input [AMSB:0] btgtC;
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input [AMSB:0] btgtD;
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input [AMSB:0] btgtD;
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input [3:0] nop_fetchbuf;
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input [3:0] nop_fetchbuf;
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output take_branch0;
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output take_branch0;
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output take_branch1;
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output take_branch1;
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input [3:0] stompedRets;
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input [3:0] stompedRets;
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output reg [3:0] panic;
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output reg [3:0] panic;
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integer n;
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integer n;
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//`include "FT64_decode.vh"
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//`include "FT64_decode.vh"
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function IsBranch;
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function IsBranch;
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input [47:0] isn;
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input [47:0] isn;
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casex(isn[`INSTRUCTION_OP])
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casex(isn[`INSTRUCTION_OP])
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`Bcc: IsBranch = TRUE;
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`Bcc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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default: IsBranch = FALSE;
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default: IsBranch = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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function IsJmp;
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function IsJmp;
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input [47:0] isn;
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input [47:0] isn;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP;
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endfunction
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endfunction
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function IsCall;
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function IsCall;
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input [47:0] isn;
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input [47:0] isn;
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IsCall = isn[`INSTRUCTION_OP]==`CALL;
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IsCall = isn[`INSTRUCTION_OP]==`CALL;
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endfunction
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endfunction
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function IsRet;
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function IsRet;
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input [47:0] isn;
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input [47:0] isn;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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endfunction
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endfunction
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function IsRTI;
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function IsRTI;
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input [47:0] isn;
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input [47:0] isn;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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endfunction
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endfunction
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function [2:0] fnInsLength;
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function [2:0] fnInsLength;
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input [47:0] ins;
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input [47:0] ins;
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`ifdef SUPPORT_DCI
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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fnInsLength = 3'd2;
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fnInsLength = 3'd2;
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else
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else
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`endif
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case(ins[7:6])
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case(ins[7:6])
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2'd0: fnInsLength = 3'd4;
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2'd0: fnInsLength = 3'd4;
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2'd1: fnInsLength = 3'd6;
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2'd1: fnInsLength = 3'd6;
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default: fnInsLength = 3'd2;
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default: fnInsLength = 3'd2;
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endcase
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endcase
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endfunction
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endfunction
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wire [2:0] fetchbufA_inslen;
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wire [2:0] fetchbufA_inslen;
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wire [2:0] fetchbufB_inslen;
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wire [2:0] fetchbufB_inslen;
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wire [2:0] fetchbufC_inslen;
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wire [2:0] fetchbufC_inslen;
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wire [2:0] fetchbufD_inslen;
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wire [2:0] fetchbufD_inslen;
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FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen);
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FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen);
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FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen);
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FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen);
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FT64_InsLength uilC (fetchbufC_instr, fetchbufC_inslen);
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FT64_InsLength uilC (fetchbufC_instr, fetchbufC_inslen);
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FT64_InsLength uilD (fetchbufD_instr, fetchbufD_inslen);
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FT64_InsLength uilD (fetchbufD_instr, fetchbufD_inslen);
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wire [47:0] xinsn0;
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wire [47:0] xinsn0;
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wire [47:0] xinsn1;
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wire [47:0] xinsn1;
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FT64_iexpander ux1
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FT64_iexpander ux1
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(
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(
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.cinstr(insn0[15:0]),
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.cinstr(insn0[15:0]),
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.expand(xinsn0)
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.expand(xinsn0)
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);
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);
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FT64_iexpander ux2
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FT64_iexpander ux2
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(
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(
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.cinstr(insn1[15:0]),
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.cinstr(insn1[15:0]),
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.expand(xinsn1)
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.expand(xinsn1)
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);
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);
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Table of decompressed instructions.
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// Table of decompressed instructions.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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assign ack_o = cs_i & cyc_i & stb_i;
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assign ack_o = cs_i & cyc_i & stb_i;
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`ifdef SUPPORT_DCI
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reg [47:0] DecompressTable [0:2047];
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reg [47:0] DecompressTable [0:2047];
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always @(posedge clk)
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always @(posedge clk)
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if (cs_i & cyc_i & stb_i & we_i)
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if (cs_i & cyc_i & stb_i & we_i)
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DecompressTable[adr_i[12:3]] <= dat_i[47:0];
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DecompressTable[adr_i[12:3]] <= dat_i[47:0];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,insn0[15:8]}];
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wire [47:0] expand0 = DecompressTable[{cmpgrp,insn0[15:8]}];
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wire [47:0] expand1 = DecompressTable[{cmpgrp,insn1[15:8]}];
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wire [47:0] expand1 = DecompressTable[{cmpgrp,insn1[15:8]}];
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`endif
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg thread;
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reg thread;
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reg stompedRet;
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reg stompedRet;
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reg ret0Counted, ret1Counted;
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reg ret0Counted, ret1Counted;
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wire [AMSB:0] retpc0, retpc1;
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wire [AMSB:0] retpc0, retpc1;
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reg did_branchback0;
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reg did_branchback0;
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reg did_branchback1;
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reg did_branchback1;
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assign predict_taken0 = (fetchbuf==1'b0) ? predict_takenA : predict_takenC;
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assign predict_taken0 = (fetchbuf==1'b0) ? predict_takenA : predict_takenC;
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assign predict_taken1 = (fetchbuf==1'b0) ? predict_takenB : predict_takenD;
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assign predict_taken1 = (fetchbuf==1'b0) ? predict_takenB : predict_takenD;
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reg [AMSB:0] branch_pcA;
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reg [AMSB:0] branch_pcA;
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reg [AMSB:0] branch_pcB;
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reg [AMSB:0] branch_pcB;
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reg [AMSB:0] branch_pcC;
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reg [AMSB:0] branch_pcC;
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reg [AMSB:0] branch_pcD;
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reg [AMSB:0] branch_pcD;
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always @*
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always @*
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case(fetchbufA_instr[`INSTRUCTION_OP])
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case(fetchbufA_instr[`INSTRUCTION_OP])
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`RET: branch_pcA = retpc0;
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`RET: branch_pcA = retpc0;
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`JMP,`CALL: branch_pcA = fetchbufA_instr[6] ? {fetchbufA_instr[39:8],1'b0} : {fetchbufA_pc[31:25],fetchbufA_instr[31:8],1'b0};
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`JMP,`CALL: branch_pcA = fetchbufA_instr[6] ? {fetchbufA_instr[39:8],1'b0} : {fetchbufA_pc[31:25],fetchbufA_instr[31:8],1'b0};
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`R2: branch_pcA = btgtA; // RTI
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`R2: branch_pcA = btgtA; // RTI
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`BRK,`JAL: branch_pcA = btgtA;
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`BRK,`JAL: branch_pcA = btgtA;
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default: branch_pcA = fetchbufA_pc + {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:21],1'b0} + fetchbufA_inslen;
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default: branch_pcA = fetchbufA_pc + {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:21],1'b0} + fetchbufA_inslen;
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endcase
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endcase
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always @*
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always @*
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case(fetchbufB_instr[`INSTRUCTION_OP])
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case(fetchbufB_instr[`INSTRUCTION_OP])
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`RET: branch_pcB = retpc1;
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`RET: branch_pcB = retpc1;
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`JMP,`CALL: branch_pcB = fetchbufB_instr[6] ? {fetchbufB_instr[39:8],1'b0} : {fetchbufB_pc[31:25],fetchbufB_instr[31:8],1'b0};
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`JMP,`CALL: branch_pcB = fetchbufB_instr[6] ? {fetchbufB_instr[39:8],1'b0} : {fetchbufB_pc[31:25],fetchbufB_instr[31:8],1'b0};
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`R2: branch_pcB = btgtB; // RTI
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`R2: branch_pcB = btgtB; // RTI
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`BRK,`JAL: branch_pcB = btgtB;
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`BRK,`JAL: branch_pcB = btgtB;
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default: branch_pcB = fetchbufB_pc + {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:21],1'b0} + fetchbufB_inslen;
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default: branch_pcB = fetchbufB_pc + {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:21],1'b0} + fetchbufB_inslen;
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endcase
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endcase
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|
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always @*
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always @*
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case(fetchbufC_instr[`INSTRUCTION_OP])
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case(fetchbufC_instr[`INSTRUCTION_OP])
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`RET: branch_pcC = retpc0;
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`RET: branch_pcC = retpc0;
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`JMP,`CALL: branch_pcC = fetchbufC_instr[6] ? {fetchbufC_instr[39:8],1'b0} : {fetchbufC_pc[31:25],fetchbufC_instr[31:8],1'b0};
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`JMP,`CALL: branch_pcC = fetchbufC_instr[6] ? {fetchbufC_instr[39:8],1'b0} : {fetchbufC_pc[31:25],fetchbufC_instr[31:8],1'b0};
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`R2: branch_pcC = btgtC; // RTI
|
`R2: branch_pcC = btgtC; // RTI
|
`BRK,`JAL: branch_pcC = btgtC;
|
`BRK,`JAL: branch_pcC = btgtC;
|
default: branch_pcC = fetchbufC_pc + {{20{fetchbufC_instr[31]}},fetchbufC_instr[31:21],1'b0} + fetchbufC_inslen;
|
default: branch_pcC = fetchbufC_pc + {{20{fetchbufC_instr[31]}},fetchbufC_instr[31:21],1'b0} + fetchbufC_inslen;
|
endcase
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endcase
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|
|
always @*
|
always @*
|
case(fetchbufD_instr[`INSTRUCTION_OP])
|
case(fetchbufD_instr[`INSTRUCTION_OP])
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`RET: branch_pcD = retpc1;
|
`RET: branch_pcD = retpc1;
|
`JMP,`CALL: branch_pcD = fetchbufD_instr[6] ? {fetchbufD_instr[39:8],1'b0} : {fetchbufD_pc[31:25],fetchbufD_instr[31:8],1'b0};
|
`JMP,`CALL: branch_pcD = fetchbufD_instr[6] ? {fetchbufD_instr[39:8],1'b0} : {fetchbufD_pc[31:25],fetchbufD_instr[31:8],1'b0};
|
`R2: branch_pcD = btgtD; // RTI
|
`R2: branch_pcD = btgtD; // RTI
|
`BRK,`JAL: branch_pcD = btgtD;
|
`BRK,`JAL: branch_pcD = btgtD;
|
default: branch_pcD = fetchbufD_pc + {{20{fetchbufD_instr[31]}},fetchbufD_instr[31:21],1'b0} + fetchbufD_inslen;
|
default: branch_pcD = fetchbufD_pc + {{20{fetchbufD_instr[31]}},fetchbufD_instr[31:21],1'b0} + fetchbufD_inslen;
|
endcase
|
endcase
|
|
|
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) ||
|
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) ||
|
((IsRet(fetchbufA_instr)||IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)||
|
((IsRet(fetchbufA_instr)||IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)||
|
IsRTI(fetchbufA_instr)|| fetchbufA_instr[`INSTRUCTION_OP]==`BRK || fetchbufA_instr[`INSTRUCTION_OP]==`JAL) &&
|
IsRTI(fetchbufA_instr)|| fetchbufA_instr[`INSTRUCTION_OP]==`BRK || fetchbufA_instr[`INSTRUCTION_OP]==`JAL) &&
|
fetchbufA_v);
|
fetchbufA_v);
|
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) ||
|
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) ||
|
((IsRet(fetchbufB_instr)|IsJmp(fetchbufB_instr)|IsCall(fetchbufB_instr) ||
|
((IsRet(fetchbufB_instr)|IsJmp(fetchbufB_instr)|IsCall(fetchbufB_instr) ||
|
IsRTI(fetchbufB_instr)|| fetchbufB_instr[`INSTRUCTION_OP]==`BRK || fetchbufB_instr[`INSTRUCTION_OP]==`JAL) &&
|
IsRTI(fetchbufB_instr)|| fetchbufB_instr[`INSTRUCTION_OP]==`BRK || fetchbufB_instr[`INSTRUCTION_OP]==`JAL) &&
|
fetchbufB_v);
|
fetchbufB_v);
|
wire take_branchC = ({fetchbufC_v, IsBranch(fetchbufC_instr), predict_takenC} == {`VAL, `TRUE, `TRUE}) ||
|
wire take_branchC = ({fetchbufC_v, IsBranch(fetchbufC_instr), predict_takenC} == {`VAL, `TRUE, `TRUE}) ||
|
((IsRet(fetchbufC_instr)|IsJmp(fetchbufC_instr)|IsCall(fetchbufC_instr) ||
|
((IsRet(fetchbufC_instr)|IsJmp(fetchbufC_instr)|IsCall(fetchbufC_instr) ||
|
IsRTI(fetchbufC_instr)|| fetchbufC_instr[`INSTRUCTION_OP]==`BRK || fetchbufC_instr[`INSTRUCTION_OP]==`JAL) &&
|
IsRTI(fetchbufC_instr)|| fetchbufC_instr[`INSTRUCTION_OP]==`BRK || fetchbufC_instr[`INSTRUCTION_OP]==`JAL) &&
|
fetchbufC_v);
|
fetchbufC_v);
|
wire take_branchD = ({fetchbufD_v, IsBranch(fetchbufD_instr), predict_takenD} == {`VAL, `TRUE, `TRUE}) ||
|
wire take_branchD = ({fetchbufD_v, IsBranch(fetchbufD_instr), predict_takenD} == {`VAL, `TRUE, `TRUE}) ||
|
((IsRet(fetchbufD_instr)|IsJmp(fetchbufD_instr)|IsCall(fetchbufD_instr) ||
|
((IsRet(fetchbufD_instr)|IsJmp(fetchbufD_instr)|IsCall(fetchbufD_instr) ||
|
IsRTI(fetchbufD_instr)|| fetchbufD_instr[`INSTRUCTION_OP]==`BRK || fetchbufD_instr[`INSTRUCTION_OP]==`JAL) &&
|
IsRTI(fetchbufD_instr)|| fetchbufD_instr[`INSTRUCTION_OP]==`BRK || fetchbufD_instr[`INSTRUCTION_OP]==`JAL) &&
|
fetchbufD_v);
|
fetchbufD_v);
|
|
|
assign take_branch0 = fetchbuf==1'b0 ? take_branchA : take_branchC;
|
assign take_branch0 = fetchbuf==1'b0 ? take_branchA : take_branchC;
|
assign take_branch1 = fetchbuf==1'b0 ? take_branchB : take_branchD;
|
assign take_branch1 = fetchbuf==1'b0 ? take_branchB : take_branchD;
|
wire take_branch = take_branch0 || take_branch1;
|
wire take_branch = take_branch0 || take_branch1;
|
/*
|
/*
|
always @*
|
always @*
|
begin
|
begin
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
|
end
|
end
|
*/
|
*/
|
assign threadx = fetchbuf;
|
assign threadx = fetchbuf;
|
|
|
`ifdef FCU_ENH
|
`ifdef FCU_ENH
|
FT64_RSB #(AMSB) ursb1
|
FT64_RSB #(AMSB) ursb1
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fcu_clk),
|
.clk(fcu_clk),
|
.regLR(regLR),
|
.regLR(regLR),
|
.queued1(queued1),
|
.queued1(queued1),
|
.queued2(queued2),
|
.queued2(queued2),
|
.fetchbuf0_v(fetchbuf0_v),
|
.fetchbuf0_v(fetchbuf0_v),
|
.fetchbuf0_pc(fetchbuf0_pc),
|
.fetchbuf0_pc(fetchbuf0_pc),
|
.fetchbuf0_instr(fetchbuf0_instr),
|
.fetchbuf0_instr(fetchbuf0_instr),
|
.fetchbuf1_v(fetchbuf1_v),
|
.fetchbuf1_v(fetchbuf1_v),
|
.fetchbuf1_pc(fetchbuf1_pc),
|
.fetchbuf1_pc(fetchbuf1_pc),
|
.fetchbuf1_instr(fetchbuf1_instr),
|
.fetchbuf1_instr(fetchbuf1_instr),
|
.stompedRets(stompedRets),
|
.stompedRets(stompedRets),
|
.stompedRet(stompedRet),
|
.stompedRet(stompedRet),
|
.pc(retpc0)
|
.pc(retpc0)
|
);
|
);
|
|
|
FT64_RSB #(AMSB) ursb2
|
FT64_RSB #(AMSB) ursb2
|
(
|
(
|
.rst(rst),
|
.rst(rst),
|
.clk(fcu_clk),
|
.clk(fcu_clk),
|
.regLR(regLR),
|
.regLR(regLR),
|
.queued1(queued1),
|
.queued1(queued1),
|
.queued2(1'b0),
|
.queued2(1'b0),
|
.fetchbuf0_v(fetchbuf1_v),
|
.fetchbuf0_v(fetchbuf1_v),
|
.fetchbuf0_pc(fetchbuf1_pc),
|
.fetchbuf0_pc(fetchbuf1_pc),
|
.fetchbuf0_instr(fetchbuf1_instr),
|
.fetchbuf0_instr(fetchbuf1_instr),
|
.fetchbuf1_v(1'b0),
|
.fetchbuf1_v(1'b0),
|
.fetchbuf1_pc(32'h00000000),
|
.fetchbuf1_pc(32'h00000000),
|
.fetchbuf1_instr(`NOP_INSN),
|
.fetchbuf1_instr(`NOP_INSN),
|
.stompedRets(stompedRets[3:1]),
|
.stompedRets(stompedRets[3:1]),
|
.stompedRet(stompedRet),
|
.stompedRet(stompedRet),
|
.pc(retpc1)
|
.pc(retpc1)
|
);
|
);
|
`else
|
`else
|
assign retpc0 = RSTPC;
|
assign retpc0 = RSTPC;
|
assign retpc1 = RSTPC;
|
assign retpc1 = RSTPC;
|
`endif
|
`endif
|
|
|
wire peclk, neclk;
|
wire peclk, neclk;
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst) begin
|
if (rst) begin
|
pc0 <= RSTPC;
|
pc0 <= RSTPC;
|
pc1 <= RSTPC;
|
pc1 <= RSTPC;
|
fetchbufA_v <= 0;
|
fetchbufA_v <= 0;
|
fetchbufB_v <= 0;
|
fetchbufB_v <= 0;
|
fetchbufC_v <= 0;
|
fetchbufC_v <= 0;
|
fetchbufD_v <= 0;
|
fetchbufD_v <= 0;
|
fetchbuf <= 0;
|
fetchbuf <= 0;
|
panic <= `PANIC_NONE;
|
panic <= `PANIC_NONE;
|
end
|
end
|
else begin
|
else begin
|
|
|
did_branchback0 <= take_branch0;
|
did_branchback0 <= take_branch0;
|
did_branchback1 <= take_branch1;
|
did_branchback1 <= take_branch1;
|
|
|
stompedRet = FALSE;
|
stompedRet = FALSE;
|
|
|
begin
|
begin
|
|
|
// On a branch miss with threading enabled all fectch buffers are
|
// On a branch miss with threading enabled all fectch buffers are
|
// invalidated even though the data in the fetch buffer would be valid
|
// invalidated even though the data in the fetch buffer would be valid
|
// for the thread that isn't in a branchmiss state. This is done to
|
// for the thread that isn't in a branchmiss state. This is done to
|
// keep things simple. For the thread that doesn't miss the current
|
// keep things simple. For the thread that doesn't miss the current
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
// data for the fetch buffer needs to be retrieved again, so the pc
|
// for that thread is assigned the current fetchbuf pc.
|
// for that thread is assigned the current fetchbuf pc.
|
// For the thread that misses the pc is simply assigned the misspc.
|
// For the thread that misses the pc is simply assigned the misspc.
|
if (branchmiss) begin
|
if (branchmiss) begin
|
$display("***********");
|
$display("***********");
|
$display("Branch miss");
|
$display("Branch miss");
|
$display("***********");
|
$display("***********");
|
if (branchmiss_thrd) begin
|
if (branchmiss_thrd) begin
|
pc0 <= fetchbuf0_pc;
|
pc0 <= fetchbuf0_pc;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
pc1 <= misspc;
|
pc1 <= misspc;
|
`endif
|
`endif
|
end
|
end
|
else begin
|
else begin
|
pc0 <= misspc;
|
pc0 <= misspc;
|
`ifdef SUPPORT_SMT
|
`ifdef SUPPORT_SMT
|
pc1 <= fetchbuf1_pc;
|
pc1 <= fetchbuf1_pc;
|
`endif
|
`endif
|
end
|
end
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbufC_v <= `INV;
|
fetchbufC_v <= `INV;
|
fetchbufD_v <= `INV;
|
fetchbufD_v <= `INV;
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("Branch miss");
|
$display("Branch miss");
|
$display("misspc=%h", misspc);
|
$display("misspc=%h", misspc);
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
$display("********************");
|
end
|
end
|
// Some of the testing for valid branch conditions has been removed. In real
|
// Some of the testing for valid branch conditions has been removed. In real
|
// hardware it isn't needed, and just increases the size of the core. It's
|
// hardware it isn't needed, and just increases the size of the core. It's
|
// assumed that the hardware is working.
|
// assumed that the hardware is working.
|
// The risk is an error will occur during simulation and go missed.
|
// The risk is an error will occur during simulation and go missed.
|
else if (take_branch) begin
|
else if (take_branch) begin
|
|
|
// update the fetchbuf valid bits as well as fetchbuf itself
|
// update the fetchbuf valid bits as well as fetchbuf itself
|
// ... this must be based on which things are backwards branches, how many things
|
// ... this must be based on which things are backwards branches, how many things
|
// will get enqueued (0, 1, or 2), and how old the instructions are
|
// will get enqueued (0, 1, or 2), and how old the instructions are
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v})
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, fetchbufC_v, fetchbufD_v})
|
|
|
4'b0000 : ; // do nothing
|
4'b0000 : ; // do nothing
|
// 4'b0001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0011 : panic <= `PANIC_INVALIDFBSTATE; // this looks like it might be screwy fetchbuf logic
|
// 4'b0011 : panic <= `PANIC_INVALIDFBSTATE; // this looks like it might be screwy fetchbuf logic
|
|
|
// because the first instruction has been enqueued,
|
// because the first instruction has been enqueued,
|
// we must have noted this in the previous cycle.
|
// we must have noted this in the previous cycle.
|
// therefore, pc0 and pc1 have to have been set appropriately ... so do a regular fetch
|
// therefore, pc0 and pc1 have to have been set appropriately ... so do a regular fetch
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a INSTR+BEQ, with fbB holding a branchback
|
// cycle 0 - fetched a INSTR+BEQ, with fbB holding a branchback
|
// cycle 1 - enqueued fbA, stomped on fbB, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued fbA, stomped on fbB, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufB_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufB_v appropriately
|
4'b0100 :
|
4'b0100 :
|
begin
|
begin
|
FetchCD();
|
FetchCD();
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// Can occur with threading enabled
|
// Can occur with threading enabled
|
4'b0101:
|
4'b0101:
|
fetchbufB_v <= !(queued1|queuedNop);
|
fetchbufB_v <= !(queued1|queuedNop);
|
|
|
// 4'b0101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0110 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0110 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched an INSTR+BEQ, with fbB holding a branchback
|
// cycle 0 - fetched an INSTR+BEQ, with fbB holding a branchback
|
// cycle 1 - enqueued fbA, but not fbB, recognized branchback in fbB, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued fbA, but not fbB, recognized branchback in fbB, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbB, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbB, but fetched from backwards target
|
// cycle 3 - where we are now ... update fetchbufB_v appropriately
|
// cycle 3 - where we are now ... update fetchbufB_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b0111 :
|
4'b0111 :
|
begin
|
begin
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a BEQ+INSTR, with fbA holding a branchback
|
// cycle 0 - fetched a BEQ+INSTR, with fbA holding a branchback
|
// cycle 1 - stomped on fbB, but could not enqueue fbA, stalled fetch + updated pc0/pc1
|
// cycle 1 - stomped on fbB, but could not enqueue fbA, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufA_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufA_v appropriately
|
4'b1000 :
|
4'b1000 :
|
begin
|
begin
|
FetchCD();
|
FetchCD();
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// 4'b1001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1010 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a BEQ+INSTR, with fbA holding a branchback
|
// cycle 0 - fetched a BEQ+INSTR, with fbA holding a branchback
|
// cycle 1 - stomped on fbB, but could not enqueue fbA, stalled fetch + updated pc0/pc1
|
// cycle 1 - stomped on fbB, but could not enqueue fbA, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbA, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbA, but fetched from backwards target
|
// cycle 3 - where we are now ... set fetchbufA_v appropriately
|
// cycle 3 - where we are now ... set fetchbufA_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b1011 :
|
4'b1011 :
|
begin
|
begin
|
fetchbufA_v <=!(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <=!(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// if fbB has the branchback, can't immediately tell which of the following scenarios it is:
|
// if fbB has the branchback, can't immediately tell which of the following scenarios it is:
|
// cycle 0 - fetched a pair of instructions, one or both of which is a branchback
|
// cycle 0 - fetched a pair of instructions, one or both of which is a branchback
|
// cycle 1 - where we are now. stomp, enqueue, and update pc0/pc1
|
// cycle 1 - where we are now. stomp, enqueue, and update pc0/pc1
|
// or
|
// or
|
// cycle 0 - fetched a INSTR+BEQ, with fbB holding a branchback
|
// cycle 0 - fetched a INSTR+BEQ, with fbB holding a branchback
|
// cycle 1 - could not enqueue fbA or fbB, stalled fetch + updated pc0/pc1
|
// cycle 1 - could not enqueue fbA or fbB, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
|
// if fbA has the branchback, then it is scenario 1.
|
// if fbA has the branchback, then it is scenario 1.
|
// if fbB has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
|
// if fbB has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
|
4'b1100:
|
4'b1100:
|
if (thread_en) begin
|
if (thread_en) begin
|
if (take_branchA && take_branchB) begin
|
if (take_branchA && take_branchB) begin
|
pc0 <= branch_pcA;
|
pc0 <= branch_pcA;
|
pc1 <= branch_pcB;
|
pc1 <= branch_pcB;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else if (take_branchA) begin
|
else if (take_branchA) begin
|
pc0 <= branch_pcA;
|
pc0 <= branch_pcA;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else if (take_branchB) begin
|
else if (take_branchB) begin
|
pc1 <= branch_pcB;
|
pc1 <= branch_pcB;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (take_branchA) begin
|
if (take_branchA) begin
|
pc0 <= branch_pcA;
|
pc0 <= branch_pcA;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (did_branchback0) begin
|
if (did_branchback0) begin
|
FetchCD();
|
FetchCD();
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + ((queued2|queuedNop));
|
fetchbuf <= fetchbuf + ((queued2|queuedNop));
|
end
|
end
|
else begin
|
else begin
|
pc0 <= branch_pcB;
|
pc0 <= branch_pcB;
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1110 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1110 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched an INSTR+BEQ, with fbB holding a branchback
|
// cycle 0 - fetched an INSTR+BEQ, with fbB holding a branchback
|
// cycle 1 - enqueued neither fbA nor fbB, recognized branchback in fbB, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued neither fbA nor fbB, recognized branchback in fbB, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbB, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbB, but fetched from backwards target
|
// cycle 3 - where we are now ... update fetchbufX_v appropriately
|
// cycle 3 - where we are now ... update fetchbufX_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b1111 :
|
4'b1111 :
|
begin
|
begin
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufA_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufB_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
else case ({fetchbufC_v, fetchbufD_v, fetchbufA_v, fetchbufB_v})
|
else case ({fetchbufC_v, fetchbufD_v, fetchbufA_v, fetchbufB_v})
|
|
|
4'b0000 : ; // do nothing
|
4'b0000 : ; // do nothing
|
// 4'b0001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0011 : panic <= `PANIC_INVALIDFBSTATE; // this looks like it might be screwy fetchbuf logic
|
// 4'b0011 : panic <= `PANIC_INVALIDFBSTATE; // this looks like it might be screwy fetchbuf logic
|
|
|
// because the first instruction has been enqueued,
|
// because the first instruction has been enqueued,
|
// we must have noted this in the previous cycle.
|
// we must have noted this in the previous cycle.
|
// therefore, pc0 and pc1 have to have been set appropriately ... so do a regular fetch
|
// therefore, pc0 and pc1 have to have been set appropriately ... so do a regular fetch
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a INSTR+BEQ, with fbD holding a branchback
|
// cycle 0 - fetched a INSTR+BEQ, with fbD holding a branchback
|
// cycle 1 - enqueued fbC, stomped on fbD, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued fbC, stomped on fbD, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufB_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufB_v appropriately
|
4'b0100 :
|
4'b0100 :
|
begin
|
begin
|
FetchAB();
|
FetchAB();
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
4'b0101:
|
4'b0101:
|
fetchbufD_v <= !(queued1|queuedNop);
|
fetchbufD_v <= !(queued1|queuedNop);
|
|
|
// 4'b0101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0110 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b0110 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched an INSTR+BEQ, with fbD holding a branchback
|
// cycle 0 - fetched an INSTR+BEQ, with fbD holding a branchback
|
// cycle 1 - enqueued fbC, but not fbD, recognized branchback in fbD, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued fbC, but not fbD, recognized branchback in fbD, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbD, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbD, but fetched from backwards target
|
// cycle 3 - where we are now ... update fetchbufD_v appropriately
|
// cycle 3 - where we are now ... update fetchbufD_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b0111 :
|
4'b0111 :
|
begin
|
begin
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a BEQ+INSTR, with fbC holding a branchback
|
// cycle 0 - fetched a BEQ+INSTR, with fbC holding a branchback
|
// cycle 1 - stomped on fbD, but could not enqueue fbC, stalled fetch + updated pc0/pc1
|
// cycle 1 - stomped on fbD, but could not enqueue fbC, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufC_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufC_v appropriately
|
4'b1000 :
|
4'b1000 :
|
begin
|
begin
|
FetchAB();
|
FetchAB();
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// 4'b1001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1001 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1010 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1010 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched a BEQ+INSTR, with fbC holding a branchback
|
// cycle 0 - fetched a BEQ+INSTR, with fbC holding a branchback
|
// cycle 1 - stomped on fbD, but could not enqueue fbC, stalled fetch + updated pc0/pc1
|
// cycle 1 - stomped on fbD, but could not enqueue fbC, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbC, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbC, but fetched from backwards target
|
// cycle 3 - where we are now ... set fetchbufC_v appropriately
|
// cycle 3 - where we are now ... set fetchbufC_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b1011 :
|
4'b1011 :
|
begin
|
begin
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
fetchbuf <= fetchbuf + (queued1|queuedNop);
|
end
|
end
|
|
|
// if fbD has the branchback, can't immediately tell which of the following scenarios it is:
|
// if fbD has the branchback, can't immediately tell which of the following scenarios it is:
|
// cycle 0 - fetched a pair of instructions, one or both of which is a branchback
|
// cycle 0 - fetched a pair of instructions, one or both of which is a branchback
|
// cycle 1 - where we are now. stomp, enqueue, and update pc0/pc1
|
// cycle 1 - where we are now. stomp, enqueue, and update pc0/pc1
|
// or
|
// or
|
// cycle 0 - fetched a INSTR+BEQ, with fbD holding a branchback
|
// cycle 0 - fetched a INSTR+BEQ, with fbD holding a branchback
|
// cycle 1 - could not enqueue fbC or fbD, stalled fetch + updated pc0/pc1
|
// cycle 1 - could not enqueue fbC or fbD, stalled fetch + updated pc0/pc1
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
|
// cycle 2 - where we are now ... fetch the two instructions & update fetchbufX_v appropriately
|
// if fbC has the branchback, then it is scenario 1.
|
// if fbC has the branchback, then it is scenario 1.
|
// if fbD has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
|
// if fbD has it: if pc0 == fbB_pc, then it is the former scenario, else it is the latter
|
4'b1100:
|
4'b1100:
|
if (thread_en) begin
|
if (thread_en) begin
|
if (take_branchC && take_branchD) begin
|
if (take_branchC && take_branchD) begin
|
pc0 <= branch_pcC;
|
pc0 <= branch_pcC;
|
pc1 <= branch_pcD;
|
pc1 <= branch_pcD;
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else if (take_branchC) begin
|
else if (take_branchC) begin
|
pc0 <= branch_pcC;
|
pc0 <= branch_pcC;
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else if (take_branchD) begin
|
else if (take_branchD) begin
|
pc1 <= branch_pcD;
|
pc1 <= branch_pcD;
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (take_branchC) begin
|
if (take_branchC) begin
|
pc0 <= branch_pcC;
|
pc0 <= branch_pcC;
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= `INV;
|
fetchbufD_v <= `INV;
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued1|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (did_branchback1) begin
|
if (did_branchback1) begin
|
FetchAB();
|
FetchAB();
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + ((queued2|queuedNop));
|
fetchbuf <= fetchbuf + ((queued2|queuedNop));
|
end
|
end
|
else begin
|
else begin
|
pc0 <= branch_pcD;
|
pc0 <= branch_pcD;
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
if ((queued2|queuedNop)) fetchbuf <= 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1101 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1110 : panic <= `PANIC_INVALIDFBSTATE;
|
// 4'b1110 : panic <= `PANIC_INVALIDFBSTATE;
|
|
|
// this looks like the following:
|
// this looks like the following:
|
// cycle 0 - fetched an INSTR+BEQ, with fbD holding a branchback
|
// cycle 0 - fetched an INSTR+BEQ, with fbD holding a branchback
|
// cycle 1 - enqueued neither fbC nor fbD, recognized branchback in fbD, stalled fetch + updated pc0/pc1
|
// cycle 1 - enqueued neither fbC nor fbD, recognized branchback in fbD, stalled fetch + updated pc0/pc1
|
// cycle 2 - still could not enqueue fbD, but fetched from backwards target
|
// cycle 2 - still could not enqueue fbD, but fetched from backwards target
|
// cycle 3 - where we are now ... update fetchbufX_v appropriately
|
// cycle 3 - where we are now ... update fetchbufX_v appropriately
|
//
|
//
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// however -- if there are backwards branches in the latter two slots, it is more complex.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
// simple solution: leave it alone and wait until we are through with the first two slots.
|
4'b1111 :
|
4'b1111 :
|
begin
|
begin
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufC_v <= !(queued1|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbufD_v <= !(queued2|queuedNop); // if it can be queued, it will
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
fetchbuf <= fetchbuf + (queued2|queuedNop);
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
end // if branchback
|
end // if branchback
|
|
|
else begin // there is no branchback in the system
|
else begin // there is no branchback in the system
|
//
|
//
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
// update fetchbufX_v and fetchbuf ... relatively simple, as
|
// there are no backwards branches in the mix
|
// there are no backwards branches in the mix
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, (queued1|queuedNop), (queued2|queuedNop)})
|
if (fetchbuf == 1'b0) case ({fetchbufA_v, fetchbufB_v, (queued1|queuedNop), (queued2|queuedNop)})
|
4'b00_00 : ; // do nothing
|
4'b00_00 : ; // do nothing
|
// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
|
4'b00_10 : ; // do nothing
|
4'b00_10 : ; // do nothing
|
4'b00_11 : ; // do nothing
|
4'b00_11 : ; // do nothing
|
4'b01_00 : ; // do nothing
|
4'b01_00 : ; // do nothing
|
// 4'b01_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b01_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b01_10,
|
4'b01_10,
|
4'b01_11 : begin // enqueue fbB and flip fetchbuf
|
4'b01_11 : begin // enqueue fbB and flip fetchbuf
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
|
|
4'b10_00 : ; // do nothing
|
4'b10_00 : ; // do nothing
|
// 4'b10_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b10_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b10_10,
|
4'b10_10,
|
4'b10_11 : begin // enqueue fbA and flip fetchbuf
|
4'b10_11 : begin // enqueue fbA and flip fetchbuf
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
|
|
4'b11_00 : ; // do nothing
|
4'b11_00 : ; // do nothing
|
// 4'b11_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b11_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b11_10 : begin // enqueue fbA but leave fetchbuf
|
4'b11_10 : begin // enqueue fbA but leave fetchbuf
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
end
|
end
|
|
|
4'b11_11 : begin // enqueue both and flip fetchbuf
|
4'b11_11 : begin // enqueue both and flip fetchbuf
|
fetchbufA_v <= `INV;
|
fetchbufA_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbufB_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
endcase
|
endcase
|
else case ({fetchbufC_v, fetchbufD_v, (queued1|queuedNop), (queued2|queuedNop)})
|
else case ({fetchbufC_v, fetchbufD_v, (queued1|queuedNop), (queued2|queuedNop)})
|
4'b00_00 : ; // do nothing
|
4'b00_00 : ; // do nothing
|
// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b00_01 : panic <= `PANIC_INVALIDIQSTATE;
|
4'b00_10 : ; // do nothing
|
4'b00_10 : ; // do nothing
|
4'b00_11 : ; // do nothing
|
4'b00_11 : ; // do nothing
|
4'b01_00 : ; // do nothing
|
4'b01_00 : ; // do nothing
|
// 4'b01_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b01_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b01_10,
|
4'b01_10,
|
4'b01_11 : begin // enqueue fbD and flip fetchbuf
|
4'b01_11 : begin // enqueue fbD and flip fetchbuf
|
fetchbufD_v <= `INV;
|
fetchbufD_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
|
|
4'b10_00 : ; // do nothing
|
4'b10_00 : ; // do nothing
|
// 4'b10_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b10_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b10_10,
|
4'b10_10,
|
4'b10_11 : begin // enqueue fbC and flip fetchbuf
|
4'b10_11 : begin // enqueue fbC and flip fetchbuf
|
fetchbufC_v <= `INV;
|
fetchbufC_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
|
|
4'b11_00 : ; // do nothing
|
4'b11_00 : ; // do nothing
|
// 4'b11_01 : panic <= `PANIC_INVALIDIQSTATE;
|
// 4'b11_01 : panic <= `PANIC_INVALIDIQSTATE;
|
|
|
4'b11_10 : begin // enqueue fbC but leave fetchbuf
|
4'b11_10 : begin // enqueue fbC but leave fetchbuf
|
fetchbufC_v <= `INV;
|
fetchbufC_v <= `INV;
|
end
|
end
|
|
|
4'b11_11 : begin // enqueue both and flip fetchbuf
|
4'b11_11 : begin // enqueue both and flip fetchbuf
|
fetchbufC_v <= `INV;
|
fetchbufC_v <= `INV;
|
fetchbufD_v <= `INV;
|
fetchbufD_v <= `INV;
|
fetchbuf <= ~fetchbuf;
|
fetchbuf <= ~fetchbuf;
|
end
|
end
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
default: panic <= `PANIC_INVALIDIQSTATE;
|
endcase
|
endcase
|
//
|
//
|
// get data iff the fetch buffers are empty
|
// get data iff the fetch buffers are empty
|
//
|
//
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
|
FetchAB();
|
FetchAB();
|
// fetchbuf steering logic correction
|
// fetchbuf steering logic correction
|
if (fetchbufC_v==`INV && fetchbufD_v==`INV && phit)
|
if (fetchbufC_v==`INV && fetchbufD_v==`INV && phit)
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
end
|
end
|
else if (fetchbufC_v == `INV && fetchbufD_v == `INV)
|
else if (fetchbufC_v == `INV && fetchbufD_v == `INV)
|
FetchCD();
|
FetchCD();
|
end
|
end
|
//
|
//
|
// get data iff the fetch buffers are empty
|
// get data iff the fetch buffers are empty
|
//
|
//
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV && fetchbufC_v==`INV && fetchbufD_v==`INV) begin
|
if (fetchbufA_v == `INV && fetchbufB_v == `INV && fetchbufC_v==`INV && fetchbufD_v==`INV) begin
|
FetchAB();
|
FetchAB();
|
fetchbuf <= 1'b0;
|
fetchbuf <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
// The fetchbuffer is invalidated at the end of a vector instruction
|
// queue.
|
// queue.
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
|
if (nop_fetchbuf[2]) fetchbufC_v <= `INV;
|
if (nop_fetchbuf[2]) fetchbufC_v <= `INV;
|
if (nop_fetchbuf[3]) fetchbufD_v <= `INV;
|
if (nop_fetchbuf[3]) fetchbufD_v <= `INV;
|
end
|
end
|
|
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufC_instr;
|
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufC_instr;
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufC_inslen;
|
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufC_inslen;
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufC_v ;
|
assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufC_v ;
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufC_pc ;
|
assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufC_pc ;
|
assign fetchbuf1_instr = (fetchbuf == 1'b0) ? fetchbufB_instr : fetchbufD_instr;
|
assign fetchbuf1_instr = (fetchbuf == 1'b0) ? fetchbufB_instr : fetchbufD_instr;
|
assign fetchbuf1_insln = (fetchbuf == 1'b0) ? fetchbufB_inslen: fetchbufD_inslen;
|
assign fetchbuf1_insln = (fetchbuf == 1'b0) ? fetchbufB_inslen: fetchbufD_inslen;
|
assign fetchbuf1_v = (fetchbuf == 1'b0) ? fetchbufB_v : fetchbufD_v ;
|
assign fetchbuf1_v = (fetchbuf == 1'b0) ? fetchbufB_v : fetchbufD_v ;
|
assign fetchbuf1_pc = (fetchbuf == 1'b0) ? fetchbufB_pc : fetchbufD_pc ;
|
assign fetchbuf1_pc = (fetchbuf == 1'b0) ? fetchbufB_pc : fetchbufD_pc ;
|
assign fetchbuf0_thrd = 1'b0;
|
assign fetchbuf0_thrd = 1'b0;
|
assign fetchbuf1_thrd = thread_en;
|
assign fetchbuf1_thrd = thread_en;
|
|
|
reg [2:0] insln0, insln1;
|
reg [2:0] insln0, insln1;
|
always @*
|
always @*
|
begin
|
begin
|
|
`ifdef SUPPORT_DCI
|
if (insn0[5:0]==`CMPRSSD)
|
if (insn0[5:0]==`CMPRSSD)
|
insln0 <= 3'd2;
|
insln0 <= 3'd2;
|
else if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
else
|
|
`endif
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
insln0 <= fnInsLength(codebuf0);
|
insln0 <= fnInsLength(codebuf0);
|
else
|
else
|
insln0 <= fnInsLength(insn0);
|
insln0 <= fnInsLength(insn0);
|
end
|
end
|
|
|
always @*
|
always @*
|
begin
|
begin
|
|
`ifdef SUPPORT_DCI
|
if (insn1[5:0]==`CMPRSSD)
|
if (insn1[5:0]==`CMPRSSD)
|
insln1 <= 3'd2;
|
insln1 <= 3'd2;
|
else if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
else
|
|
`endif
|
|
if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
insln1 <= fnInsLength(codebuf1);
|
insln1 <= fnInsLength(codebuf1);
|
else
|
else
|
insln1 <= fnInsLength(insn1);
|
insln1 <= fnInsLength(insn1);
|
end
|
end
|
|
|
reg [47:0] cinsn0, cinsn1;
|
reg [47:0] cinsn0, cinsn1;
|
|
|
always @*
|
always @*
|
begin
|
begin
|
|
`ifdef SUPPORT_DCI
|
if (insn0[5:0]==`CMPRSSD)
|
if (insn0[5:0]==`CMPRSSD)
|
cinsn0 <= expand0;
|
cinsn0 <= expand0;
|
else if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
else
|
|
`endif
|
|
if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
|
cinsn0 <= codebuf0;
|
cinsn0 <= codebuf0;
|
else if (insn0[7])
|
else if (insn0[7])
|
cinsn0 <= xinsn0;
|
cinsn0 <= xinsn0;
|
else
|
else
|
cinsn0 <= insn0;
|
cinsn0 <= insn0;
|
end
|
end
|
|
|
always @*
|
always @*
|
begin
|
begin
|
|
`ifdef SUPPORT_DCI
|
if (insn1[5:0]==`CMPRSSD)
|
if (insn1[5:0]==`CMPRSSD)
|
cinsn1 <= expand1;
|
cinsn1 <= expand1;
|
else if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
else
|
|
`endif
|
|
if (insn1[7:6]==2'b00 && insn1[`INSTRUCTION_OP]==`EXEC)
|
cinsn1 <= codebuf1;
|
cinsn1 <= codebuf1;
|
else if (insn1[7])
|
else if (insn1[7])
|
cinsn1 <= xinsn1;
|
cinsn1 <= xinsn1;
|
else
|
else
|
cinsn1 <= insn1;
|
cinsn1 <= insn1;
|
end
|
end
|
|
|
task FetchA;
|
task FetchA;
|
begin
|
begin
|
fetchbufA_instr <= cinsn0;
|
fetchbufA_instr <= cinsn0;
|
fetchbufA_v <= `VAL;
|
fetchbufA_v <= `VAL;
|
fetchbufA_pc <= pc0;
|
fetchbufA_pc <= pc0;
|
if (phit && ~freezePC) begin
|
if (phit && ~freezePC) begin
|
if (thread_en)
|
if (thread_en)
|
pc0 <= pc0 + insln0;
|
pc0 <= pc0 + insln0;
|
else if (`WAYS > 1)
|
else if (`WAYS > 1)
|
pc0 <= pc0 + insln0 + insln1;
|
pc0 <= pc0 + insln0 + insln1;
|
else
|
else
|
pc0 <= pc0 + insln0;
|
pc0 <= pc0 + insln0;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task FetchB;
|
task FetchB;
|
begin
|
begin
|
fetchbufB_instr <= cinsn1;
|
fetchbufB_instr <= cinsn1;
|
fetchbufB_v <= `WAYS > 1;
|
fetchbufB_v <= `WAYS > 1;
|
if (thread_en)
|
if (thread_en)
|
fetchbufB_pc <= pc1;
|
fetchbufB_pc <= pc1;
|
else
|
else
|
fetchbufB_pc <= pc0 + insln0;
|
fetchbufB_pc <= pc0 + insln0;
|
if (phit & thread_en)
|
if (phit & thread_en)
|
pc1 <= pc1 + insln1;
|
pc1 <= pc1 + insln1;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task FetchAB;
|
task FetchAB;
|
begin
|
begin
|
FetchA();
|
FetchA();
|
FetchB();
|
FetchB();
|
end
|
end
|
endtask
|
endtask
|
|
|
task FetchC;
|
task FetchC;
|
begin
|
begin
|
fetchbufC_instr <= cinsn0;
|
fetchbufC_instr <= cinsn0;
|
fetchbufC_v <= `VAL;
|
fetchbufC_v <= `VAL;
|
fetchbufC_pc <= pc0;
|
fetchbufC_pc <= pc0;
|
if (phit && ~freezePC) begin
|
if (phit && ~freezePC) begin
|
if (thread_en)
|
if (thread_en)
|
pc0 <= pc0 + insln0;
|
pc0 <= pc0 + insln0;
|
else if (`WAYS > 1)
|
else if (`WAYS > 1)
|
pc0 <= pc0 + insln0 + insln1;
|
pc0 <= pc0 + insln0 + insln1;
|
else
|
else
|
pc0 <= pc0 + insln0;
|
pc0 <= pc0 + insln0;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task FetchD;
|
task FetchD;
|
begin
|
begin
|
fetchbufD_instr <= cinsn1;
|
fetchbufD_instr <= cinsn1;
|
fetchbufD_v <= `WAYS > 1;
|
fetchbufD_v <= `WAYS > 1;
|
if (thread_en)
|
if (thread_en)
|
fetchbufD_pc <= pc1;
|
fetchbufD_pc <= pc1;
|
else
|
else
|
fetchbufD_pc <= pc0 + insln0;
|
fetchbufD_pc <= pc0 + insln0;
|
if (phit & thread_en)
|
if (phit & thread_en)
|
pc1 <= pc1 + insln1;
|
pc1 <= pc1 + insln1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task FetchCD;
|
task FetchCD;
|
begin
|
begin
|
FetchC();
|
FetchC();
|
FetchD();
|
FetchD();
|
end
|
end
|
endtask
|
endtask
|
|
|
endmodule
|
endmodule
|
|
|
|
|