`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2012-2013 Robert Finch, Stratford
|
// \\__/ o\ (C) 2012-2013 Robert Finch, Stratford
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@opencores.org
|
// \/_// robfinch<remove>@opencores.org
|
// ||
|
// ||
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
// (at your option) any later version.
|
// (at your option) any later version.
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// This source file is distributed in the hope that it will be useful,
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
module bootrom(rst_i, clk_i, cti_i, cyc_i, stb_i, ack_o, adr_i, dat_o, perr);
|
module bootrom(rst_i, clk_i, cti_i, cyc_i, stb_i, ack_o, adr_i, dat_o, perr, err1, err2);
|
parameter DBW=64;
|
parameter DBW=64;
|
parameter MAGIC1=32'hAAAAAAAA;
|
parameter MAGIC1=32'hAAAAAAAA;
|
parameter MAGIC2=32'h55555555;
|
parameter MAGIC2=32'h55555555;
|
input rst_i;
|
input rst_i;
|
input clk_i;
|
input clk_i;
|
input [2:0] cti_i;
|
input [2:0] cti_i;
|
input cyc_i;
|
input cyc_i;
|
input stb_i;
|
input stb_i;
|
output ack_o;
|
output ack_o;
|
input [31:0] adr_i;
|
input [31:0] adr_i;
|
output [DBW-1:0] dat_o;
|
output [DBW+6:0] dat_o;
|
reg [DBW-1:0] dat_o;
|
reg [DBW+6:0] dat_o;
|
output perr;
|
output perr;
|
reg perr;
|
output err1;
|
|
output err2;
|
|
|
wire ne_cs;
|
wire ne_cs;
|
wire cs;
|
wire cs;
|
reg ack0,ack1,ack2,ack3;
|
reg ack0,ack1,ack2,ack3;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
begin
|
begin
|
if (ne_cs)
|
if (ne_cs)
|
ack0 <= cs;
|
ack0 <= cs;
|
else if (!cs)
|
else if (!cs)
|
ack0 <= 1'b0;
|
ack0 <= 1'b0;
|
ack1 <= ack0 & cs;
|
ack1 <= ack0 & cs;
|
ack2 <= ack1 & cs;
|
ack2 <= ack1 & cs;
|
ack3 <= ack2 & cs;
|
ack3 <= ack2 & cs;
|
end
|
end
|
assign cs = cyc_i && stb_i && adr_i[31:16]==16'hFFFF;
|
assign cs = cyc_i && stb_i && adr_i[31:20]==12'hFFF;
|
assign ack_o = cs & ack0;
|
assign ack_o = cs & ack0;
|
|
|
reg [DBW:0] rommem0 [0:8191];
|
reg [38:0] rommem0 [0:25599];
|
reg [DBW:0] rommem1 [0:8191];
|
//reg [DBW-1:0] rommem1 [0:7167];
|
reg [DBW:0] rommem2 [0:8191];
|
//reg [DBW-1:0] rommem2 [0:7167];
|
initial begin
|
initial begin
|
if (DBW==32) begin
|
if (DBW==32) begin
|
`include "..\..\software\A64\bin\boot.ve0"
|
`include "..\..\software\source\boot.ve0"
|
`include "..\..\software\A64\bin\boot.ve1"
|
//`include "..\..\software\A64\bin\boot.ve1"
|
`include "..\..\software\A64\bin\boot.ve2"
|
//`include "..\..\software\A64\bin\boot.ve2"
|
end
|
end
|
else begin
|
else begin
|
`include "..\..\software\a64\bin\boot.ve0"
|
`include "..\..\software\source\boot.ve0"
|
`include "..\..\software\A64\bin\boot.ve1"
|
//`include "..\..\software\A64\bin\boot.ve1"
|
`include "..\..\software\A64\bin\boot.ve2"
|
//`include "..\..\software\A64\bin\boot.ve2"
|
end
|
end
|
end
|
end
|
|
|
wire pe_cs;
|
wire pe_cs;
|
edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee());
|
edge_det u1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee());
|
edge_det u2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(pe_cs), .pe(), .ne(ne_cs), .ee());
|
edge_det u2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(pe_cs), .pe(), .ne(ne_cs), .ee());
|
|
|
reg [14:2] radr;
|
reg [14:2] radr;
|
reg [14:2] ctr;
|
reg [14:2] ctr;
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (pe_cs) begin
|
if (pe_cs) begin
|
if (DBW==32)
|
if (DBW==32)
|
ctr <= adr_i[14:2] + 13'd1;
|
ctr <= adr_i[14:2] + 13'd1;
|
else
|
else
|
ctr <= adr_i[14:3] + 13'd1;
|
ctr <= adr_i[14:3] + 13'd1;
|
end
|
end
|
else if (cs)
|
else if (cs)
|
ctr <= ctr + 13'd1;
|
ctr <= ctr + 13'd1;
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (DBW==32)
|
if (DBW==32)
|
radr <= pe_cs ? adr_i[14:2] : ctr;
|
radr <= pe_cs ? adr_i[14:2] : ctr;
|
else
|
else
|
radr <= pe_cs ? adr_i[14:3] : ctr;
|
radr <= pe_cs ? adr_i[14:3] : ctr;
|
|
|
wire [31:0] d0 = rommem0[radr][DBW-1:0];
|
wire [38:0] d0 = rommem0[radr];
|
wire [31:0] d1 = rommem1[radr][DBW-1:0]^MAGIC1;
|
//wire [31:0] d1 = rommem1[radr][DBW-1:0]^MAGIC1;
|
wire [31:0] d2 = rommem2[radr][DBW-1:0]^MAGIC2;
|
//wire [31:0] d2 = rommem2[radr][DBW-1:0]^MAGIC2;
|
wire [31:0] d4 = (d0&d1)|(d0&d2)|(d1&d2);
|
wire [31:0] d4;//(d0&d1)|(d0&d2)|(d1&d2);
|
|
|
|
//ECC ecc1(d0,d4);
|
|
ecc_0 uecc1 (
|
|
.ecc_correct_n(1'b0), // input wire ecc_correct_n
|
|
.ecc_data_in(d0[31:0]), // input wire [31 : 0] ecc_data_in
|
|
.ecc_data_out(d4), // output wire [31 : 0] ecc_data_out
|
|
.ecc_chkbits_in({d0[37:32],d0[38]}), // input wire [6 : 0] ecc_chkbits_in
|
|
.ecc_sbit_err(err1), // output wire ecc_sbit_err
|
|
.ecc_dbit_err(err2) // output wire ecc_dbit_err
|
|
);
|
|
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (cs) begin
|
if (cs) begin
|
dat_o <= d4;
|
dat_o <= {d0[38:32],d4};
|
$display("br read: %h %h", radr,d4);
|
$display("br read: %h %h", radr,d4);
|
end
|
end
|
else
|
else
|
dat_o <= {DBW{1'b0}};
|
dat_o <= {DBW+6{1'b0}};
|
|
|
always @(posedge clk_i)
|
/*
|
if (cs)
|
always @(posedge clk_i)
|
perr <= ^rommem0[radr][DBW-1:0]!=rommem0[radr][DBW];
|
if (cs)
|
else
|
perr <= ^rommem0[radr][DBW-1:0]!=rommem0[radr][DBW];
|
perr <= 1'd0;
|
else
|
|
perr <= 1'd0;
|
|
*/
|
|
assign perr = 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|
