`include "Thor_defines.v"
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`include "Thor_defines.v"
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2011,2012,2013 Robert Finch
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// \\__/ o\ (C) 2011,2012,2013 Robert Finch
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// Thor_TLB.v
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// Thor_TLB.v
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// TLB
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// TLB
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// The TLB contains 64 entries, that are 8 way set associative.
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// The TLB contains 64 entries, that are 8 way set associative.
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// The TLB is dual ported and shared between the instruction and data streams.
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// The TLB is dual ported and shared between the instruction and data streams.
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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`define TLBMissPage {DBW-12{1'b1}}
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`define TLBMissPage {DBW-12{1'b1}}
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module Thor_TLB(rst, clk, km, pc, ea, ppc, pea,
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module Thor_TLB(rst, clk, km, pc, ea, ppc, pea,
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iuncached, uncached,
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iuncached, uncached,
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m1IsStore, ASID, state, op, regno, dati, dato,
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m1IsStore, ASID, state, op, regno, dati, dato,
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ITLBMiss, DTLBMiss, HTLBVirtPageo);
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ITLBMiss, DTLBMiss, HTLBVirtPageo);
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parameter DBW=64;
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parameter DBW=64;
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input rst;
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input rst;
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input clk;
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input clk;
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input km; // kernel mode
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input km; // kernel mode
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input [DBW-1:0] pc;
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input [DBW-1:0] pc;
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input [DBW-1:0] ea;
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input [DBW-1:0] ea;
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output reg [DBW-1:0] ppc;
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output reg [DBW-1:0] ppc;
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output reg [DBW-1:0] pea;
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output reg [DBW-1:0] pea;
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output iuncached;
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output iuncached;
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output uncached;
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output uncached;
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input m1IsStore;
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input m1IsStore;
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input [7:0] ASID;
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input [7:0] ASID;
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input [2:0] state;
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input [2:0] state;
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input [3:0] op;
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input [3:0] op;
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input [3:0] regno;
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input [3:0] regno;
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input [DBW-1:0] dati;
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input [DBW-1:0] dati;
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output [DBW-1:0] dato;
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output [DBW-1:0] dato;
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reg [DBW-1:0] dato;
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reg [DBW-1:0] dato;
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output ITLBMiss;
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output ITLBMiss;
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output DTLBMiss;
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output DTLBMiss;
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output [DBW-1:0] HTLBVirtPageo;
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output [DBW-1:0] HTLBVirtPageo;
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integer n;
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integer n;
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// Holding registers
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// Holding registers
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// These allow the TLB to updated in a single cycle
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// These allow the TLB to updated in a single cycle
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reg [DBW-1:0] HTLBVirtPage;
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reg [DBW-1:0] HTLBVirtPage;
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assign HTLBVirtPageo = {HTLBVirtPage,12'b0};
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assign HTLBVirtPageo = {HTLBVirtPage,12'b0};
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reg [DBW-1:0] HTLBPhysPage;
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reg [DBW-1:0] HTLBPhysPage;
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reg [7:0] HTLBASID;
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reg [7:0] HTLBASID;
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reg HTLBG;
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reg HTLBG;
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reg HTLBD;
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reg HTLBD;
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reg [2:0] HTLBC;
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reg [2:0] HTLBC;
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reg HTLBValid;
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reg HTLBValid;
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reg TLBenabled;
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reg TLBenabled;
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reg [5:0] i;
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reg [5:0] i;
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reg [DBW-1:0] Index;
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reg [DBW-1:0] Index;
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reg [2:0] Random;
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reg [2:0] Random;
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reg [2:0] Wired;
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reg [2:0] Wired;
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reg [2:0] PageSize;
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reg [2:0] PageSize;
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reg [7:0] IMatch,DMatch;
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reg [7:0] IMatch,DMatch;
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reg [3:0] m;
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reg [3:0] m;
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reg [3:0] q;
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reg [3:0] q;
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wire doddpage;
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wire doddpage;
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reg [DBW-1:0] TLBVirtPage [63:0];
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reg [DBW-1:0] TLBVirtPage [63:0];
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reg [DBW-1:0] TLBPhysPage [63:0];
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reg [DBW-1:0] TLBPhysPage [63:0];
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reg [63:0] TLBG;
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reg [63:0] TLBG;
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reg [63:0] TLBD;
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reg [63:0] TLBD;
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reg [2:0] TLBC [63:0];
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reg [2:0] TLBC [63:0];
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reg [7:0] TLBASID [63:0];
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reg [7:0] TLBASID [63:0];
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reg [63:0] TLBValid;
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reg [63:0] TLBValid;
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reg [DBW-1:0] imiss_addr;
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reg [DBW-1:0] imiss_addr;
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reg [DBW-1:0] dmiss_addr;
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reg [DBW-1:0] dmiss_addr;
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reg [DBW-1:0] PageTblAddr;
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reg [DBW-1:0] PageTblAddr;
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reg [DBW-1:0] PageTblCtrl;
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reg [DBW-1:0] PageTblCtrl;
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initial begin
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initial begin
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for (n = 0; n < 64; n = n + 1)
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for (n = 0; n < 64; n = n + 1)
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begin
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begin
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TLBVirtPage[n] = 0;
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TLBVirtPage[n] = 0;
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TLBPhysPage[n] = 0;
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TLBPhysPage[n] = 0;
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TLBG[n] = 0;
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TLBG[n] = 0;
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TLBASID[n] = 0;
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TLBASID[n] = 0;
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TLBD[n] = 0;
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TLBD[n] = 0;
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TLBC[n] = 0;
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TLBC[n] = 0;
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TLBValid[n] = 0;
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TLBValid[n] = 0;
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end
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end
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end
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end
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// Assume the instruction doesn't overlap between a mapped and unmapped area.
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// Assume the instruction doesn't overlap between a mapped and unmapped area.
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wire unmappedArea = pc[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire unmappedArea = pc[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire unmappedDataArea = ea[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire unmappedDataArea = ea[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire m1UnmappedDataArea = pea[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire m1UnmappedDataArea = pea[DBW-1:DBW-4]==4'hF || !TLBenabled;
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wire hitIOPage = ea[DBW-1:DBW-12]==12'hFFD;
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wire hitIOPage = ea[DBW-1:DBW-12]==12'hFFD;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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TLBenabled <= 1'b0;
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TLBenabled <= 1'b0;
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Random <= 3'h7;
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Random <= 3'h7;
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Wired <= 3'd0;
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Wired <= 3'd0;
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PageSize <= 3'd0;
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PageSize <= 3'd0;
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PageTblAddr <= {DBW{1'b0}};
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PageTblAddr <= {DBW{1'b0}};
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PageTblCtrl <= {DBW{1'b0}};
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PageTblCtrl <= {DBW{1'b0}};
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end
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end
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else begin
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else begin
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if (dmiss_addr == {DBW{1'b0}} && DTLBMiss)
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if (dmiss_addr == {DBW{1'b0}} && DTLBMiss)
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dmiss_addr <= ea;
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dmiss_addr <= ea;
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if (imiss_addr == {DBW{1'b0}} && ITLBMiss)
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if (imiss_addr == {DBW{1'b0}} && ITLBMiss)
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imiss_addr <= pc;
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imiss_addr <= pc;
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if (Random==Wired)
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if (Random==Wired)
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Random <= 3'd7;
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Random <= 3'd7;
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else
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else
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Random <= Random - 3'd1;
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Random <= Random - 3'd1;
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if (state==3'd1) begin
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if (state==3'd1) begin
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case(op)
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case(op)
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`TLB_RD,`TLB_WI:
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`TLB_RD,`TLB_WI:
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i <= {Index[5:3],(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
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i <= {Index[5:3],(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
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`TLB_WR:
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`TLB_WR:
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i <= {Random,(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
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i <= {Random,(HTLBVirtPage >> {PageSize,1'b0}) & 3'h7};
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`TLB_WRREG:
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`TLB_WRREG:
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begin
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begin
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case(regno)
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case(regno)
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`TLBWired: Wired <= dati[2:0];
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`TLBWired: Wired <= dati[2:0];
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`TLBIndex: Index <= dati[5:0];
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`TLBIndex: Index <= dati[5:0];
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`TLBRandom: Random <= dati[2:0];
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`TLBRandom: Random <= dati[2:0];
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`TLBPageSize: PageSize <= dati[2:0];
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`TLBPageSize: PageSize <= dati[2:0];
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`TLBVirtPage: HTLBVirtPage <= dati;
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`TLBVirtPage: HTLBVirtPage <= dati;
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`TLBPhysPage: HTLBPhysPage <= dati;
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`TLBPhysPage: HTLBPhysPage <= dati;
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`TLBASID: begin
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`TLBASID: begin
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HTLBValid <= dati[0];
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HTLBValid <= dati[0];
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HTLBD <= dati[1];
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HTLBD <= dati[1];
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HTLBC <= dati[4:2];
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HTLBC <= dati[4:2];
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HTLBASID <= dati[23:16];
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HTLBASID <= dati[23:16];
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HTLBG <= dati[31];
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HTLBG <= dati[31];
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end
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end
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`TLBDMissAdr: dmiss_addr <= dati;
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`TLBDMissAdr: dmiss_addr <= dati;
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`TLBIMissAdr: imiss_addr <= dati;
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`TLBIMissAdr: imiss_addr <= dati;
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`TLBPageTblAddr: PageTblAddr <= dati;
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`TLBPageTblAddr: PageTblAddr <= dati;
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`TLBPageTblCtrl: PageTblCtrl <= dati;
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`TLBPageTblCtrl: PageTblCtrl <= dati;
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default: ;
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endcase
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endcase
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end
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end
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`TLB_EN:
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`TLB_EN:
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TLBenabled <= 1'b1;
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TLBenabled <= 1'b1;
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`TLB_DIS:
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`TLB_DIS:
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TLBenabled <= 1'b0;
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TLBenabled <= 1'b0;
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`TLB_INVALL:
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`TLB_INVALL:
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TLBValid <= 64'd0;
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TLBValid <= 64'd0;
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default: ;
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endcase
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endcase
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end
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end
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else if (state==3'd2) begin
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else if (state==3'd2) begin
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case(op)
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case(op)
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`TLB_P:
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`TLB_P:
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begin
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begin
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Index[DBW-1] <= ~|DMatch;
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Index[DBW-1] <= ~|DMatch;
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end
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end
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`TLB_RD:
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`TLB_RD:
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begin
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begin
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HTLBVirtPage <= TLBVirtPage[i];
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HTLBVirtPage <= TLBVirtPage[i];
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HTLBPhysPage <= TLBPhysPage[i];
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HTLBPhysPage <= TLBPhysPage[i];
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HTLBASID <= TLBASID[i];
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HTLBASID <= TLBASID[i];
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HTLBG <= TLBG[i];
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HTLBG <= TLBG[i];
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HTLBD <= TLBD[i];
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HTLBD <= TLBD[i];
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HTLBC <= TLBC[i];
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HTLBC <= TLBC[i];
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HTLBValid <= TLBValid[i];
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HTLBValid <= TLBValid[i];
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end
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end
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`TLB_WR,`TLB_WI:
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`TLB_WR,`TLB_WI:
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begin
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begin
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBVirtPage[i] <= HTLBVirtPage;
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TLBPhysPage[i] <= HTLBPhysPage;
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TLBPhysPage[i] <= HTLBPhysPage;
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TLBASID[i] <= HTLBASID;
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TLBASID[i] <= HTLBASID;
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TLBG[i] <= HTLBG;
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TLBG[i] <= HTLBG;
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TLBD[i] <= HTLBD;
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TLBD[i] <= HTLBD;
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TLBC[i] <= HTLBC;
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TLBC[i] <= HTLBC;
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TLBValid[i] <= HTLBValid;
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TLBValid[i] <= HTLBValid;
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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// Set the dirty bit on a store
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// Set the dirty bit on a store
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if (m1IsStore)
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if (m1IsStore)
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if (!m1UnmappedDataArea & !q[3]) begin
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if (!m1UnmappedDataArea & !q[3]) begin
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TLBD[{q[2:0],(pea[DBW-1:12]>>{PageSize,1'b0})&3'd7}] <= 1'b1;
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TLBD[{q[2:0],(pea[DBW-1:12]>>{PageSize,1'b0})&3'd7}] <= 1'b1;
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end
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end
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end
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end
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always @*
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always @*
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case(regno)
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case(regno)
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`TLBWired: dato = Wired;
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`TLBWired: dato = Wired;
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`TLBIndex: dato = Index;
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`TLBIndex: dato = Index;
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`TLBRandom: dato = Random;
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`TLBRandom: dato = Random;
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`TLBPhysPage: dato = HTLBPhysPage;
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`TLBPhysPage: dato = HTLBPhysPage;
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`TLBVirtPage: dato = HTLBVirtPage;
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`TLBVirtPage: dato = HTLBVirtPage;
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`TLBPageSize: dato = PageSize;
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`TLBPageSize: dato = PageSize;
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`TLBASID: begin
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`TLBASID: begin
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dato = {DBW{1'b0}};
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dato = {DBW{1'b0}};
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dato[0] = HTLBValid;
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dato[0] = HTLBValid;
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dato[1] = HTLBD;
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dato[1] = HTLBD;
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dato[4:2] = HTLBC;
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dato[4:2] = HTLBC;
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dato[23:16] = HTLBASID;
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dato[23:16] = HTLBASID;
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dato[31] = HTLBG;
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dato[31] = HTLBG;
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end
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end
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`TLBDMissAdr: dato = dmiss_addr;
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`TLBDMissAdr: dato = dmiss_addr;
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`TLBIMissAdr: dato = imiss_addr;
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`TLBIMissAdr: dato = imiss_addr;
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`TLBPageTblAddr: dato = PageTblAddr;
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`TLBPageTblAddr: dato = PageTblAddr;
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`TLBPageTblCtrl: dato = PageTblCtrl;
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`TLBPageTblCtrl: dato = PageTblCtrl;
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default: dato = {DBW{1'b0}};
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default: dato = {DBW{1'b0}};
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endcase
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endcase
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wire [DBW-1:0] pcs = pc[DBW-1:12] >> {PageSize,1'b0};
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wire [DBW-1:0] pcs = pc[DBW-1:12] >> {PageSize,1'b0};
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always @*
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always @*
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for (n = 0; n < 8; n = n + 1)
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for (n = 0; n < 8; n = n + 1)
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begin
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begin
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IMatch[n[2:0]] = (pcs[DBW-1:3]==TLBVirtPage[{n[2:0],pcs[2:0]}][DBW-1:3]) &&
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IMatch[n[2:0]] = (pcs[DBW-1:3]==TLBVirtPage[{n[2:0],pcs[2:0]}][DBW-1:3]) &&
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((TLBASID[{n,pcs[2:0]}]==ASID) || TLBG[{n,pcs[2:0]}]) &&
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((TLBASID[{n,pcs[2:0]}]==ASID) || TLBG[{n,pcs[2:0]}]) &&
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TLBValid[{n[2:0],pcs[2:0]}];
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TLBValid[{n[2:0],pcs[2:0]}];
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end
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end
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always @(IMatch)
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always @(IMatch)
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if (IMatch[0]) m <= 4'd0;
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if (IMatch[0]) m <= 4'd0;
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else if (IMatch[1]) m <= 4'd1;
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else if (IMatch[1]) m <= 4'd1;
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else if (IMatch[2]) m <= 4'd2;
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else if (IMatch[2]) m <= 4'd2;
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else if (IMatch[3]) m <= 4'd3;
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else if (IMatch[3]) m <= 4'd3;
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else if (IMatch[4]) m <= 4'd4;
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else if (IMatch[4]) m <= 4'd4;
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else if (IMatch[5]) m <= 4'd5;
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else if (IMatch[5]) m <= 4'd5;
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else if (IMatch[6]) m <= 4'd6;
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else if (IMatch[6]) m <= 4'd6;
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else if (IMatch[7]) m <= 4'd7;
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else if (IMatch[7]) m <= 4'd7;
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else m <= 4'd15;
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else m <= 4'd15;
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wire [DBW-1:0] IPFN = TLBPhysPage[{m[2:0],pcs[2:0]}];
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wire [DBW-1:0] IPFN = TLBPhysPage[{m[2:0],pcs[2:0]}];
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assign iuncached = TLBC[{m[2:0],pcs[2:0]}]==3'd1;
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assign iuncached = TLBC[{m[2:0],pcs[2:0]}]==3'd1;
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assign ITLBMiss = TLBenabled & (!unmappedArea & (m[3] | ~TLBValid[{m[2:0],pcs[2:0]}]));
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assign ITLBMiss = TLBenabled & (!unmappedArea & (m[3] | ~TLBValid[{m[2:0],pcs[2:0]}]));
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always @*
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always @*
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begin
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begin
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ppc[11:0] = pc[11:0];
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ppc[11:0] = pc[11:0];
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case(PageSize)
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case(PageSize)
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3'd0: ppc[DBW-1:12] = unmappedArea ? pc[DBW-1:12] : ITLBMiss ? `TLBMissPage: IPFN; // 4KiB
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3'd0: ppc[DBW-1:12] = unmappedArea ? pc[DBW-1:12] : ITLBMiss ? `TLBMissPage: IPFN; // 4KiB
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3'd1: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:14] : ITLBMiss ? `TLBMissPage: IPFN,pc[13:12]}; // 16KiB
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3'd1: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:14] : ITLBMiss ? `TLBMissPage: IPFN,pc[13:12]}; // 16KiB
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3'd2: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:16] : ITLBMiss ? `TLBMissPage: IPFN,pc[15:12]}; // 64KiB
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3'd2: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:16] : ITLBMiss ? `TLBMissPage: IPFN,pc[15:12]}; // 64KiB
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3'd3: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:18] : ITLBMiss ? `TLBMissPage: IPFN,pc[17:12]}; // 256 KiB
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3'd3: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:18] : ITLBMiss ? `TLBMissPage: IPFN,pc[17:12]}; // 256 KiB
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3'd4: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:20] : ITLBMiss ? `TLBMissPage: IPFN,pc[19:12]}; // 1 MiB
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3'd4: ppc[DBW-1:12] = {unmappedArea ? pc[DBW-1:20] : ITLBMiss ? `TLBMissPage: IPFN,pc[19:12]}; // 1 MiB
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default: ppc[DBW-1:12] = pc[DBW-1:12];
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default: ppc[DBW-1:12] = pc[DBW-1:12];
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endcase
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endcase
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end
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end
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wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
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wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
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always @(ea)
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always @(eas or ASID or q or TLBG or TLBValid)
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for (n = 0; n < 8; n = n + 1)
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for (n = 0; n < 8; n = n + 1)
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DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
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DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
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((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
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((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
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TLBValid[{q[2:0],eas[2:0]}];
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TLBValid[{q[2:0],eas[2:0]}];
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always @(DMatch)
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always @(DMatch)
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if (DMatch[0]) q <= 4'd0;
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if (DMatch[0]) q <= 4'd0;
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else if (DMatch[1]) q <= 4'd1;
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else if (DMatch[1]) q <= 4'd1;
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else if (DMatch[2]) q <= 4'd2;
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else if (DMatch[2]) q <= 4'd2;
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else if (DMatch[3]) q <= 4'd3;
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else if (DMatch[3]) q <= 4'd3;
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else if (DMatch[4]) q <= 4'd4;
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else if (DMatch[4]) q <= 4'd4;
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else if (DMatch[5]) q <= 4'd5;
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else if (DMatch[5]) q <= 4'd5;
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else if (DMatch[6]) q <= 4'd6;
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else if (DMatch[6]) q <= 4'd6;
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else if (DMatch[7]) q <= 4'd7;
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else if (DMatch[7]) q <= 4'd7;
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else q <= 4'd15;
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else q <= 4'd15;
|
|
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wire [DBW-1:0] DPFN = TLBPhysPage[{q[2:0],eas[2:0]}];
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wire [DBW-1:0] DPFN = TLBPhysPage[{q[2:0],eas[2:0]}];
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assign uncached = TLBC[{q[2:0],eas[2:0]}]==3'd1;// || unmappedDataArea;
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assign uncached = TLBC[{q[2:0],eas[2:0]}]==3'd1;// || unmappedDataArea;
|
|
|
assign DTLBMiss = TLBenabled & (!unmappedDataArea & (q[3] | ~TLBValid[{q[2:0],eas[2:0]}]) ||
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assign DTLBMiss = TLBenabled & (!unmappedDataArea & (q[3] | ~TLBValid[{q[2:0],eas[2:0]}]) ||
|
(!km && hitIOPage));
|
(!km && hitIOPage));
|
|
|
always @*
|
always @*
|
begin
|
begin
|
case(PageSize)
|
case(PageSize)
|
3'd0: pea[DBW-1:12] = unmappedDataArea ? ea[DBW-1:12] : DTLBMiss ? `TLBMissPage: DPFN;
|
3'd0: pea[DBW-1:12] = unmappedDataArea ? ea[DBW-1:12] : DTLBMiss ? `TLBMissPage: DPFN;
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3'd1: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:14] : DTLBMiss ? `TLBMissPage: DPFN,ea[13:12]};
|
3'd1: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:14] : DTLBMiss ? `TLBMissPage: DPFN,ea[13:12]};
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3'd2: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:16] : DTLBMiss ? `TLBMissPage: DPFN,ea[15:12]};
|
3'd2: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:16] : DTLBMiss ? `TLBMissPage: DPFN,ea[15:12]};
|
3'd3: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:18] : DTLBMiss ? `TLBMissPage: DPFN,ea[17:12]};
|
3'd3: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:18] : DTLBMiss ? `TLBMissPage: DPFN,ea[17:12]};
|
3'd4: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:20] : DTLBMiss ? `TLBMissPage: DPFN,ea[19:12]};
|
3'd4: pea[DBW-1:12] = {unmappedDataArea ? ea[DBW-1:20] : DTLBMiss ? `TLBMissPage: DPFN,ea[19:12]};
|
default: pea[DBW-1:12] = ea[DBW-1:12];
|
default: pea[DBW-1:12] = ea[DBW-1:12];
|
endcase
|
endcase
|
pea[11:0] = ea[11:0];
|
pea[11:0] = ea[11:0];
|
end
|
end
|
|
|
endmodule
|
endmodule
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|
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|
