// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Thor Superscaler
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// Thor Superscaler
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// Thor_divider.v
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// Thor_divider.v
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// - 64 bit divider
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// - 64 bit divider
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module Thor_divider(rst, clk, ld, abort, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done, idle);
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module Thor_divider(rst, clk, ld, abort, sgn, isDivi, a, b, imm, qo, ro, dvByZr, done, idle);
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parameter WID=64;
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parameter WID=64;
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parameter DIV=3'd3;
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parameter DIV=3'd3;
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parameter IDLE=3'd4;
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parameter IDLE=3'd4;
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parameter DONE=3'd5;
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parameter DONE=3'd5;
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input clk;
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input clk;
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input rst;
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input rst;
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input ld;
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input ld;
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input abort;
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input abort;
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input sgn;
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input sgn;
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input isDivi;
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input isDivi;
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input [WID-1:0] a;
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input [WID-1:0] a;
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input [WID-1:0] b;
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input [WID-1:0] b;
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input [WID-1:0] imm;
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input [WID-1:0] imm;
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output [WID-1:0] qo;
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output [WID-1:0] qo;
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reg [WID-1:0] qo;
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reg [WID-1:0] qo;
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output [WID-1:0] ro;
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output [WID-1:0] ro;
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reg [WID-1:0] ro;
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reg [WID-1:0] ro;
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output done;
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output done;
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output idle;
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output idle;
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output dvByZr;
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output dvByZr;
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reg dvByZr;
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reg dvByZr;
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reg [WID-1:0] aa,bb;
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reg [WID-1:0] aa,bb;
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reg so;
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reg so;
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reg [2:0] state;
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reg [2:0] state;
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reg [7:0] cnt;
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reg [7:0] cnt;
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wire cnt_done = cnt==8'd0;
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wire cnt_done = cnt==8'd0;
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assign done = state==DONE;
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assign done = state==DONE||(state==IDLE && !ld);
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assign idle = state==IDLE;
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assign idle = state==IDLE;
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reg ce1;
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reg ce1;
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reg [WID-1:0] q;
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reg [WID-1:0] q;
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reg [WID:0] r;
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reg [WID:0] r;
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wire b0 = bb <= r;
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wire b0 = bb <= r;
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wire [WID-1:0] r1 = b0 ? r - bb : r;
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wire [WID-1:0] r1 = b0 ? r - bb : r;
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initial begin
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initial begin
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q = 64'd0;
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q = 64'd0;
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r = 64'd0;
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r = 64'd0;
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qo = 64'd0;
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qo = 64'd0;
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ro = 64'd0;
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ro = 64'd0;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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aa <= {WID{1'b0}};
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aa <= {WID{1'b0}};
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bb <= {WID{1'b0}};
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bb <= {WID{1'b0}};
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q <= {WID{1'b0}};
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q <= {WID{1'b0}};
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r <= {WID{1'b0}};
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r <= {WID{1'b0}};
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qo <= {WID{1'b0}};
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qo <= {WID{1'b0}};
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ro <= {WID{1'b0}};
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ro <= {WID{1'b0}};
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cnt <= 8'd0;
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cnt <= 8'd0;
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dvByZr <= 1'b0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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else
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else
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begin
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begin
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if (abort)
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if (abort)
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cnt <= 8'd00;
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cnt <= 8'd00;
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else if (!cnt_done)
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else if (!cnt_done)
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cnt <= cnt - 8'd1;
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cnt <= cnt - 8'd1;
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case(state)
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case(state)
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IDLE:
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IDLE:
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if (ld) begin
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if (ld) begin
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if (sgn) begin
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if (sgn) begin
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q <= a[WID-1] ? -a : a;
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q <= a[WID-1] ? -a : a;
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bb <= isDivi ? (imm[WID-1] ? -imm : imm) :(b[WID-1] ? -b : b);
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bb <= isDivi ? (imm[WID-1] ? -imm : imm) :(b[WID-1] ? -b : b);
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so <= isDivi ? a[WID-1] ^ imm[WID-1] : a[WID-1] ^ b[WID-1];
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so <= isDivi ? a[WID-1] ^ imm[WID-1] : a[WID-1] ^ b[WID-1];
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end
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end
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else begin
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else begin
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q <= a;
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q <= a;
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bb <= isDivi ? imm : b;
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bb <= isDivi ? imm : b;
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so <= 1'b0;
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so <= 1'b0;
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$display("bb=%d", isDivi ? imm : b);
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$display("bb=%d", isDivi ? imm : b);
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end
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end
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dvByZr <= isDivi ? imm=={WID{1'b0}} : b=={WID{1'b0}};
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dvByZr <= isDivi ? imm=={WID{1'b0}} : b=={WID{1'b0}};
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r <= {WID{1'b0}};
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r <= {WID{1'b0}};
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cnt <= WID+1;
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cnt <= WID+1;
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state <= DIV;
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state <= DIV;
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end
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end
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DIV:
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DIV:
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if (!cnt_done) begin
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if (!cnt_done) begin
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$display("cnt:%d r1=%h q[63:0]=%h", cnt,r1,q);
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$display("cnt:%d r1=%h q[63:0]=%h", cnt,r1,q);
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q <= {q[WID-2:0],b0};
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q <= {q[WID-2:0],b0};
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r <= {r1,q[WID-1]};
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r <= {r1,q[WID-1]};
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end
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end
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else begin
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else begin
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$display("cnt:%d r1=%h q[63:0]=%h", cnt,r1,q);
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$display("cnt:%d r1=%h q[63:0]=%h", cnt,r1,q);
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if (sgn) begin
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if (sgn) begin
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if (so) begin
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if (so) begin
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qo <= -q;
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qo <= -q;
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ro <= -r[WID:1];
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ro <= -r[WID:1];
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end
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end
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else begin
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else begin
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qo <= q;
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qo <= q;
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ro <= r[WID:1];
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ro <= r[WID:1];
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end
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end
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end
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end
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else begin
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else begin
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qo <= q;
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qo <= q;
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ro <= r[WID:1];
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ro <= r[WID:1];
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end
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end
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state <= DONE;
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state <= DONE;
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end
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end
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DONE:
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DONE:
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state <= IDLE;
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state <= IDLE;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module Thor_divider_tb();
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module Thor_divider_tb();
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parameter WID=64;
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parameter WID=64;
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg ld;
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reg ld;
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wire done;
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wire done;
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wire [WID-1:0] qo,ro;
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wire [WID-1:0] qo,ro;
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initial begin
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initial begin
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clk = 1;
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clk = 1;
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rst = 0;
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rst = 0;
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#100 rst = 1;
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#100 rst = 1;
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#100 rst = 0;
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#100 rst = 0;
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#100 ld = 1;
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#100 ld = 1;
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#150 ld = 0;
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#150 ld = 0;
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end
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end
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always #10 clk = ~clk; // 50 MHz
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always #10 clk = ~clk; // 50 MHz
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Thor_divider #(WID) u1
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Thor_divider #(WID) u1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(ld),
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.ld(ld),
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.sgn(1'b1),
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.sgn(1'b1),
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.isDivi(1'b0),
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.isDivi(1'b0),
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.a(64'd10005),
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.a(64'd10005),
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.b(64'd27),
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.b(64'd27),
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.imm(64'd123),
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.imm(64'd123),
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.qo(qo),
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.qo(qo),
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.ro(ro),
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.ro(ro),
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.dvByZr(),
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.dvByZr(),
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.done(done)
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.done(done)
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);
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);
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endmodule
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endmodule
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