// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Thor SuperScalar
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// Thor SuperScalar
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// Execute combinational logic
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// Execute combinational logic
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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wire [DBW-1:0] alu0_out, alu1_out;
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wire [DBW-1:0] alu0_out, alu1_out;
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wire alu0_done,alu1_done;
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wire alu0_done,alu1_done;
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wire alu0_idle,alu1_idle;
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wire alu0_idle,alu1_idle;
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wire alu0_divByZero, alu1_divByZero;
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wire alu0_divByZero, alu1_divByZero;
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wire alu0_abort,alu1_abort;
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wire alu0_abort,alu1_abort;
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Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
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Thor_alu #(.DBW(DBW),.BIG(1)) ualu0
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(
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(
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.corenum(corenum),
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.corenum(corenum),
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk),
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.clk(clk),
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.alu_ld(alu0_ld),
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.alu_ld(alu0_ld),
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.alu_abort(alu0_abort),
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.alu_abort(alu0_abort),
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.alu_op(alu0_op),
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.alu_op(alu0_op),
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.alu_fn(alu0_fn),
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.alu_fn(alu0_fn),
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.alu_argA(alu0_argA),
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.alu_argA(alu0_argA),
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.alu_argB(alu0_argB),
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.alu_argB(alu0_argB),
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.alu_argC(alu0_argC),
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.alu_argC(alu0_argC),
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.alu_argI(alu0_argI),
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.alu_argI(alu0_argI),
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.alu_pc(alu0_pc),
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.alu_pc(alu0_pc),
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.insnsz(alu0_insnsz),
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.insnsz(alu0_insnsz),
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.o(alu0_out),
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.o(alu0_out),
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.alu_done(alu0_done),
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.alu_done(alu0_done),
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.alu_idle(alu0_idle),
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.alu_idle(alu0_idle),
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.alu_divByZero(alu0_divByZero)
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.alu_divByZero(alu0_divByZero)
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);
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);
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Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
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Thor_alu #(.DBW(DBW),.BIG(ALU1BIG)) ualu1
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(
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(
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.corenum(corenum),
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.corenum(corenum),
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk),
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.clk(clk),
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.alu_ld(alu1_ld),
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.alu_ld(alu1_ld),
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.alu_abort(alu1_abort),
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.alu_abort(alu1_abort),
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.alu_op(alu1_op),
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.alu_op(alu1_op),
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.alu_fn(alu1_fn),
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.alu_fn(alu1_fn),
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.alu_argA(alu1_argA),
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.alu_argA(alu1_argA),
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.alu_argB(alu1_argB),
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.alu_argB(alu1_argB),
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.alu_argC(alu1_argC),
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.alu_argC(alu1_argC),
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.alu_argI(alu1_argI),
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.alu_argI(alu1_argI),
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.alu_pc(alu1_pc),
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.alu_pc(alu1_pc),
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.insnsz(alu1_insnsz),
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.insnsz(alu1_insnsz),
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.o(alu1_out),
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.o(alu1_out),
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.alu_done(alu1_done),
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.alu_done(alu1_done),
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.alu_idle(alu1_idle),
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.alu_idle(alu1_idle),
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.alu_divByZero(alu1_divByZero)
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.alu_divByZero(alu1_divByZero)
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);
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);
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function fnPredicate;
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function fnPredicate;
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input [3:0] pr;
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input [3:0] pr;
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input [3:0] cond;
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input [3:0] cond;
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case(cond)
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case(cond)
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PF: fnPredicate = 1'b0;
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PF: fnPredicate = 1'b0;
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PT: fnPredicate = 1'b1;
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PT: fnPredicate = 1'b1;
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PEQ: fnPredicate = pr[0];
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PEQ: fnPredicate = pr[0];
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PNE: fnPredicate = !pr[0];
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PNE: fnPredicate = !pr[0];
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PLE: fnPredicate = pr[0]|pr[1];
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PLE: fnPredicate = pr[0]|pr[1];
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PGT: fnPredicate = !(pr[0]|pr[1]);
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PGT: fnPredicate = !(pr[0]|pr[1]);
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PLT: fnPredicate = pr[1];
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PLT: fnPredicate = pr[1];
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PGE: fnPredicate = !pr[1];
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PGE: fnPredicate = !pr[1];
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PLEU: fnPredicate = pr[0]|pr[2];
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PLEU: fnPredicate = pr[0]|pr[2];
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PGTU: fnPredicate = !(pr[0]|pr[2]);
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PGTU: fnPredicate = !(pr[0]|pr[2]);
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PLTU: fnPredicate = pr[2];
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PLTU: fnPredicate = pr[2];
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PGEU: fnPredicate = !pr[2];
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PGEU: fnPredicate = !pr[2];
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default: fnPredicate = 1'b1;
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default: fnPredicate = 1'b1;
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endcase
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endcase
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endfunction
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endfunction
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wire alu0_cmtw = fnPredicate(alu0_pred, alu0_cond);
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wire alu0_cmtw = fnPredicate(alu0_pred, alu0_cond);
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wire alu1_cmtw = fnPredicate(alu1_pred, alu1_cond);
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wire alu1_cmtw = fnPredicate(alu1_pred, alu1_cond);
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always @*
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always @*
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begin
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begin
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alu0_cmt <= alu0_cmtw;
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alu0_cmt <= alu0_cmtw;
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alu1_cmt <= alu1_cmtw;
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alu1_cmt <= alu1_cmtw;
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alu0_bus <= alu0_cmtw ? alu0_out : alu0_argT;
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alu0_bus <= alu0_cmtw ? alu0_out : alu0_argT;
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alu1_bus <= alu1_cmtw ? alu1_out : alu1_argT;
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alu1_bus <= alu1_cmtw ? alu1_out : alu1_argT;
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alu0_v <= alu0_dataready;
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alu0_v <= alu0_dataready;
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alu1_v <= alu1_dataready;
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alu1_v <= alu1_dataready;
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alu0_id <= alu0_sourceid;
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alu0_id <= alu0_sourceid;
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alu1_id <= alu1_sourceid;
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alu1_id <= alu1_sourceid;
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end
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end
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assign alu0_abort = !alu0_cmt;
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assign alu0_abort = !alu0_cmt;
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assign alu1_abort = !alu1_cmt;
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assign alu1_abort = !alu1_cmt;
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// Special flag nybble is used for INT and SYS instructions in order to turn off
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// Special flag bit is used for INT and SYS instructions in order to turn off
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// segmentation while the vector jump is taking place.
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// segmentation while the vector jump is taking place.
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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always @(alu0_op or alu0_fn or alu0_argA or alu0_argI or alu0_insnsz or alu0_pc or alu0_bt)
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case(alu0_op)
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case(alu0_op)
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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alu0_misspc <= alu0_argA + alu0_argI;
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alu0_misspc <= alu0_argA + alu0_argI;
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`LOOP,`SYNC:
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`LOOP,`SYNC:
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alu0_misspc <= alu0_pc + alu0_insnsz;
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alu0_misspc <= alu0_pc + alu0_insnsz;
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`RTS:
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`RTS:
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alu0_misspc <= alu0_argA + alu0_fn[3:0];
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alu0_misspc <= alu0_argA + alu0_fn[3:0];
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`SYS,`INT:
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`SYS,`INT:
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alu0_misspc <= {1'b1,alu0_argA + alu0_argI};
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alu0_misspc <= {1'b1,alu0_argA + alu0_argI};
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default:
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default:
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alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
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alu0_misspc <= (alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI);
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endcase
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endcase
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always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
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always @(alu1_op or alu1_fn or alu1_argA or alu1_argI or alu1_insnsz or alu1_pc or alu1_bt)
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case(alu1_op)
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case(alu1_op)
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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`JSR,`JSRS,`JSRZ,`RTD,`RTE,`RTI,`RTS2:
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alu1_misspc <= alu1_argA + alu1_argI;
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alu1_misspc <= alu1_argA + alu1_argI;
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`LOOP,`SYNC:
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`LOOP,`SYNC:
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alu1_misspc <= alu1_pc + alu1_insnsz;
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alu1_misspc <= alu1_pc + alu1_insnsz;
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`RTS:
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`RTS:
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alu1_misspc <= alu1_argA + alu1_fn[3:0];
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alu1_misspc <= alu1_argA + alu1_fn[3:0];
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`SYS,`INT:
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`SYS,`INT:
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alu1_misspc <= {1'b1,alu1_argA + alu1_argI};
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alu1_misspc <= {1'b1,alu1_argA + alu1_argI};
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default:
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default:
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alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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alu1_misspc <= (alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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endcase
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endcase
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always @(dram0_fn or dram0_misspc or dram_bus)
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always @(dram0_fn or dram0_misspc or dram_bus)
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case (dram0_fn[1:0])
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case (dram0_fn[1:0])
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2'd1: jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};
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2'd1: jmpi_misspc <= {dram0_misspc[DBW-1:16],dram_bus[15:0]};
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2'd2: jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};
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2'd2: jmpi_misspc <= (DBW==32) ? dram_bus[31:0] : {dram0_misspc[63:32],dram_bus[31:0]};
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2'd3: jmpi_misspc <= dram_bus[DBW-1:0];
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2'd3: jmpi_misspc <= dram_bus[DBW-1:0];
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default: jmpi_misspc <= 32'h00000FA0; // unimplemented instruction vector
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default: jmpi_misspc <= 32'h00000FA0; // unimplemented instruction vector
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endcase
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endcase
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/*
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assign alu0_misspc = (alu0_op == `JSR || alu0_op==`JSRS || alu0_op==`JSRZ ||
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assign alu0_exc = (fnIsKMOnly(alu0_op) && !km && alu0_cmt) ? `EXC_PRIV :
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op == `RTE || alu0_op==`RTI || alu0_op==`LOOP) ? alu0_argA + alu0_argI :
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(alu0_done && alu0_divByZero && alu0_cmt) ? `EXC_DBZ :
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(alu0_op == `SYS || alu0_op==`INT) ? alu0_argA + {alu0_argI[DBW-5:0],4'b0} :
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((alu0_op==`CHKI||(alu0_op==`RR && alu0_fn==`CHK)) && !alu0_out && alu0_cmt) ? `EXC_CHK :
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(alu0_bt ? alu0_pc + alu0_insnsz : alu0_pc + alu0_insnsz + alu0_argI),
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`EXC_NONE;
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alu1_misspc = (alu1_op == `JSR || alu1_op==`JSRS || alu1_op==`JSRZ ||
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alu1_op==`RTS || alu1_op == `RTE || alu1_op==`RTI || alu1_op==`LOOP) ? alu1_argA + alu1_argI :
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assign alu1_exc = (fnIsKMOnly(alu1_op) && !km && alu1_cmt) ? `EXC_PRIV :
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(alu1_op == `SYS || alu1_op==`INT) ? alu1_argA + {alu1_argI[DBW-5:0],4'b0} :
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(alu1_done && alu1_divByZero && alu1_cmt) ? `EXC_DBZ :
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(alu1_bt ? alu1_pc + alu1_insnsz : alu1_pc + alu1_insnsz + alu1_argI);
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((alu1_op==`CHKI ||(alu1_op==`RR && alu1_fn==`CHK)) && !alu1_out && alu1_cmt) ? `EXC_CHK :
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*/
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`EXC_NONE;
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assign alu0_exc = (fnIsKMOnly(alu0_op) && !km) ? `EXC_PRIV :
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(alu0_done && alu0_divByZero) ? `EXC_DBZ : `EXC_NONE;
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// ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu0_argB[`INSTRUCTION_S2]
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
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// : (alu0_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu0_argB[`INSTRUCTION_S2]
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// : `EXC_INVALID;
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assign alu1_exc = (fnIsKMOnly(alu1_op) && !km) ? `EXC_PRIV :
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(alu1_done && alu1_divByZero) ? `EXC_DBZ : `EXC_NONE;
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// ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_NONE) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_CALL) ? alu1_argB[`INSTRUCTION_S2]
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MFSR) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_MTSR) ? `EXC_NONE
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU1) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU2) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_RFU3) ? `EXC_INVALID
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// : (alu1_argB[`INSTRUCTION_S1] == `SYS_EXC) ? alu1_argB[`INSTRUCTION_S2]
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// : `EXC_INVALID;
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assign alu0_branchmiss = alu0_dataready &&
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assign alu0_branchmiss = alu0_dataready &&
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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((fnIsBranch(alu0_op)) ? ((alu0_cmt && !alu0_bt) || (!alu0_cmt && alu0_bt))
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: !alu0_cmt ? (alu0_op==`LOOP)
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: !alu0_cmt ? (alu0_op==`LOOP)
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: (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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: (alu0_cmt && (alu0_op==`SYNC || alu0_op == `JSR || alu0_op == `JSRS || alu0_op == `JSRZ ||
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alu0_op==`SYS || alu0_op==`INT ||
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alu0_op==`SYS || alu0_op==`INT ||
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
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alu0_op==`RTS || alu0_op==`RTS2 || alu0_op==`RTD || alu0_op == `RTE || alu0_op==`RTI || ((alu0_op==`LOOP) && (alu0_argA == 64'd0)))));
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assign alu1_branchmiss = alu1_dataready &&
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assign alu1_branchmiss = alu1_dataready &&
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((fnIsBranch(alu1_op)) ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
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((fnIsBranch(alu1_op)) ? ((alu1_cmt && !alu1_bt) || (!alu1_cmt && alu1_bt))
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: !alu1_cmt ? (alu1_op==`LOOP)
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: !alu1_cmt ? (alu1_op==`LOOP)
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: (alu1_cmt && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
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: (alu1_cmt && (alu1_op==`SYNC || alu1_op == `JSR || alu1_op == `JSRS || alu1_op == `JSRZ ||
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alu1_op==`SYS || alu1_op==`INT ||
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alu1_op==`SYS || alu1_op==`INT ||
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alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
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alu1_op==`RTS || alu1_op==`RTS2 || alu1_op==`RTD || alu1_op == `RTE || alu1_op==`RTI || ((alu1_op==`LOOP) && (alu1_argA == 64'd0)))));
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assign branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
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assign branchmiss = (alu0_branchmiss | alu1_branchmiss | mem_stringmiss | jmpi_miss),
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misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
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misspc = (jmpi_miss ? jmpi_misspc : mem_stringmiss ? dram0_misspc : alu0_branchmiss ? alu0_misspc : alu1_misspc),
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missid = (jmpi_miss ? dram0_id : mem_stringmiss ? dram0_id : alu0_branchmiss ? alu0_sourceid : alu1_sourceid);
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missid = (jmpi_miss ? dram0_id : mem_stringmiss ? dram0_id : alu0_branchmiss ? alu0_sourceid : alu1_sourceid);
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`ifdef FLOATING_POINT
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`ifdef FLOATING_POINT
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wire fp0_exception;
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wire fp0_exception;
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fpUnit ufp0
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fpUnit ufp0
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk),
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.clk(clk),
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.ce(1'b1),
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.ce(1'b1),
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.op(fp0_op),
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.op(fp0_op),
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.fn(fp0_fn),
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.fn(fp0_fn),
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.ld(fp0_ld),
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.ld(fp0_ld),
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.a(fp0_argA),
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.a(fp0_argA),
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.b(fp0_argB),
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.b(fp0_argB),
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.o(fp0_bus),
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.o(fp0_bus),
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.exception(fp0_exception)
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.exception(fp0_exception)
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);
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);
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|
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reg [7:0] cnt;
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reg [7:0] cnt;
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always @(posedge clk)
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always @(posedge clk)
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if (rst_i)
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if (rst_i)
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cnt <= 8'h00;
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cnt <= 8'h00;
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else begin
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else begin
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if (fp0_ld)
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if (fp0_ld)
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cnt <= 8'h00;
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cnt <= 8'h00;
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else begin
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else begin
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if (cnt < 8'hff)
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if (cnt < 8'hff)
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cnt <= cnt + 8'd1;
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cnt <= cnt + 8'd1;
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end
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end
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end
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end
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|
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always @*
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always @*
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begin
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begin
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case(fp0_op)
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case(fp0_op)
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`FLOAT:
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`FLOAT:
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case(fp0_fn)
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case(fp0_fn)
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`FCMP,`FCMPS: fp0_done = 1'b1; // These ops are done right away
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`FCMP,`FCMPS: fp0_done = 1'b1; // These ops are done right away
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`FADD,`FSUB,`FMUL,`FADDS,`FSUBS,`FMULS:
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`FADD,`FSUB,`FMUL,`FADDS,`FSUBS,`FMULS:
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fp0_done = cnt > 8'd4;
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fp0_done = cnt > 8'd4;
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`FDIV: fp0_done = cnt > 8'h70;
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`FDIV: fp0_done = cnt > 8'h70;
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`FDIVS: fp0_done = cnt > 8'h37;
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`FDIVS: fp0_done = cnt > 8'h37;
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default: fp0_done = 1'b1;
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default: fp0_done = 1'b1;
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endcase
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endcase
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`SINGLE_R:
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`SINGLE_R:
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case(fp0_fn)
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case(fp0_fn)
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`FNEGS,`FABSS,`FSIGNS,`FMOVS,
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`FNEGS,`FABSS,`FSIGNS,`FMOVS,
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`FNABSS,`FMANS:
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`FNABSS,`FMANS:
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fp0_done = 1'b1; // These ops are done right away
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fp0_done = 1'b1; // These ops are done right away
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`FTOIS,`ITOFS: fp0_done = cnt > 8'd1;
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`FTOIS,`ITOFS: fp0_done = cnt > 8'd1;
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default: fp0_done = 1'b1;
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default: fp0_done = 1'b1;
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endcase
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endcase
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`DOUBLE_R:
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`DOUBLE_R:
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case(fp0_fn)
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case(fp0_fn)
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`FMOV,`FNEG,`FABS,`FNABS,`FSIGN,`FMAN:
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`FMOV,`FNEG,`FABS,`FNABS,`FSIGN,`FMAN:
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fp0_done = 1'b1; // These ops are done right away
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fp0_done = 1'b1; // These ops are done right away
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`FTOI,`ITOF: fp0_done = cnt > 8'd1;
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`FTOI,`ITOF: fp0_done = cnt > 8'd1;
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default: fp0_done = 1'b1;
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default: fp0_done = 1'b1;
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endcase
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endcase
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default: fp0_done = 1'b1;
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default: fp0_done = 1'b1;
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endcase
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endcase
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end
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end
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|
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assign fp0_cmt = fnPredicate(fp0_pred, fp0_cond);
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assign fp0_cmt = fnPredicate(fp0_pred, fp0_cond);
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assign fp0_exc = fp0_exception ? 8'd242 : 8'd0;
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assign fp0_exc = fp0_exception ? 8'd242 : 8'd0;
|
|
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assign fp0_v = fp0_dataready;
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assign fp0_v = fp0_dataready;
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assign fp0_id = fp0_sourceid;
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assign fp0_id = fp0_sourceid;
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`endif
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`endif
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