// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Thor Superscaler
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// Thor Superscaler
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// Thor_multiplier.v
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// Thor_multiplier.v
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// - 64 bit multiplier
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// - 64 bit multiplier
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module Thor_multiplier(rst, clk, ld, sgn, isMuli, a, b, imm, o, done);
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module Thor_multiplier(rst, clk, ld, abort, sgn, isMuli, a, b, imm, o, done, idle);
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parameter WID=64;
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parameter WID=64;
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parameter SGNADJO=3'd2;
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parameter SGNADJO=3'd2;
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parameter MULT=3'd3;
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parameter MULT=3'd3;
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parameter IDLE=3'd4;
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parameter IDLE=3'd4;
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parameter DONE=3'd5;
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parameter DONE=3'd5;
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input clk;
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input clk;
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input rst;
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input rst;
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input ld;
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input ld;
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input abort;
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input sgn;
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input sgn;
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input isMuli;
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input isMuli;
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input [WID-1:0] a;
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input [WID-1:0] a;
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input [WID-1:0] b;
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input [WID-1:0] b;
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input [WID-1:0] imm;
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input [WID-1:0] imm;
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output [WID*2-1:0] o;
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output [WID*2-1:0] o;
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reg [WID*2-1:0] o;
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reg [WID*2-1:0] o;
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output done;
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output done;
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output idle;
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reg [WID-1:0] aa,bb;
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reg [WID-1:0] aa,bb;
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reg so;
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reg so;
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reg [2:0] state;
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reg [2:0] state;
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reg [7:0] cnt;
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reg [7:0] cnt;
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wire cnt_done = cnt==8'd0;
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wire cnt_done = cnt==8'd0;
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assign done = state==DONE;
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assign done = state==DONE;
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assign idle = state==IDLE;
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reg ce1;
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reg ce1;
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reg [WID*2-1:0] prod;
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reg [WID*2-1:0] prod;
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//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
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//wire [64:0] p1 = aa[0] ? prod[127:64] + b : prod[127:64];
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//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
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//wire [65:0] p2 = aa[1] ? p1 + {b,1'b0} : p1;
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wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
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wire [WID+WID/4-1:0] p1 = bb * aa[WID/4-1:0] + prod[WID*2-1:WID];
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initial begin
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initial begin
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prod = 64'd0;
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prod = 64'd0;
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o = 64'd0;
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o = 64'd0;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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aa <= {WID{1'b0}};
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aa <= {WID{1'b0}};
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bb <= {WID{1'b0}};
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bb <= {WID{1'b0}};
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prod <= {WID*2{1'b0}};
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prod <= {WID*2{1'b0}};
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o <= {WID*2{1'b0}};
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o <= {WID*2{1'b0}};
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state <= IDLE;
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state <= IDLE;
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end
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end
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else
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else
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begin
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begin
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if (!cnt_done)
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if (abort)
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cnt <= 8'd00;
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else if (!cnt_done)
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cnt <= cnt - 8'd1;
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cnt <= cnt - 8'd1;
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case(state)
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case(state)
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IDLE:
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IDLE:
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if (ld) begin
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if (ld) begin
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if (sgn) begin
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if (sgn) begin
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aa <= a[WID-1] ? -a : a;
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aa <= a[WID-1] ? -a : a;
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bb <= isMuli ? (imm[WID-1] ? -imm : imm) :(b[WID-1] ? -b : b);
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bb <= isMuli ? (imm[WID-1] ? -imm : imm) :(b[WID-1] ? -b : b);
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so <= isMuli ? a[WID-1] ^ imm[WID-1] : a[WID-1] ^ b[WID-1];
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so <= isMuli ? a[WID-1] ^ imm[WID-1] : a[WID-1] ^ b[WID-1];
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end
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end
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else begin
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else begin
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aa <= a;
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aa <= a;
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bb <= isMuli ? imm : b;
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bb <= isMuli ? imm : b;
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so <= 1'b0;
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so <= 1'b0;
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end
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end
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prod <= {WID*2{1'b0}};
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prod <= {WID*2{1'b0}};
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cnt <= 8'd4;
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cnt <= 8'd4;
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state <= MULT;
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state <= MULT;
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end
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end
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MULT:
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MULT:
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if (!cnt_done) begin
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if (!cnt_done) begin
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aa <= {16'b0,aa[WID-1:WID/4]};
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aa <= {16'b0,aa[WID-1:WID/4]};
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prod <= {16'b0,prod[WID*2-1:WID/4]};
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prod <= {16'b0,prod[WID*2-1:WID/4]};
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prod[WID*2-1:WID*3/4] <= p1;
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prod[WID*2-1:WID*3/4] <= p1;
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end
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end
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else begin
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else begin
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if (sgn) begin
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if (sgn) begin
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if (so)
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if (so)
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o <= -prod;
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o <= -prod;
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else
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else
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o <= prod;
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o <= prod;
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end
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end
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else
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else
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o <= prod;
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o <= prod;
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state <= DONE;
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state <= DONE;
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end
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end
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default:
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default:
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state <= IDLE;
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state <= IDLE;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module Thor_multiplier_tb();
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module Thor_multiplier_tb();
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg ld;
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reg ld;
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wire [127:0] o;
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wire [127:0] o;
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initial begin
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initial begin
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clk = 1;
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clk = 1;
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rst = 0;
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rst = 0;
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#100 rst = 1;
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#100 rst = 1;
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#100 rst = 0;
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#100 rst = 0;
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#100 ld = 1;
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#100 ld = 1;
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#150 ld = 0;
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#150 ld = 0;
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end
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end
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always #10 clk = ~clk; // 50 MHz
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always #10 clk = ~clk; // 50 MHz
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Thor_multiplier u1
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Thor_multiplier u1
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(
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(
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.rst(rst),
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.rst(rst),
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.clk(clk),
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.clk(clk),
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.ld(ld),
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.ld(ld),
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.sgn(1'b0),
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.sgn(1'b0),
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.isMuli(1'b1),
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.isMuli(1'b1),
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.a(64'd56),
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.a(64'd56),
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.b(64'd0),
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.b(64'd0),
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.imm(64'd27),
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.imm(64'd27),
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.o(o)
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.o(o)
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);
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);
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endmodule
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endmodule
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