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[/] [tiny_aes/] [trunk/] [testbench/] [test_aes_192.v] - Diff between revs 6 and 9

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/*
/*
 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
 *
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * You may obtain a copy of the License at
 *
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *
 * Unless required by applicable law or agreed to in writing, software
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * See the License for the specific language governing permissions and
 * limitations under the License.
 * limitations under the License.
 */
 */
 
 
`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
module test_aes_192;
module test_aes_192;
 
 
        // Inputs
        // Inputs
        reg clk;
        reg clk;
        reg [127:0] state;
        reg [127:0] state;
        reg [191:0] key;
        reg [191:0] key;
 
 
        // Outputs
        // Outputs
        wire [127:0] out;
        wire [127:0] out;
 
 
        // Instantiate the Unit Under Test (UUT)
        // Instantiate the Unit Under Test (UUT)
        aes_192 uut (
        aes_192 uut (
                .clk(clk),
                .clk(clk),
                .state(state),
                .state(state),
                .key(key),
                .key(key),
                .out(out)
                .out(out)
        );
        );
 
 
        initial begin
        initial begin
                clk = 0;
                clk = 0;
                state = 0;
                state = 0;
                key = 0;
                key = 0;
 
 
                #100;
                #100;
 
        /*
 
         * TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
 
         * TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
 
         * TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
 
         */
        @ (negedge clk);
        @ (negedge clk);
 
        #2;
        state = 128'h3243f6a8885a308d313198a2e0370734;
        state = 128'h3243f6a8885a308d313198a2e0370734;
        key   = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
        key   = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
        #10;
        #10;
        state = 128'h00112233445566778899aabbccddeeff;
        state = 128'h00112233445566778899aabbccddeeff;
        key   = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
        key   = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
        #10;
        #10;
        state = 128'h0;
        state = 128'h0;
        key   = 192'h0;
        key   = 192'h0;
        #230;
        #230;
        if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
        if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
          begin $display("E"); $finish; end
          begin $display("E"); $finish; end
        #10;
        #10;
        if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
        if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
          begin $display("E"); $finish; end
          begin $display("E"); $finish; end
        $display("Good.");
        $display("Good.");
        $finish;
        $finish;
        end
        end
 
 
    always #5 clk = ~clk;
    always #5 clk = ~clk;
endmodule
endmodule
 
 
 
 

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