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/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`define P 20
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`define P 20
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module test_pe;
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module test_pe;
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// Inputs
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// Inputs
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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reg [10:0] ctrl;
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reg [10:0] ctrl;
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reg [197:0] d0;
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reg [197:0] d0;
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reg [193:0] d1;
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reg [193:0] d1;
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reg [193:0] d2;
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reg [193:0] d2;
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reg [193:0] wish;
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reg [193:0] wish;
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// Outputs
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// Outputs
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wire [193:0] out;
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wire [193:0] out;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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PE uut (
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PE uut (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.ctrl(ctrl),
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.ctrl(ctrl),
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.d0(d0),
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.d0(d0),
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.d1(d1),
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.d1(d1),
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.d2(d2),
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.d2(d2),
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.out(out)
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.out(out)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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clk = 0;
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clk = 0;
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reset = 0;
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reset = 0;
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ctrl = 0;
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ctrl = 0;
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d0 = 0;
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d0 = 0;
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d1 = 0;
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d1 = 0;
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d2 = 0;
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d2 = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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// test mult
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// test mult
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d0 = 194'h15a25886512165251569195908560596a6695612620504191;
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d0 = 194'h15a25886512165251569195908560596a6695612620504191;
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d1 = 194'h159546442405a181195655549614540592955a15a26984015;
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d1 = 194'h159546442405a181195655549614540592955a15a26984015;
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d2 = d1;
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d2 = d1;
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wish = 194'h21019120440545215a1462a194a24a6019441081402410969;
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wish = 194'h21019120440545215a1462a194a24a6019441081402410969;
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@(negedge clk);
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@(negedge clk);
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reset=1;#`P reset=0;
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reset=1;#`P reset=0;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b00000_111111; #(33*`P);
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ctrl=11'b00000_111111; #(33*`P);
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check;
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check;
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// test cubic
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// test cubic
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d0 = {6'b10101, 192'd0};
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d0 = {6'b10101, 192'd0};
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d1 = 194'h0894286a45940549565566512aa04a15558406850485454a4;
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d1 = 194'h0894286a45940549565566512aa04a15558406850485454a4;
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d2 = d1;
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d2 = d1;
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wish = 194'h1049480a48a0855a494855810160a90956659914560616652;
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wish = 194'h1049480a48a0855a494855810160a90956659914560616652;
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@(negedge clk);
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@(negedge clk);
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reset=1;#`P reset=0;
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reset=1;#`P reset=0;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b11111_000000; #`P;
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ctrl=1; #(33*`P);
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ctrl=1; #(33*`P);
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check;
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check;
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// test add
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// test add
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d0 = {6'b000101, 192'd0};
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d0 = {6'b000101, 192'd0};
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d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
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d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
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d2 = 194'h1901269451681914415481656104980811a5a555155546949;
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d2 = 194'h1901269451681914415481656104980811a5a555155546949;
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wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
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wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
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@(negedge clk);
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@(negedge clk);
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reset=1;#`P reset=0;
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reset=1;#`P reset=0;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b10001; #(33*`P);
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ctrl=11'b10001; #(33*`P);
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check;
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check;
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// test sub
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// test sub
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d0 = {6'b001001, 192'd0};
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d0 = {6'b001001, 192'd0};
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d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
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d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
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d2 = 194'h1901269451681914415481656104980811a5a555155546949;
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d2 = 194'h1901269451681914415481656104980811a5a555155546949;
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wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
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wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
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@(negedge clk);
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@(negedge clk);
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reset=1;#`P reset=0;
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reset=1;#`P reset=0;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b11111_000000; #`P;
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ctrl=11'b10001; #(33*`P);
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ctrl=11'b10001; #(33*`P);
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check;
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check;
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$display("Good!");
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$display("Good!");
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$finish;
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$finish;
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end
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end
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initial #100 forever #(`P/2) clk = ~clk;
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initial #100 forever #(`P/2) clk = ~clk;
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task check;
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task check;
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begin
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begin
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if (out !== wish)
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if (out !== wish)
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begin $display("E %h %h", out, wish); $finish; end
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begin $display("E %h %h", out, wish); $finish; end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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