This is the design of TinyCPU. It's goals are as follows:
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This is the design of TinyCPU. It's goals are as follows:
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1. 8-bit registers and operations (8 bit processor)
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1. 8-bit registers and operations (8 bit processor)
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2. 16-bit address bus
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2. 16-bit address bus
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3. fixed 16-bit instruction length
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3. fixed 16-bit instruction length
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4. use a small amount of "rich" instructions to do powerful things
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4. use a small amount of "rich" instructions to do powerful things
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5. 1 instruction per clock cycle
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5. 1 instruction per clock cycle
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Relative moves:
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In order to provide uesfulness to the segment-carryover feature, there are a few options for moving a "relative" amount to a register, including IP and SP
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A relative move differs in most of the opcodes in that the relative factor is treated as a signed value.
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so for instance, a
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mov r0,50
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mov_relative r0, -10
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in the ned, r0 will end up being 40. Although this feature won't see much use in general registers, IP and SP are special because of the option of using the
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segment-carryover feature. This means that SP and IP, while being 8-bit registers, can function very similar to a 16-bit register, enabling full usage of the available address space.
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Register list:
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Register list:
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r0-r5 general purpose registers
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r0-r5 general purpose registers
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sp stack pointer (represented as r6)
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sp stack pointer (represented as r6)
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ip instruction pointer register (represented as r7)
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ip instruction pointer register (represented as r7)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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cs, ds, es, ss segment registers (code segment, data segment, extra segment, stack segment)
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tr truth register for conditionals
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tr truth register for conditionals
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general opcode format
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general opcode format
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first byte:
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first byte:
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first 4 bits: actual instruction
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first 4 bits: actual instruction
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next 3 bits: (target) register
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next 3 bits: (target) register
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last 1 bit: conditional
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last 1 bit: conditional
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second byte:
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second byte:
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first 1 bit: second portion of condition (if not immediate) (1 for only if false)
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first 1 bit: second portion of condition (if not immediate) (1 for only if false)
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next 1 bit: use extra segment
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next 1 bit: use extra segment
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next 3 bits: other register
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next 3 bits: other register. If not 3rd register, top bit specifies which register bank, others unused
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last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register
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last 3 bits: extra opcode information or third register. such as for ADD it could be target=source+third_register
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...or second byte is immediate value
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...or second byte is immediate value
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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For opcodes requiring 3 registers but without room, the target opcode is assume to be the second operation. Such as for AND, target=source AND target
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short list of instructions: (not final, still planning)
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short list of instructions: (not final, still planning)
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immediates:
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immediates:
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1. move reg, immediate
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1. move reg, immediate
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2. move [reg], immediate
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2. move [reg], immediate
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3. push and move reg, immediate (or call immediate)
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3. push and move reg, immediate (or call immediate)
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4. push immediate
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4. push immediate
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5. jmp immediate
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5. mov (relative) immediate
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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groups: (limited to 2 registers and no immediates. each group has 8 opcodes)
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group 1:
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group 1:
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move(store) [reg],reg
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move(store) [reg],reg
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move(load) reg,[reg]
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move(load) reg,[reg]
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out reg1,reg2 (output to port reg1 value reg2)
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out reg1,reg2 (output to port reg1 value reg2)
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in reg1,reg2 (input from port reg2 and store in reg1)
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in reg1,reg2 (input from port reg2 and store in reg1)
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pop reg
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pop reg
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push reg
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push reg
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move segmentreg,reg
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move segmentreg,reg
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move reg,segmentreg
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move reg,segmentreg
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group 2:
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group 2:
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and reg1,reg2 (reg1=reg1 and reg2)
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and reg1,reg2 (reg1=reg1 and reg2)
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or reg, reg
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or reg, reg
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xor reg,reg
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xor reg,reg
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not reg1,reg2 (reg1=not reg2)
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not reg1,reg2 (reg1=not reg2)
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left shift reg,reg
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left shift reg,reg
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right shift reg,reg
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right shift reg,reg
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rotate right reg,reg
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rotate right reg,reg
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rotate left reg,reg
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rotate left reg,reg
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group 3: compares
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group 3: compares
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is greater than reg1,reg2 (TR=reg1>reg2)
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is greater than reg1,reg2 (TR=reg1>reg2)
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is greater or equal to reg,reg
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is greater or equal to reg,reg
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is less than reg,reg
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is less than reg,reg
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is less than or equal to reg,reg
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is less than or equal to reg,reg
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is equal to reg,reg
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is equal to reg,reg
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is not equal to reg,reg
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is not equal to reg,reg
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equals 0 reg
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equals 0 reg
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not equals 0 reg
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not equals 0 reg
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group 4:
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group 4:
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push segmentreg
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push segmentreg
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pop segmentreg
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pop segmentreg
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push and move reg, reg (or call reg)
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push and move reg, reg (or call reg)
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exchange reg,reg
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exchange reg,reg
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exchange reg,seg
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exchange reg,seg
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clear TR
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clear TR
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Set TR
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Set TR
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group 5:
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group 5:
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increment reg
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increment reg
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decrement reg
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decrement reg
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far jmp reg1, reg2 (CS=reg1 and IP=reg2)
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far jmp reg1, reg2 (CS=reg1 and IP=reg2)
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far call reg1,reg2
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far call reg1,reg2
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far jmp [reg] (first byte is CS, second byte is IP)
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far jmp [reg] (first byte is CS, second byte is IP)
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push extended segmentreg, reg (equivalent to push seg; push reg)
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push extended segmentreg, reg (equivalent to push seg; push reg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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pop extended segmentreg, reg (equivalent to pop reg; pop seg)
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reset processor (will completely reset the processor to starting state, but not RAM or anything else)
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reset processor (will completely reset the processor to starting state, but not RAM or anything else)
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group 6:
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group 6:
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set register bank 0
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set default register bank to 0 (can be condensed to 1 opcode)
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set register bank 1
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set default register bank to 1
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push extended reg, reg
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push extended reg, reg
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pop extended reg,reg
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pop extended reg,reg
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enable carryover seg
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disable CS carryover seg
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mov relative reg, reg
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exchange reg, reg
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3 register instructions:
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3 register instructions:
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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1. add reg1, reg2, reg3 (reg1=reg2+reg3)
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2. sub reg1, reg2, reg3
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2. sub reg1, reg2, reg3
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opcodes used: 12 of 16. 4 more opcodes available. Decide what to do with the room later.
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opcodes used: 12 of 16. 4 more opcodes available. Decide what to do with the room later.
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0 -nop (doesn't do a thing)
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0 -nop (doesn't do a thing)
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1 -move immediate (only uses first byte)
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1 -move immediate (only uses first byte)
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2 -move
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2 -move
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3 -push
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3 -push
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4 -push immediate
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4 -push immediate
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5 -push and move (or call when acting on ip)
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5 -push and move (or call when acting on ip)
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6 -compare (is less than, is less than or equal, is greater than, is greater than or equal, is equal, is not equal) (6 conditions room for 2 more in extra)
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6 -compare (is less than, is less than or equal, is greater than, is greater than or equal, is equal, is not equal) (6 conditions room for 2 more in extra)
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7 -add
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7 -add
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8 -subtract
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8 -subtract
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9 -bitwise operations (xor, or, and, shift right, shift left, not)
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9 -bitwise operations (xor, or, and, shift right, shift left, not)
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x -multiply (if room)
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x -multiply (if room)
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x -divide
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x -divide
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conditionals
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conditionals
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0 -- always
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0 -- always
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1 -- only if true
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1 -- only if true
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for only if false, there should basically be another compare or if applicable an always afterwards
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for only if false, there should basically be another compare or if applicable an always afterwards
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push
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push
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pop
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pop
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move
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move
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add
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add
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sub
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sub
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limitations that shouldn't be passed with instructions
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limitations that shouldn't be passed with instructions
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* Doing 2 memory references
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* Doing 2 memory references
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* pushing a memory reference (equates to 2 memory references)
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* pushing a memory reference (equates to 2 memory references)
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Note it is possible however to read and write 16bits at one time to the memory to consecutive addresses.
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Note it is possible however to read and write 16bits at one time to the memory to consecutive addresses.
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segments:
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segments:
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DS is used in all "normal" memory references
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DS is used in all "normal" memory references
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SS is used in all push and pop instructions
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SS is used in all push and pop instructions
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ES is used when the ExtraSegment bit is set for either push/pop or normal memory references
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ES is used when the ExtraSegment bit is set for either push/pop or normal memory references
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CS is only used for fetching instructions
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CS is only used for fetching instructions
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Segment carryover:
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In order to overcome the limitations of only having a 256 byte segment, there is a workaround option to "pretend" that IP is a 16 bit register.
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When CS carryover is enabled, when IP rollover from 255 to 0 or whatever, CS will be incremented. This makes it so that if you start at address 0:0.
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you can continue as far as needed into the address space without having to do ugly far jumps at each of the borders.
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States needed:
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States needed:
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0. reset
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0. reset
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1. decode current instruction (All without memory capable within 1 clock cycle)
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1. decode current instruction (All without memory capable within 1 clock cycle)
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2. increment IP(and SP if needed) and fetch next instruction
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2. increment IP(and SP if needed) and fetch next instruction
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3. Write 1 register to memory
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3. Write 1 register to memory
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4. Read 1 register from memory
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4. Read 1 register from memory
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5. Write 2 registers to memory
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5. Write 2 registers to memory
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6. Read 2 registers from memory
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6. Read 2 registers from memory
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7. Write 1 register to memory and setup increment of sp
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7. Write 1 register to memory and setup increment of sp
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8. Write 2 registers to memory and setup double increment of sp
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8. Write 2 registers to memory and setup double increment of sp
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9. Read 1 register from memory and setup decrement of sp
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9. Read 1 register from memory and setup decrement of sp
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10. Read 2 registers from memory and setup double decrement of sp
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10. Read 2 registers from memory and setup double decrement of sp
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11.
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11.
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registerfile map:
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registerfile map:
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0000: general r0
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0000: general r0
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0001: general r1
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0001: general r1
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0010: general r2
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0010: general r2
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0011: general r3
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0011: general r3
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0100: general r4
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0100: general r4
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0101: general r5
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0101: general r5
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0110: SP (r6)
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0110: SP (r6)
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0111: IP (r7)
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0111: IP (r7)
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1000: second bank r0
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1000: second bank r0
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1001: second bank r1
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1001: second bank r1
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1010: second bank r2
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1010: second bank r2
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1011: second bank r3
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1011: second bank r3
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1100: CS
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1100: CS
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1101: DS
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1101: DS
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1110: ES
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1110: ES
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1111: SS
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1111: SS
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Banking works like if(regnumber(2) = '0') then regnumber(3)=regbank; end if;
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Banking works like if(regnumber(2) = '0') then regnumber(3)=regbank; end if;
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ALU operations
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ALU operations
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00000 and reg1,reg2 (reg1=reg1 and reg2)
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00000 and reg1,reg2 (reg1=reg1 and reg2)
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00001 or reg, reg
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00001 or reg, reg
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00010 xor reg,reg
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00010 xor reg,reg
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00011 not reg1,reg2 (reg1=not reg2)
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00011 not reg1,reg2 (reg1=not reg2)
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00100 left shift reg,reg (logical)
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00100 left shift reg,reg (logical)
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00101 right shift reg,reg (logical)
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00101 right shift reg,reg (logical)
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00110 rotate right reg,reg
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00110 rotate right reg,reg
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00111 rotate left reg,reg
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00111 rotate left reg,reg
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01000 is greater than reg1,reg2 (TR=reg1>reg2)
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01000 is greater than reg1,reg2 (TR=reg1>reg2)
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01001 is greater or equal to reg,reg
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01001 is greater or equal to reg,reg
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01010 is less than reg,reg
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01010 is less than reg,reg
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01011 is less than or equal to reg,reg
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01011 is less than or equal to reg,reg
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01100 is equal to reg,reg
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01100 is equal to reg,reg
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01101 is not equal to reg,reg
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01101 is not equal to reg,reg
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01110 equals 0 reg
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01110 equals 0 reg
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01111 not equals 0 reg
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01111 not equals 0 reg
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10000 Set TR
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10000 Set TR
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10001 Reset TR
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10001 Reset TR
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10011 Increment
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10011 Increment
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10010 Decrement
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10010 Decrement
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10100 Add
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10100 Add
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10101 Subtract
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10101 Subtract
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