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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.tinycpu.all;
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use work.tinycpu.all;
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entity alu is
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entity alu is
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port(
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port(
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Op: in std_logic_vector(4 downto 0);
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Op: in std_logic_vector(4 downto 0);
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DataIn1: in std_logic_vector(7 downto 0);
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DataIn1: in std_logic_vector(7 downto 0);
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DataIn2: in std_logic_vector(7 downto 0);
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DataIn2: in std_logic_vector(7 downto 0);
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DataOut: out std_logic_vector(7 downto 0);
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DataOut: out std_logic_vector(7 downto 0);
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TR: out std_logic
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TR: out std_logic
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);
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);
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end alu;
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end alu;
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architecture Behavioral of alu is
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architecture Behavioral of alu is
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signal TRData: std_logic;
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signal TRData: std_logic;
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begin
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begin
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TR <= TRData;
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TR <= TRData;
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process(DataIn1, DataIn2, Op)
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process(DataIn1, DataIn2, Op)
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begin
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begin
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--TRData <='0'; --default
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case Op is
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case Op is
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--bitwise operations
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--bitwise operations
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when "00000" => --and
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when "00000" => --and
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DataOut <= DataIn1 and DataIn2;
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DataOut <= DataIn1 and DataIn2;
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when "00001" => --or
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when "00001" => --or
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DataOut <= DataIn1 or DataIn2;
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DataOut <= DataIn1 or DataIn2;
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when "00010" => --xor
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when "00010" => --xor
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DataOut <= DataIn1 xor DataIn2;
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DataOut <= DataIn1 xor DataIn2;
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when "00011" => --not
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when "00011" => --not
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DataOut <= not DataIn2; --ignore DataIn1 here so that mapping these operations is as simple as possible
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DataOut <= not DataIn2; --ignore DataIn1 here so that mapping these operations is as simple as possible
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when "00100" => --left shift (logical)
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when "00100" => --left shift (logical)
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DataOut <= std_logic_vector(shift_left(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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DataOut <= std_logic_vector(shift_left(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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when "00101" => --right shift(logical)
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when "00101" => --right shift(logical)
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DataOut <= std_logic_vector(shift_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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DataOut <= std_logic_vector(shift_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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when "00110" => --left rotate
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when "00110" => --left rotate
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DataOut <= std_logic_vector(rotate_left(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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DataOut <= std_logic_vector(rotate_left(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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when "00111" => --right rotate
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when "00111" => --right rotate
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DataOut <= std_logic_vector(rotate_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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DataOut <= std_logic_vector(rotate_right(unsigned(DataIn1),to_integer(unsigned(DataIn2(2 downto 0)))));
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--comparisons
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--comparisons
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when "01000" => --greater than
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when "01000" => --greater than
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) > to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) > to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01001" => --greater than or equal
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when "01001" => --greater than or equal
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) >= to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) >= to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01010" => --less than
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when "01010" => --less than
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) < to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) < to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01011" => --less than or equal
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when "01011" => --less than or equal
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) <= to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) <= to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01100" => --equals to
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when "01100" => --equals to
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) = to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) = to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01101" => --not equal
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when "01101" => --not equal
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) /= to_integer(unsigned(DataIn2))) then
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if(to_integer(unsigned(DataIn1)) /= to_integer(unsigned(DataIn2))) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01110" => --equal to 0
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when "01110" => --equal to 0
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) = 0) then
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if(to_integer(unsigned(DataIn1)) = 0) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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when "01111" => --not equal to 0
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when "01111" => --not equal to 0
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DataOut <= "00000000";
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DataOut <= "00000000";
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if(to_integer(unsigned(DataIn1)) /= 0) then
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if(to_integer(unsigned(DataIn1)) /= 0) then
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TRData <= '1';
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TRData <= '1';
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else
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else
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TRData <= '0';
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TRData <= '0';
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end if;
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end if;
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--other operations
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--other operations
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when "10000" => --set TR
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when "10000" => --set TR
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DataOut <= "00000000";
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DataOut <= "00000000";
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TRData <= '1';
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TRData <= '1';
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when "10001" => --reset TR
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when "10001" => --reset TR
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DataOut <= "00000000";
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DataOut <= "00000000";
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TRData <= '0';
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TRData <= '0';
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when "10010" => --increment
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when "10010" => --increment
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DataOut <= std_logic_vector(unsigned(DataIn1) + 1);
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DataOut <= std_logic_vector(unsigned(DataIn1) + 1);
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when "10011" => --decrement
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when "10011" => --decrement
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DataOut <= std_logic_vector(unsigned(DataIn1) - 1);
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DataOut <= std_logic_vector(unsigned(DataIn1) - 1);
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when "10100" => --add
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when "10100" => --add
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DataOut <= std_logic_vector(unsigned(DataIn1) + unsigned(DataIn2));
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DataOut <= std_logic_vector(unsigned(DataIn1) + unsigned(DataIn2));
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when "10101" => --subtract
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when "10101" => --subtract
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DataOut <= std_logic_vector(unsigned(DataIn1) - unsigned(DataIn2));
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DataOut <= std_logic_vector(unsigned(DataIn1) - unsigned(DataIn2));
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when others =>
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when others =>
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DataOut <= "00000000";
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DataOut <= "00000000";
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TRData <= '1';
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TRData <= '1';
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end case;
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end case;
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end process;
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end process;
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