--Core module.
|
--Core module.
|
--This module is basically connects everything and decodes the opcodes.
|
--This module is basically connects everything and decodes the opcodes.
|
--The only thing above this is toplevel.vhd which actually sets the pinout for the FPGA
|
--The only thing above this is toplevel.vhd which actually sets the pinout for the FPGA
|
|
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use work.tinycpu.all;
|
use work.tinycpu.all;
|
|
|
entity core is
|
entity core is
|
port(
|
port(
|
--memory interface
|
--memory interface
|
MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
|
MemAddr: out std_logic_vector(15 downto 0); --memory address (in bytes)
|
MemWW: out std_logic; --memory writeword
|
MemWW: out std_logic; --memory writeword
|
MemWE: out std_logic; --memory writeenable
|
MemWE: out std_logic; --memory writeenable
|
MemIn: in std_logic_vector(15 downto 0);
|
MemIn: in std_logic_vector(15 downto 0);
|
MemOut: out std_logic_vector(15 downto 0);
|
MemOut: out std_logic_vector(15 downto 0);
|
--general interface
|
--general interface
|
Clock: in std_logic;
|
Clock: in std_logic;
|
Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
|
Reset: in std_logic; --When this is high, CPU will reset within 1 clock cycles.
|
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
|
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
|
Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
|
Hold: in std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
|
HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
|
HoldAck: out std_logic; --when high, CPU acknowledged hold and buses are in high Z
|
--todo: port interface
|
--todo: port interface
|
|
|
--debug ports:
|
--debug ports:
|
DebugIR: out std_logic_vector(15 downto 0); --current instruction
|
DebugIR: out std_logic_vector(15 downto 0); --current instruction
|
DebugIP: out std_logic_vector(7 downto 0); --current IP
|
DebugIP: out std_logic_vector(7 downto 0); --current IP
|
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
DebugCS: out std_logic_vector(7 downto 0); --current code segment
|
DebugTR: out std_logic; --current value of TR
|
DebugTR: out std_logic; --current value of TR
|
DebugR0: out std_logic_vector(7 downto 0)
|
DebugR0: out std_logic_vector(7 downto 0)
|
);
|
);
|
end core;
|
end core;
|
|
|
architecture Behavioral of core is
|
architecture Behavioral of core is
|
component fetch is
|
component fetch is
|
port(
|
port(
|
Enable: in std_logic;
|
Enable: in std_logic;
|
AddressIn: in std_logic_vector(15 downto 0);
|
AddressIn: in std_logic_vector(15 downto 0);
|
Clock: in std_logic;
|
Clock: in std_logic;
|
DataIn: in std_logic_vector(15 downto 0); --interface from memory
|
DataIn: in std_logic_vector(15 downto 0); --interface from memory
|
IROut: out std_logic_vector(15 downto 0);
|
IROut: out std_logic_vector(15 downto 0);
|
AddressOut: out std_logic_vector(15 downto 0) --interface to memory
|
AddressOut: out std_logic_vector(15 downto 0) --interface to memory
|
);
|
);
|
end component;
|
end component;
|
component alu is
|
component alu is
|
port(
|
port(
|
Op: in std_logic_vector(4 downto 0);
|
Op: in std_logic_vector(4 downto 0);
|
DataIn1: in std_logic_vector(7 downto 0);
|
DataIn1: in std_logic_vector(7 downto 0);
|
DataIn2: in std_logic_vector(7 downto 0);
|
DataIn2: in std_logic_vector(7 downto 0);
|
DataOut: out std_logic_vector(7 downto 0);
|
DataOut: out std_logic_vector(7 downto 0);
|
TR: out std_logic
|
TR: out std_logic
|
);
|
);
|
end component;
|
end component;
|
component carryover is
|
component carryover is
|
port(
|
port(
|
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
|
EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
|
DataIn: in std_logic_vector(7 downto 0);
|
DataIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
SegmentIn: in std_logic_vector(7 downto 0);
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
|
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
|
DataOut: out std_logic_vector(7 downto 0);
|
DataOut: out std_logic_vector(7 downto 0);
|
SegmentOut: out std_logic_vector(7 downto 0);
|
SegmentOut: out std_logic_vector(7 downto 0);
|
Clock: in std_logic
|
Clock: in std_logic
|
);
|
);
|
end component;
|
end component;
|
component registerfile is
|
component registerfile is
|
port(
|
port(
|
WriteEnable: in regwritetype;
|
WriteEnable: in regwritetype;
|
DataIn: in regdatatype;
|
DataIn: in regdatatype;
|
Clock: in std_logic;
|
Clock: in std_logic;
|
DataOut: out regdatatype
|
DataOut: out regdatatype
|
);
|
);
|
end component;
|
end component;
|
|
|
constant REGIP: integer := 7;
|
constant REGIP: integer := 7;
|
constant REGSP: integer := 6;
|
constant REGSP: integer := 6;
|
constant REGSS: integer := 15;
|
constant REGSS: integer := 15;
|
constant REGES: integer := 14;
|
constant REGES: integer := 14;
|
constant REGDS: integer := 13;
|
constant REGDS: integer := 13;
|
constant REGCS: integer := 12;
|
constant REGCS: integer := 12;
|
|
|
type ProcessorState is (
|
type ProcessorState is (
|
ResetProcessor,
|
ResetProcessor,
|
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
FirstFetch1, --the fetcher needs two clock cycles to catch up
|
FirstFetch2,
|
FirstFetch2,
|
Firstfetch3,
|
Firstfetch3,
|
Execute,
|
Execute,
|
WaitForMemory,
|
WaitForMemory,
|
HoldMemory
|
HoldMemory
|
);
|
);
|
signal state: ProcessorState;
|
signal state: ProcessorState;
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
|
|
|
--carryout signals
|
--carryout signals
|
signal CarryCS: std_logic;
|
signal CarryCS: std_logic;
|
signal CarrySS: std_logic;
|
signal CarrySS: std_logic;
|
signal IPAddend: std_logic_vector(7 downto 0);
|
signal IPAddend: std_logic_vector(7 downto 0);
|
signal SPAddend: std_logic_vector(7 downto 0);
|
signal SPAddend: std_logic_vector(7 downto 0);
|
signal IPCarryOut: std_logic_vector(7 downto 0);
|
signal IPCarryOut: std_logic_vector(7 downto 0);
|
signal CSCarryOut: std_logic_vector(7 downto 0);
|
signal CSCarryOut: std_logic_vector(7 downto 0);
|
signal SPCarryOut: std_logic_vector(7 downto 0);
|
signal SPCarryOut: std_logic_vector(7 downto 0);
|
signal SSCarryOut: std_logic_vector(7 downto 0);
|
signal SSCarryOut: std_logic_vector(7 downto 0);
|
|
|
--register signals
|
--register signals
|
signal regWE:regwritetype;
|
signal regWE:regwritetype;
|
signal regIn: regdatatype;
|
signal regIn: regdatatype;
|
signal regOut: regdatatype;
|
signal regOut: regdatatype;
|
--fetch signals
|
--fetch signals
|
signal fetchEN: std_logic;
|
signal fetchEN: std_logic;
|
signal IR: std_logic_vector(15 downto 0);
|
signal IR: std_logic_vector(15 downto 0);
|
--alu signals
|
--alu signals
|
signal AluOp: std_logic_vector(4 downto 0);
|
signal AluOp: std_logic_vector(4 downto 0);
|
signal AluIn1: std_logic_vector(7 downto 0);
|
signal AluIn1: std_logic_vector(7 downto 0);
|
signal AluIn2: std_logic_vector(7 downto 0);
|
signal AluIn2: std_logic_vector(7 downto 0);
|
signal AluOut: std_logic_vector(7 downto 0);
|
signal AluOut: std_logic_vector(7 downto 0);
|
signal TR: std_logic;
|
signal TR: std_logic;
|
|
|
--control signals
|
--control signals
|
signal InReset: std_logic;
|
signal InReset: std_logic;
|
signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
|
signal OpAddress: std_logic_vector(15 downto 0); --memory address to use for operation of an instruction
|
signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
|
signal OpData: std_logic_vector(15 downto 0); --data to write or will load to here
|
signal OpWW: std_logic;
|
signal OpWW: std_logic;
|
signal OpWE: std_logic;
|
signal OpWE: std_logic;
|
|
|
--opcode shortcut signals
|
--opcode shortcut signals
|
signal opmain: std_logic_vector(3 downto 0);
|
signal opmain: std_logic_vector(3 downto 0);
|
signal opimmd: std_logic_vector(7 downto 0);
|
signal opimmd: std_logic_vector(7 downto 0);
|
signal opcond1: std_logic; --first conditional bit
|
signal opcond1: std_logic; --first conditional bit
|
signal opcond2: std_logic; --second conditional bit
|
signal opcond2: std_logic; --second conditional bit
|
signal opreg1: std_logic_vector(2 downto 0);
|
signal opreg1: std_logic_vector(2 downto 0);
|
signal opreg2: std_logic_vector(2 downto 0);
|
signal opreg2: std_logic_vector(2 downto 0);
|
signal opreg3: std_logic_vector(2 downto 0);
|
signal opreg3: std_logic_vector(2 downto 0);
|
signal opseges: std_logic; --use ES segment
|
signal opseges: std_logic; --use ES segment
|
|
|
signal regbank: std_logic;
|
signal regbank: std_logic;
|
|
|
signal fetcheraddress: std_logic_vector(15 downto 0);
|
signal fetcheraddress: std_logic_vector(15 downto 0);
|
|
|
--temporary signals
|
|
signal tempreg1: std_logic_vector(3 downto 0);
|
signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in
|
signal tempreg2: std_logic_vector(3 downto 0);
|
signal bankreg2: std_logic_vector(3 downto 0);
|
signal tempreg3: std_logic_vector(3 downto 0);
|
signal bankreg3: std_logic_vector(3 downto 0);
|
signal FetchMemAddr: std_logic_vector(15 downto 0);
|
signal FetchMemAddr: std_logic_vector(15 downto 0);
|
|
|
|
|
begin
|
begin
|
reg: registerfile port map(
|
reg: registerfile port map(
|
WriteEnable => regWE,
|
WriteEnable => regWE,
|
DataIn => regIn,
|
DataIn => regIn,
|
Clock => Clock,
|
Clock => Clock,
|
DataOut => regOut
|
DataOut => regOut
|
);
|
);
|
carryovercs: carryover port map(
|
carryovercs: carryover port map(
|
EnableCarry => CarryCS,
|
EnableCarry => CarryCS,
|
DataIn => regIn(REGIP),
|
DataIn => regIn(REGIP),
|
SegmentIn => regIn(REGCS),
|
SegmentIn => regIn(REGCS),
|
Addend => IPAddend,
|
Addend => IPAddend,
|
DataOut => IPCarryOut,
|
DataOut => IPCarryOut,
|
SegmentOut => CSCarryOut,
|
SegmentOut => CSCarryOut,
|
Clock => Clock
|
Clock => Clock
|
);
|
);
|
carryoverss: carryover port map(
|
carryoverss: carryover port map(
|
EnableCarry => CarrySS,
|
EnableCarry => CarrySS,
|
DataIn => regIn(REGSP),
|
DataIn => regIn(REGSP),
|
SegmentIn => RegIn(REGSS),
|
SegmentIn => RegIn(REGSS),
|
Addend => SPAddend,
|
Addend => SPAddend,
|
DataOut => SPCarryOut,
|
DataOut => SPCarryOut,
|
SegmentOut => SSCarryOut,
|
SegmentOut => SSCarryOut,
|
Clock => Clock
|
Clock => Clock
|
);
|
);
|
fetcher: fetch port map(
|
fetcher: fetch port map(
|
Enable => fetchEN,
|
Enable => fetchEN,
|
AddressIn => fetcheraddress,
|
AddressIn => fetcheraddress,
|
Clock => Clock,
|
Clock => Clock,
|
DataIn => MemIn,
|
DataIn => MemIn,
|
IROut => IR,
|
IROut => IR,
|
AddressOut => FetchMemAddr
|
AddressOut => FetchMemAddr
|
);
|
);
|
cpualu: alu port map(
|
cpualu: alu port map(
|
Op => AluOp,
|
Op => AluOp,
|
DataIn1 => AluIn1,
|
DataIn1 => AluIn1,
|
DataIn2 => AluIn2,
|
DataIn2 => AluIn2,
|
DataOut => AluOut,
|
DataOut => AluOut,
|
TR => TR
|
TR => TR
|
);
|
);
|
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
|
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
|
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
|
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else x"0000";
|
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else x"0000";
|
MemWE <= OpWE when state=WaitForMemory else '0';
|
MemWE <= OpWE when state=WaitForMemory else '0';
|
MemWW <= OpWW when state=WaitForMemory else '0';
|
MemWW <= OpWW when state=WaitForMemory else '0';
|
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
|
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
|
--opcode shortcuts
|
--opcode shortcuts
|
opmain <= IR(15 downto 12);
|
opmain <= IR(15 downto 12);
|
opimmd <= IR(7 downto 0);
|
opimmd <= IR(7 downto 0);
|
opcond1 <= IR(8);
|
opcond1 <= IR(8);
|
opcond2 <= IR(7);
|
opcond2 <= IR(7);
|
opreg1 <= IR(11 downto 9);
|
opreg1 <= IR(11 downto 9);
|
opreg3 <= IR(2 downto 0);
|
opreg3 <= IR(2 downto 0);
|
opreg2 <= IR(5 downto 3);
|
opreg2 <= IR(6 downto 4);
|
opseges <= IR(6);
|
opseges <= IR(3);
|
--debug ports
|
--debug ports
|
DebugCS <= regOut(REGCS);
|
DebugCS <= regOut(REGCS);
|
DebugIP <= regOut(REGIP);
|
DebugIP <= regOut(REGIP);
|
DebugR0 <= regOut(0);
|
DebugR0 <= regOut(0);
|
DebugIR <= IR;
|
DebugIR <= IR;
|
DebugTR <= TR;
|
DebugTR <= TR;
|
--register addresses with registerbank baked in
|
--register addresses with registerbank baked in
|
tempreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
|
bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
|
tempreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
|
bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
|
tempreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
|
bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
|
|
|
|
|
|
|
decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
|
decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
|
|
--states
|
--states
|
if reset='1' and hold='0' then
|
if reset='1' and hold='0' then
|
InReset <= '1';
|
InReset <= '1';
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
HoldAck <= '0';
|
HoldAck <= '0';
|
CarryCS <= '1';
|
CarryCS <= '1';
|
CarrySS <= '0';
|
CarrySS <= '0';
|
regWE <= (others => '1');
|
regWE <= (others => '1');
|
regIn <= (others => "00000000");
|
regIn <= (others => "00000000");
|
regIn(REGCS) <= x"01";
|
regIn(REGCS) <= x"01";
|
IPAddend <= x"00";
|
IPAddend <= x"00";
|
SPAddend <= x"00";
|
SPAddend <= x"00";
|
AluOp <= "10001"; --reset TR in ALU
|
AluOp <= "10001"; --reset TR in ALU
|
regbank <= '0';
|
regbank <= '0';
|
fetchEN <= '1';
|
fetchEN <= '1';
|
OpData <= "ZZZZZZZZZZZZZZZZ";
|
OpData <= "ZZZZZZZZZZZZZZZZ";
|
OpAddress <= x"0000";
|
OpAddress <= x"0000";
|
OpWE <= '0';
|
OpWE <= '0';
|
opWW <= '0';
|
opWW <= '0';
|
--finish up
|
--finish up
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
elsif InReset='1' and reset='0' and Hold='0' then --reset is done, start executing
|
InReset <= '0';
|
InReset <= '0';
|
fetchEN <= '1';
|
fetchEN <= '1';
|
state <= FirstFetch1;
|
state <= FirstFetch1;
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
elsif Hold = '1' and (state=HoldMemory or state=Execute or state=ResetProcessor) then
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
--do not hold immediately if waiting on memory or if waiting on the first fetch of an instruction after reset
|
state <= HoldMemory;
|
state <= HoldMemory;
|
HoldAck <= '1';
|
HoldAck <= '1';
|
FetchEN <= '0';
|
FetchEN <= '0';
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
MemAddr <= "ZZZZZZZZZZZZZZZZ";
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
MemOut <= "ZZZZZZZZZZZZZZZZ";
|
MemWE <= 'Z';
|
MemWE <= 'Z';
|
MemWW <= 'Z';
|
MemWW <= 'Z';
|
elsif Hold='0' and state=HoldMemory then
|
elsif Hold='0' and state=HoldMemory then
|
if reset='1' or InReset='1' then
|
if reset='1' or InReset='1' then
|
state <= ResetProcessor;
|
state <= ResetProcessor;
|
else
|
else
|
state <= Execute;
|
state <= Execute;
|
end if;
|
end if;
|
FetchEN <= '1';
|
FetchEN <= '1';
|
elsif state=FirstFetch1 then --we have to let IR get loaded before we can execute.
|
elsif state=FirstFetch1 then --we have to let IR get loaded before we can execute.
|
--regWE <= (others => '0');
|
--regWE <= (others => '0');
|
fetchEN <= '1'; --already enabled, but anyway
|
fetchEN <= '1'; --already enabled, but anyway
|
--regWE <= (others => '0');
|
--regWE <= (others => '0');
|
IPAddend <= x"02";
|
IPAddend <= x"02";
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
RegWE <= (others => '0');
|
RegWE <= (others => '0');
|
regIn(REGIP) <= IPCarryOut;
|
regIn(REGIP) <= IPCarryOut;
|
regWE(REGIP) <= '1';
|
regWE(REGIP) <= '1';
|
regWE(REGCS) <= '1';
|
regWE(REGCS) <= '1';
|
regIn(REGCS) <= CSCarryOut;
|
regIn(REGCS) <= CSCarryOut;
|
state <= Execute;
|
state <= Execute;
|
elsif state=FirstFetch2 then
|
elsif state=FirstFetch2 then
|
state <= FirstFetch3;
|
state <= FirstFetch3;
|
|
|
elsif state=FirstFetch3 then
|
elsif state=FirstFetch3 then
|
state <= Execute;
|
state <= Execute;
|
elsif state=WaitForMemory then
|
elsif state=WaitForMemory then
|
state <= Execute;
|
state <= Execute;
|
FetchEn <= '1';
|
FetchEn <= '1';
|
IpAddend <= x"02";
|
IpAddend <= x"02";
|
end if;
|
end if;
|
|
|
|
|
if state=Execute then
|
if state=Execute then
|
fetchEN <= '1';
|
fetchEN <= '1';
|
--reset to "usual"
|
--reset to "usual"
|
IPAddend <= x"02";
|
IPAddend <= x"02";
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
SPAddend <= x"00"; --no addend unless pushing or popping
|
RegWE <= (others => '0');
|
RegWE <= (others => '0');
|
regIn(REGIP) <= IPCarryOut;
|
regIn(REGIP) <= IPCarryOut;
|
regWE(REGIP) <= '1';
|
regWE(REGIP) <= '1';
|
regWE(REGCS) <= '1';
|
regWE(REGCS) <= '1';
|
regIn(REGCS) <= CSCarryOut;
|
regIn(REGCS) <= CSCarryOut;
|
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
|
regIn(REGSP) <= SPCarryOut; --with addend being 0, it'll just write SP to SP so it won't change, but this makes code easier for me
|
regIn(REGSS) <= SSCarryOut;
|
regIn(REGSS) <= SSCarryOut;
|
regWE(REGSP) <= '1';
|
regWE(REGSP) <= '1';
|
regWE(REGSS) <= '1';
|
regWE(REGSS) <= '1';
|
OpAddress <= "ZZZZZZZZZZZZZZZZ";
|
OpAddress <= "ZZZZZZZZZZZZZZZZ";
|
|
|
--actual decoding
|
--actual decoding
|
if opcond1='0' or (opcond1='1' and TR='1') then
|
if opcond1='0' or (opcond1='1' and TR='1') then
|
case opmain is
|
case opmain is
|
when "0000" => --mov reg,imm
|
when "0000" => --mov reg,imm
|
regIn(to_integer(unsigned(tempreg1))) <= opimmd;
|
regIn(to_integer(unsigned(bankreg1))) <= opimmd;
|
regWE(to_integer(unsigned(tempreg1))) <= '1';
|
regWE(to_integer(unsigned(bankreg1))) <= '1';
|
when "0001" => --mov [reg],imm
|
when "0001" => --mov [reg],imm
|
OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(tempreg1)));
|
OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
|
OpWE <= '1';
|
OpWE <= '1';
|
OpData <= x"00" & opimmd;
|
OpData <= x"00" & opimmd;
|
OpWW <= '0';
|
OpWW <= '0';
|
state <= WaitForMemory;
|
state <= WaitForMemory;
|
IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
|
IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory
|
FetchEN <= '0';
|
FetchEN <= '0';
|
|
when "0011" => --group 3 comparisons
|
|
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
|
|
AluIn1 <= regOut(to_integer(unsigned(opreg1)));
|
|
AluIn2 <= regOut(to_integer(unsigned(opreg2)));
|
|
when "0100" => --group 4 bitwise operations
|
|
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
|
|
AluIn1 <= regOut(to_integer(unsigned(opreg1)));
|
|
AluIn2 <= regOut(to_integer(unsigned(opreg2)));
|
|
regIn(to_integer(unsigned(opreg1))) <= AluOut;
|
|
regWE(to_integer(unsigned(opreg1))) <= '1';
|
|
|
when others =>
|
when others =>
|
--synthesis off
|
--synthesis off
|
report "Not implemented" severity error;
|
report "Not implemented" severity error;
|
--synthesis on
|
--synthesis on
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
|
|
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|