--This component interfaces with the memory controller and fetches the next instruction according to IP and CS
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--This component interfaces with the memory controller and fetches the next instruction according to IP and CS
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--Each instruction is 16 bits.
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--Each instruction is 16 bits.
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--How it works: IROut keeps the instruction that was featched in the "last" clock cycle.
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--How it works: IROut keeps the instruction that was featched in the "last" clock cycle.
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--What is basically required is that AddressIn must be the value that CS:IP "will be" in the next clock cycle
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--What is basically required is that AddressIn must be the value that CS:IP "will be" in the next clock cycle
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--This can cause some (in my opinion) odd logic at times, but should not have any problems synthesizing
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--This can cause some (in my opinion) odd logic at times, but should not have any problems synthesizing
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.tinycpu.all;
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use work.tinycpu.all;
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entity fetch is
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entity fetch is
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port(
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port(
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Enable: in std_logic;
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Enable: in std_logic;
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AddressIn: in std_logic_vector(15 downto 0);
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AddressIn: in std_logic_vector(15 downto 0);
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0); --interface from memory
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DataIn: in std_logic_vector(15 downto 0); --interface from memory
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IROut: out std_logic_vector(15 downto 0);
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IROut: out std_logic_vector(15 downto 0);
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AddressOut: out std_logic_vector(15 downto 0) --interface to memory
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AddressOut: out std_logic_vector(15 downto 0) --interface to memory
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);
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);
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end fetch;
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end fetch;
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architecture Behavioral of fetch is
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architecture Behavioral of fetch is
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signal IR: std_logic_vector(15 downto 0);
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signal IR: std_logic_vector(15 downto 0);
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begin
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begin
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process(Clock, AddressIn, DataIn)
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process(Clock, AddressIn, DataIn, Enable)
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begin
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begin
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--if(rising_edge(Clock)) then
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--if(rising_edge(Clock)) then
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if(Enable='1') then
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if(Enable='1') then
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IR <= DataIn;
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IR <= DataIn;
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AddressOut <= AddressIn;
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AddressOut <= AddressIn;
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else
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else
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IR <= x"FFFF"; --avoid a latch
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AddressOut <= "ZZZZZZZZZZZZZZZZ";
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AddressOut <= "ZZZZZZZZZZZZZZZZ";
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end if;
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end if;
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--end if;
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--end if;
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end process;
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end process;
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--AddressOut <= AddressIn when Enable='1' else "ZZZZZZZZZZZZZZZZ";
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--AddressOut <= AddressIn when Enable='1' else "ZZZZZZZZZZZZZZZZ";
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IROut <= IR;
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IROut <= IR;
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