--RAM module
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--RAM module
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--4096*8 bit file
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--4096*8 bit file
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--simultaneous write/read support
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--simultaneous write/read support
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--16 bit or 8 bit data bus
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--16 bit or 8 bit data bus
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--16 bit address bus
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--16 bit address bus
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--On Reset, will load a "default" RAM image
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--On Reset, will load a "default" RAM image
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity memory is
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entity memory is
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port(
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port(
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Address: in std_logic_vector(15 downto 0); --memory address
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Address: in std_logic_vector(15 downto 0); --memory address
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Write: in std_logic; --write or read
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Write: in std_logic; --write or read
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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Reset: in std_logic
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Reset: in std_logic
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);
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);
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end memory;
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end memory;
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architecture Behavioral of memory is
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architecture Behavioral of memory is
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constant SIZE : integer := 4096;
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constant BUSSIZE : integer := 8;
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type memorytype is array(0 to (size-1)) of std_logic_vector(7 downto 0);
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type memorytype is array(0 to integer((2**BUSSIZE))) of std_logic_vector(7 downto 0);
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signal mem: memorytype;
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signal mem: memorytype;
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begin
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begin
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writemem: process(Reset,Write, Address, UseTopBits, Clock)
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writemem: process(Reset,Write, Address, UseTopBits, Clock)
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variable addr: integer;
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variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
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begin
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begin
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addr := conv_integer(Address);
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addr := conv_integer(Address(BUSSIZE-1 downto 0));
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if(addr>size-1) then
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addr:=0;
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end if;
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if(rising_edge(Clock)) then
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if(rising_edge(Clock)) then
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if(Reset ='1') then
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if(Reset ='1') then
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mem <= (others => "00000000");
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--mem <= (others => "00000000");
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elsif( Write='1') then
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elsif( Write='1') then
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mem(conv_integer(addr)) <= DataIn(7 downto 0);
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mem(addr) <= DataIn(7 downto 0);
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if(UseTopBits='1') then
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if(UseTopBits='1') then
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mem(conv_integer(addr)+1) <= DataIn(15 downto 8);
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mem(addr+1) <= DataIn(15 downto 8);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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readmem: process(Reset,Address,Write,Clock)
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readmem: process(Reset,Address,Write,Clock)
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variable addr: integer;
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variable addr: integer range 0 to (2**BUSSIZE)-1 := 0;
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variable addr2: integer range 0 to (2**BUSSIZE)-1 := 0; -- for second part
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begin
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begin
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addr := conv_integer(Address);
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addr := conv_integer(Address(BUSSIZE-1 downto 0));
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if(addr>size-1) then
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addr2 := conv_integer(Address(BUSSIZE-1 downto 0));
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addr:=0;
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end if;
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if(Reset='1') then
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if(Reset='1') then
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DataOut <= (others => '0');
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DataOut <= (others => '0');
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elsif(Write='0') then
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elsif(Write='0') then
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DataOut <= mem(conv_integer(addr)+1) & mem(conv_integer(addr));
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DataOut <= mem(addr+1) & mem(addr);
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else
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else
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DataOut <= (others => '0');
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DataOut <= (others => '0');
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end if;
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end if;
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end process;
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end process;
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