--Memory management component
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--Memory management component
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--By having this separate, it should be fairly easy to add RAMs or ROMs later
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--By having this separate, it should be fairly easy to add RAMs or ROMs later
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--This basically lets the CPU not have to worry about how memory "Really" works
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--This basically lets the CPU not have to worry about how memory "Really" works
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--currently just one RAM. 1024 byte blockram.vhd mapped as 0 - 1023
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--currently just one RAM. 1024 byte blockram.vhd mapped as 0 - 1023
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity memory is
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entity memory is
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port(
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port(
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteEnable: in std_logic;
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WriteEnable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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Port0: inout std_logic_vector(7 downto 0)
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Port0: inout std_logic_vector(7 downto 0)
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-- Reset: in std_logic
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-- Reset: in std_logic
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--RAM/ROM interface (RAMA is built in to here
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--RAM/ROM interface (RAMA is built in to here
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--RAMBDataIn: out std_logic_vector(15 downto 0);
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--RAMBDataIn: out std_logic_vector(15 downto 0);
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--RAMBDataOut: in std_logic_vector(15 downto 0);
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--RAMBDataOut: in std_logic_vector(15 downto 0);
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--RAMBAddress: out std_logic_vector(15 downto 0);
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--RAMBAddress: out std_logic_vector(15 downto 0);
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--RAMBWriteEnable: out std_logic_vector(1 downto 0);
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--RAMBWriteEnable: out std_logic_vector(1 downto 0);
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);
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);
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end memory;
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end memory;
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architecture Behavioral of memory is
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architecture Behavioral of memory is
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component blockram
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component blockram
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port(
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port(
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Address: in std_logic_vector(7 downto 0); --memory address
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Address: in std_logic_vector(7 downto 0); --memory address
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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Enable: in std_logic;
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Enable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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constant R1START: integer := 15;
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constant R1START: integer := 15;
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constant R1END: integer := 1023+15;
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constant R1END: integer := 1023+15;
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signal addr: std_logic_vector(15 downto 0) := (others => '0');
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signal addr: std_logic_vector(15 downto 0) := (others => '0');
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signal R1addr: std_logic_vector(7 downto 0);
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signal R1addr: std_logic_vector(7 downto 0);
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signal we: std_logic_vector(1 downto 0);
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signal we: std_logic_vector(1 downto 0);
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signal datawrite: std_logic_vector(15 downto 0);
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signal datawrite: std_logic_vector(15 downto 0);
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signal dataread: std_logic_vector(15 downto 0);
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signal dataread: std_logic_vector(15 downto 0);
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--signal en: std_logic;
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--signal en: std_logic;
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signal R1we: std_logic_vector(1 downto 0);
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signal R1we: std_logic_vector(1 downto 0);
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signal R1en: std_logic;
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signal R1en: std_logic;
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signal R1in: std_logic_vector(15 downto 0);
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signal R1in: std_logic_vector(15 downto 0);
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signal R1out: std_logic_vector(15 downto 0);
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signal R1out: std_logic_vector(15 downto 0);
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signal port0we: std_logic_vector(7 downto 0);
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signal port0we: std_logic_vector(7 downto 0);
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signal port0temp: std_logic_vector(7 downto 0);
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signal port0temp: std_logic_vector(7 downto 0);
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begin
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begin
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R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
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R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
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addrwe: process(Address, WriteWord, WriteEnable, DataIn)
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addrwe: process(Address, WriteWord, WriteEnable, DataIn)
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begin
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begin
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addr <= Address(15 downto 1) & '0';
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addr <= Address(15 downto 1) & '0';
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if WriteEnable='1' then
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if WriteEnable='1' then
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if WriteWord='1' then
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if WriteWord='1' then
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we <= "11";
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we <= "11";
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datawrite <= DataIn;
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datawrite <= DataIn;
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else
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else
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if Address(0)='0' then
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if Address(0)='0' then
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we <= "01";
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we <= "01";
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datawrite <= x"00" & DataIn(7 downto 0); --not really necessary
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datawrite <= x"00" & DataIn(7 downto 0); --not really necessary
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else
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else
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we <= "10";
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we <= "10";
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datawrite <= DataIn(7 downto 0) & x"00";
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datawrite <= DataIn(7 downto 0) & x"00";
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end if;
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end if;
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end if;
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end if;
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else
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else
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datawrite <= x"0000";
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datawrite <= x"0000";
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we <= "00";
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we <= "00";
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end if;
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end if;
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end process;
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end process;
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assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address)
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assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock)
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variable tmp: integer;
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variable tmp: integer;
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variable tmp2: integer;
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variable tmp2: integer;
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variable found: boolean := false;
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variable found: boolean := false;
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begin
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begin
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tmp := to_integer(unsigned(addr));
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tmp := to_integer(unsigned(addr));
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tmp2 := to_integer(unsigned(Address));
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tmp2 := to_integer(unsigned(Address));
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if tmp2 <= 15 then --internal registers/mapped IO
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if tmp2 <= 15 then --internal registers/mapped IO
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if rising_edge(Clock) then
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if WriteWord='0' then
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if WriteWord='0' then
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if tmp2=0 then
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if tmp2=0 then
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dataread <= x"0000";
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dataread <= x"0000";
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gen: for I in 0 to 7 loop
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gen: for I in 0 to 7 loop
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if WriteEnable='1' then
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if WriteEnable='1' then
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if port0we(I)='1' then --1-bit port set to WRITE mode
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if port0we(I)='1' then --1-bit port set to WRITE mode
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port0(I) <= DataIn(I);
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port0(I) <= DataIn(I);
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port0temp(I) <= DataIn(I);
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port0temp(I) <= DataIn(I);
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else
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else
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port0(I) <= 'Z';
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port0(I) <= 'Z';
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end if;
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end if;
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else --not WE
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else --not WE
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if port0we(I)='0' then --1-bit-port set to READ mode
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if port0we(I)='0' then --1-bit-port set to READ mode
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dataread(I) <= port0(I);
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dataread(I) <= port0(I);
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else
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else
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dataread(I) <= port0temp(I);
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dataread(I) <= port0temp(I);
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end if;
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end if;
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end if;
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end if;
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end loop gen;
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end loop gen;
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elsif tmp2=1 then
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elsif tmp2=1 then
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dataread <= x"00" & port0we;
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dataread <= x"00" & port0we;
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if WriteEnable='1' then
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if WriteEnable='1' then
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port0we <= DataIn(7 downto 0);
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port0we <= DataIn(7 downto 0);
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setwe: for I in 0 to 7 loop
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setwe: for I in 0 to 7 loop
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if DataIn(I)='0' then
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if DataIn(I)='0' then
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port0(I) <= 'Z';
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port0(I) <= 'Z';
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end if;
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end if;
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end loop setwe;
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end loop setwe;
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else
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else
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dataread <= x"00" & port0we;
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dataread <= x"00" & port0we;
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end if;
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end if;
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else
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else
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--synthesis off
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--synthesis off
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report "Memory address is outside of bounds of RAM and registers" severity warning;
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report "Memory address is outside of bounds of RAM and registers" severity warning;
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--synthesis on
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--synthesis on
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end if;
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end if;
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else
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else
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--synthesis off
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--synthesis off
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report "WriteWord is not allowed in register area. Ignoring access" severity warning;
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report "WriteWord is not allowed in register area. Ignoring access" severity warning;
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--synthesis on
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--synthesis on
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end if;
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end if;
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end if;
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R1en <= '0';
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R1we <= "00";
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R1in <= x"0000";
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R1addr <= x"00";
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elsif tmp >= R1START and tmp <= R1END then --RAM bank1
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elsif tmp >= R1START and tmp <= R1END then --RAM bank1
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--map all to R1
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--map all to R1
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found := true;
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found := true;
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R1en <= '1';
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R1en <= '1';
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R1we <= we;
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R1we <= we;
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R1in <= datawrite;
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R1in <= datawrite;
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dataread <= R1out;
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dataread <= R1out;
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R1addr <= addr(8 downto 1);
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R1addr <= addr(8 downto 1);
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else
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else
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R1en <= '0';
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R1en <= '0';
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R1we <= "00";
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R1we <= "00";
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R1in <= x"0000";
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R1in <= x"0000";
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R1addr <= x"00";
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R1addr <= x"00";
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dataread <= x"0000";
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dataread <= x"0000";
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end if;
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end if;
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end process;
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end process;
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readdata: process(Address, dataread)
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readdata: process(Address, dataread)
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begin
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begin
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if Address(0) = '0' then
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if Address(0) = '0' then
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DataOut <= dataread;
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DataOut <= dataread;
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else
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else
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DataOut <= x"00" & dataread(15 downto 8);
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DataOut <= x"00" & dataread(15 downto 8);
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end if;
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end if;
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end process;
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end process;
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