--registerfile module
|
--registerfile module
|
--16 registers, read/write port for all registers.
|
--16 registers, read/write port for all registers.
|
--8 bit registers
|
--8 bit registers
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use IEEE.NUMERIC_STD.ALL;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use work.tinycpu.all;
|
use work.tinycpu.all;
|
|
|
entity registerfile is
|
entity registerfile is
|
|
|
port(
|
port(
|
WriteEnable: in regwritetype;
|
WriteEnable: in regwritetype;
|
DataIn: in regdatatype;
|
DataIn: in regdatatype;
|
Clock: in std_logic;
|
Clock: in std_logic;
|
DataOut: out regdatatype
|
DataOut: out regdatatype
|
);
|
);
|
end registerfile;
|
end registerfile;
|
|
|
architecture Behavioral of registerfile is
|
architecture Behavioral of registerfile is
|
|
|
type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
|
type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
|
signal registers: registerstype;
|
signal registers: registerstype;
|
--attribute ram_style : string;
|
--attribute ram_style : string;
|
--attribute ram_style of registers: signal is "distributed";
|
--attribute ram_style of registers: signal is "distributed";
|
begin
|
begin
|
regs:
|
regs: for I in 0 to 15 generate
|
for I in 0 to 15 generate
|
|
process(WriteEnable(I), DataIn(I), Clock)
|
process(WriteEnable(I), DataIn(I), Clock)
|
begin
|
begin
|
if rising_edge(Clock) then
|
if rising_edge(Clock) then
|
if(WriteEnable(I) = '1') then
|
if(WriteEnable(I) = '1') then
|
registers(I) <= DataIn(I);
|
registers(I) <= DataIn(I);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
DataOut(I) <= registers(I);
|
DataOut(I) <= registers(I);
|
end generate regs;
|
end generate regs;
|
|
|
