--registerfile module
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--registerfile module
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--16 registers, read/write port for all registers.
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--16 registers, read/write port for all registers.
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--8 bit registers
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--8 bit registers
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.tinycpu.all;
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use work.tinycpu.all;
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entity registerfile is
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entity registerfile is
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port(
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port(
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WriteEnable: in regwritetype;
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WriteEnable: in regwritetype;
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DataIn: in regdatatype;
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DataIn: in regdatatype;
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Clock: in std_logic;
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Clock: in std_logic;
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DataOut: out regdatatype
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DataOut: out regdatatype
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);
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);
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end registerfile;
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end registerfile;
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architecture Behavioral of registerfile is
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architecture Behavioral of registerfile is
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type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
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type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
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signal registers: registerstype;
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signal registers: registerstype;
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--attribute ram_style : string;
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--attribute ram_style : string;
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--attribute ram_style of registers: signal is "distributed";
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--attribute ram_style of registers: signal is "distributed";
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begin
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begin
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regs: for I in 0 to 15 generate
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regs: for I in 0 to 15 generate
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process(WriteEnable(I), DataIn(I), Clock)
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process(WriteEnable(I), DataIn(I), Clock)
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begin
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begin
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if rising_edge(Clock) then
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if falling_edge(Clock) then --I really hope this one falling_edge component doesn't bite me in the ass later
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if(WriteEnable(I) = '1') then
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if(WriteEnable(I) = '1') then
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registers(I) <= DataIn(I);
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registers(I) <= DataIn(I);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DataOut(I) <= registers(I);
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DataOut(I) <= registers(I);
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end generate regs;
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end generate regs;
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