LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY blockram_tb IS
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ENTITY blockram_tb IS
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END blockram_tb;
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END blockram_tb;
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ARCHITECTURE behavior OF blockram_tb IS
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ARCHITECTURE behavior OF blockram_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component blockram
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component blockram
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port(
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port(
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Address: in std_logic_vector(7 downto 0); --memory address
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Address: in std_logic_vector(7 downto 0); --memory address
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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WriteEnable: in std_logic_vector(1 downto 0); --write or read
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Enable: in std_logic;
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Enable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0)
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal Address: std_logic_vector(7 downto 0) := (others => '0');
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signal Address: std_logic_vector(7 downto 0) := (others => '0');
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signal WriteEnable: std_logic_vector(1 downto 0) := (others => '0');
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signal WriteEnable: std_logic_vector(1 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal Enable: std_logic := '0';
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signal Enable: std_logic := '0';
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--Outputs
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--Outputs
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signal DataOut: std_logic_vector(15 downto 0);
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signal DataOut: std_logic_vector(15 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: blockram PORT MAP (
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uut: blockram PORT MAP (
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Address => Address,
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Address => Address,
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WriteEnable => WriteEnable,
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WriteEnable => WriteEnable,
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Enable => Enable,
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Enable => Enable,
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Clock => Clock,
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Clock => Clock,
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DataIn => DataIn,
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DataIn => DataIn,
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DataOut => DataOut
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DataOut => DataOut
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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Clock <= '0';
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Clock <= '0';
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wait for clock_period/2;
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wait for clock_period/2;
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Clock <= '1';
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Clock <= '1';
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wait for clock_period/2;
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wait for clock_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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variable err_cnt: integer :=0;
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variable err_cnt: integer :=0;
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begin
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begin
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-- hold reset state for 100 ns.
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-- hold reset state for 100 ns.
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Enable <= '1';
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Enable <= '1';
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wait for 100 ns;
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wait for 100 ns;
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wait for clock_period*10;
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wait for clock_period*10;
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--case 1
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--case 1
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WriteEnable(0) <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"01";
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Address <= x"01";
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DataIn <= "1000000000001000";
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DataIn <= "1000000000001000";
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WriteEnable(0) <= '1';
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WriteEnable(0) <= '1';
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WriteEnable(1) <= '1';
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WriteEnable(1) <= '1';
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wait for 10 ns;
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wait for 10 ns;
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WriteEnable(0) <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
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assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
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--case 2
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--case 2
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Address <= x"33";
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Address <= x"33";
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DataIn <= "1000000000001100";
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DataIn <= "1000000000001100";
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WriteEnable(0) <= '1';
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WriteEnable(0) <= '1';
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WriteEnable(1) <= '1';
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WriteEnable(1) <= '1';
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wait for 10 ns;
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wait for 10 ns;
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WriteEnable(0) <= '0';
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WriteEnable(0) <= '0';
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WriteEnable(1) <= '0';
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WriteEnable(1) <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
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assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
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-- case 3
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-- case 3
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Address <= x"01";
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Address <= x"01";
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
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assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
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--case 4 (byte-wide test)
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Address <= x"11";
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WriteEnable(0) <= '1';
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WriteEnable(1) <= '1';
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DataIn <= x"932F";
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wait for 10 ns;
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WriteEnable(1) <= '0';
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DataIn <= x"165A";
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wait for 10 ns;
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WriteEnable(0) <= '0';
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wait for 10 ns;
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assert (DataOut=x"935A") report "byte-wide write error case 4" severity error;
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--case 5
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--case 5
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--Address <= x"FFFF";
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--Address <= x"FFFF";
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--Write <= '0';
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--Write <= '0';
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--wait for 10 ns;
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--wait for 10 ns;
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--assert (DataOut=x"FFC0") report "memory out of range error case 5" severity error;
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--assert (DataOut=x"FFC0") report "memory out of range error case 5" severity error;
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assert false
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assert false
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report "Testbench of memory completed successfully!"
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report "Testbench of memory completed successfully!"
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severity note;
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severity note;
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wait;
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wait;
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-- insert stimulus here
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-- insert stimulus here
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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