Subversion Repositories tinycpu

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE ieee.numeric_std.ALL;

use work.tinycpu.all;

use work.tinycpu.all;

ENTITY carryover_tb IS

ENTITY carryover_tb IS

END carryover_tb;

END carryover_tb;

ARCHITECTURE behavior OF carryover_tb IS

ARCHITECTURE behavior OF carryover_tb IS

-- Component Declaration for the Unit Under Test (UUT)

-- Component Declaration for the Unit Under Test (UUT)

  component carryover is

  component carryover is

    port(

    port(

      EnableCarry: in std_logic;

      EnableCarry: in std_logic;

      DataIn: in std_logic_vector(7 downto 0);

      DataIn: in std_logic_vector(7 downto 0);

      SegmentIn: in std_logic_vector(7 downto 0);

      SegmentIn: in std_logic_vector(7 downto 0);

      Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.

      Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.

      DataOut: out std_logic_vector(7 downto 0);

      DataOut: out std_logic_vector(7 downto 0);

--      Debug: out std_logic_vector(8 downto 0)

--      Debug: out std_logic_vector(8 downto 0)

    );

    );

  end component;

  end component;

  --Inputs

  --Inputs

  signal EnableCarry: std_logic := '0';

  signal EnableCarry: std_logic := '0';

  signal DataIn: std_logic_vector(7 downto 0) := "00000000";

  signal DataIn: std_logic_vector(7 downto 0) := "00000000";

  signal Addend: std_logic_vector(7 downto 0) := "00000000";

  signal Addend: std_logic_vector(7 downto 0) := "00000000";

  signal SegmentIn: std_logic_vector(7 downto 0) := "00000000";

  signal SegmentIn: std_logic_vector(7 downto 0) := "00000000";

  --Outputs

  --Outputs

  signal DataOut: std_logic_vector(7 downto 0);

  signal DataOut: std_logic_vector(7 downto 0);

  signal SegmentOut: std_logic_vector(7 downto 0);

  signal SegmentOut: std_logic_vector(7 downto 0);

--  signal Debug: std_logic_vector(8 downto 0);

--  signal Debug: std_logic_vector(8 downto 0);

  signal Clock: std_logic;

  signal Clock: std_logic;

  constant clock_period : time := 10 ns;

  constant clock_period : time := 10 ns;

BEGIN

BEGIN

  -- Instantiate the Unit Under Test (UUT)

  -- Instantiate the Unit Under Test (UUT)

  uut: carryover PORT MAP (

  uut: carryover PORT MAP (

    EnableCarry => EnableCarry,

    EnableCarry => EnableCarry,

    DataIn => DataIn,

    DataIn => DataIn,

    Addend => Addend,

    Addend => Addend,

    SegmentIn => SegmentIn,

    SegmentIn => SegmentIn,

    DataOut => DataOut,

    DataOut => DataOut,

--    Debug => Debug

--    Debug => Debug

  );

  );

  -- Clock process definitions

  -- Clock process definitions

  clock_process :process

  clock_process :process

  begin

  begin

    Clock <= '0';

    Clock <= '0';

    wait for clock_period/2;

    wait for clock_period/2;

    Clock <= '1';

    Clock <= '1';

    wait for clock_period/2;

    wait for clock_period/2;

  end process;

  end process;

  -- Stimulus process

  -- Stimulus process

  stim_proc: process

  stim_proc: process

    variable err_cnt: integer :=0;

    variable err_cnt: integer :=0;

  begin

  begin

    -- hold reset state for 20 ns.

    -- hold reset state for 20 ns.

    wait for 20 ns;

    wait for 20 ns;

    --wait for clock_period*10;

    --wait for clock_period*10;

    EnableCarry <= '1';

    EnableCarry <= '1';

    -- case 1

    -- case 1

    DataIn <= x"10";

    DataIn <= x"10";

    Addend <= x"02";

    Addend <= x"02";

    SegmentIn <= x"00";

    SegmentIn <= x"00";

    wait for 10 ns;

    wait for 10 ns;

    assert (SegmentOut=x"00" and DataOut = x"12") report "Addition Carryover when not appropriate" severity error;

    assert (SegmentOut=x"00" and DataOut = x"12") report "Addition Carryover when not appropriate" severity error;

    --case 2

    --case 2

    DataIn <= x"10";

    DataIn <= x"10";

    Addend <= x"FE"; -- -2

    Addend <= x"FE"; -- -2

    SegmentIn <= x"00";

    SegmentIn <= x"00";

    wait for 10 ns;

    wait for 10 ns;

    assert (SegmentOut=x"00" and DataOut = x"0E") report "Subtraction Carryover when not appropriate" severity error;

    assert (SegmentOut=x"00" and DataOut = x"0E") report "Subtraction Carryover when not appropriate" severity error;

    DataIn <= x"10";

    DataIn <= x"10";

    Addend <= x"EE"; -- -18 (-0x12)

    Addend <= x"EE"; -- -18 (-0x12)

    SegmentIn <= x"00";

    SegmentIn <= x"00";

    wait for 10 ns;

    wait for 10 ns;

    assert (SegmentOut=x"FF" and DataOut = x"FE") report "Subtraction Carryover Error" severity error;

    assert (SegmentOut=x"FF" and DataOut = x"FE") report "Subtraction Carryover Error" severity error;

    DataIn <= x"FE";

    DataIn <= x"FE";

    Addend <= x"04";

    Addend <= x"04";

    SegmentIn <= x"00";

    SegmentIn <= x"00";

    wait for 10 ns;

    wait for 10 ns;

    assert (SegmentOut=x"01" and DataOut = x"02") report "Addition Carryover Error" severity error;

    assert (SegmentOut=x"01" and DataOut = x"02") report "Addition Carryover Error" severity error;

    DataIn <= x"7F";

    DataIn <= x"7F";

    Addend <= x"7F";

    Addend <= x"7F";

    SegmentIn <= x"00";

    SegmentIn <= x"00";

    wait for 10 ns;

    wait for 10 ns;

    assert (SegmentOut=x"00" and DataOut = x"FE") report "Carryover when not appropriate case 1" severity error;

    assert (SegmentOut=x"00" and DataOut = x"FE") report "Carryover when not appropriate case 1" severity error;

    -- summary of testbench

    -- summary of testbench

    assert false

    assert false

    report "Testbench of carryover completed successfully!"

    report "Testbench of carryover completed successfully!"

    severity note;

    severity note;

    wait;

    wait;

    -- insert stimulus here 

    -- insert stimulus here 

    wait;

    wait;

  end process;

  end process;

END;

END;