LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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use work.tinycpu.all;
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use work.tinycpu.all;
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ENTITY fetch_tb IS
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ENTITY fetch_tb IS
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END fetch_tb;
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END fetch_tb;
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ARCHITECTURE behavior OF fetch_tb IS
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ARCHITECTURE behavior OF fetch_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component fetch is
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component fetch is
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port(
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port(
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Enable: in std_logic;
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Enable: in std_logic;
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AddressIn: in std_logic_vector(15 downto 0);
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AddressIn: in std_logic_vector(15 downto 0);
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0); --interface from memory
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DataIn: in std_logic_vector(15 downto 0); --interface from memory
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IROut: out std_logic_vector(15 downto 0);
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IROut: out std_logic_vector(15 downto 0);
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AddressOut: out std_logic_vector(15 downto 0) --interface to memory
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AddressOut: out std_logic_vector(15 downto 0) --interface to memory
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);
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);
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end component;
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end component;
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signal Enable: std_logic := '0';
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signal Enable: std_logic := '0';
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signal AddressIn: std_logic_vector(15 downto 0) := x"0000";
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signal AddressIn: std_logic_vector(15 downto 0) := x"0000";
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signal DataIn: std_logic_vector(15 downto 0) := x"0000";
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signal DataIn: std_logic_vector(15 downto 0) := x"0000";
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signal IROut: std_logic_vector(15 downto 0);
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signal IROut: std_logic_vector(15 downto 0);
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signal AddressOut: std_logic_vector(15 downto 0);
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signal AddressOut: std_logic_vector(15 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: fetch PORT MAP (
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uut: fetch PORT MAP (
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Enable => Enable,
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Enable => Enable,
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AddressIn => AddressIn,
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AddressIn => AddressIn,
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Clock => Clock,
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Clock => Clock,
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DataIn => DataIn,
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DataIn => DataIn,
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IROut => IROut,
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IROut => IROut,
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AddressOut => AddressOut
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AddressOut => AddressOut
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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Clock <= '0';
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Clock <= '0';
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wait for clock_period/2;
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wait for clock_period/2;
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Clock <= '1';
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Clock <= '1';
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wait for clock_period/2;
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wait for clock_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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variable err_cnt: integer :=0;
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variable err_cnt: integer :=0;
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begin
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begin
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-- hold reset state for 20 ns.
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-- hold reset state for 20 ns.
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wait for 20 ns;
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wait for 10 ns;
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--wait for clock_period*10;
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--wait for clock_period*10;
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Enable<= '1';
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Enable<= '1';
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wait for 10 ns;
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wait for 10 ns;
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Enable <= '1';
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Enable <= '1';
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AddressIn <= x"1234";
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AddressIn <= x"1234";
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DataIn <= x"5321";
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DataIn <= x"5321";
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wait for 10 ns;
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wait for 10 ns;
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assert (IROut = x"5321" and AddressOut = x"1234") report "basic operation failure" severity error;
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assert (IROut = x"5321" and AddressOut = x"1234") report "basic operation failure" severity error;
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AddressIn <= x"5121";
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AddressIn <= x"5121";
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DataIn <= x"1234";
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DataIn <= x"1234";
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wait for 5 ns;
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wait for 5 ns;
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assert (IROut = x"5321" and AddressOut = x"1234") report "Timing of latching is too early" severity error;
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assert (IROut = x"5321" and AddressOut = x"1234") report "Timing of latching is too early" severity error;
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wait for 5 ns;
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wait for 5 ns;
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assert (IROut = x"1234" and AddressOut =x"5121") report "basic operation failure 2" severity error;
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assert (IROut = x"1234" and AddressOut =x"5121") report "basic operation failure 2" severity error;
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AddressIn <= x"4278";
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AddressIn <= x"4278";
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DataIn <= x"5213";
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DataIn <= x"5213";
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Enable <= '0';
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Enable <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (IROut = x"1234" and AddressOut = "ZZZZZZZZZZZZZZZZ") report "Latching doesn't work on disable" severity error;
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assert (IROut = x"1234" and AddressOut = "ZZZZZZZZZZZZZZZZ") report "Latching doesn't work on disable" severity error;
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-- summary of testbench
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-- summary of testbench
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assert false
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assert false
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report "Testbench of fetch completed successfully!"
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report "Testbench of fetch completed successfully!"
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severity note;
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severity note;
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wait;
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wait;
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-- insert stimulus here
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-- insert stimulus here
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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