Subversion Repositories tinycpu

LIBRARY ieee;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

USE ieee.numeric_std.ALL;

use work.tinycpu.all;

use work.tinycpu.all;

ENTITY registerfile_tb IS

ENTITY registerfile_tb IS

END registerfile_tb;

END registerfile_tb;

ARCHITECTURE behavior OF registerfile_tb IS

ARCHITECTURE behavior OF registerfile_tb IS

-- Component Declaration for the Unit Under Test (UUT)

-- Component Declaration for the Unit Under Test (UUT)

  component registerfile

  component registerfile

  port(

  port(

    WriteEnable: in regwritetype;

    WriteEnable: in regwritetype;

    DataIn: in regdatatype;

    DataIn: in regdatatype;

    Clock: in std_logic;

    Clock: in std_logic;

    DataOut: out regdatatype

    DataOut: out regdatatype

  );

  );

  end component;

  end component;

  --Inputs

  --Inputs

  signal WriteEnable : regwritetype := (others => '0');

  signal WriteEnable : regwritetype := (others => '0');

  signal DataIn: regdatatype := (others => "00000000");

  signal DataIn: regdatatype := (others => "00000000");

  --Outputs

  --Outputs

  signal DataOut: regdatatype := (others => "00000000");

  signal DataOut: regdatatype := (others => "00000000");

  signal Clock: std_logic;

  signal Clock: std_logic;

  constant clock_period : time := 10 ns;

  constant clock_period : time := 10 ns;

BEGIN

BEGIN

  -- Instantiate the Unit Under Test (UUT)

  -- Instantiate the Unit Under Test (UUT)

  uut: registerfile PORT MAP (

  uut: registerfile PORT MAP (

    WriteEnable => WriteEnable,

    WriteEnable => WriteEnable,

    DataIn => DataIn,

    DataIn => DataIn,

    Clock => Clock,

    Clock => Clock,

    DataOut => DataOut

    DataOut => DataOut

  );

  );

  -- Clock process definitions

  -- Clock process definitions

  clock_process :process

  clock_process :process

  begin

  begin

    Clock <= '0';

    Clock <= '0';

    wait for clock_period/2;

    wait for clock_period/2;

    Clock <= '1';

    Clock <= '1';

    wait for clock_period/2;

    wait for clock_period/2;

  end process;

  end process;

  -- Stimulus process

  -- Stimulus process

  stim_proc: process

  stim_proc: process

    variable err_cnt: integer :=0;

    variable err_cnt: integer :=0;

  begin

  begin

    -- hold reset state for 100 ns.

    -- hold reset state for 100 ns.

    wait for 100 ns;

    wait for 100 ns;

    wait for clock_period*10;

    wait for clock_period*10;

    -- case 1

    -- case 1

    WriteEnable(1) <= '1';

    WriteEnable(1) <= '1';

    DataIn(1) <= "11110000";

    DataIn(1) <= "11110000";

    wait for 10 ns;

    wait for 10 ns;

    WriteEnable(1) <= '0';

    WriteEnable(1) <= '0';

    wait for 10 ns;

    wait for 10 ns;

    assert (DataOut(1)="11110000") report "Storage error case 1" severity error;

    assert (DataOut(1)="11110000") report "Storage error case 1" severity error;

    -- case 2

    -- case 2

    WriteEnable(5) <= '1';

    WriteEnable(5) <= '1';

    DataIn(5) <= "11110001";

    DataIn(5) <= "11110001";

    wait for 10 ns;

    wait for 10 ns;

    WriteEnable(5) <= '0';

    WriteEnable(5) <= '0';

    wait for 10 ns;

    wait for 10 ns;

    assert (DataOut(5)="11110001") report "Storage selector error case 2" severity error;

    assert (DataOut(5)="11110001") report "Storage selector error case 2" severity error;

    -- case 3;

    -- case 3;

    wait for 10 ns;

    wait for 10 ns;

    assert (DataOut(1)="11110000") report "Storage selector(remembering) error case 3" severity error;

    assert (DataOut(1)="11110000") report "Storage selector(remembering) error case 3" severity error;

    --case 4

    --case 4

    DataIn(0) <= x"12";

    DataIn(0) <= x"12";

    DataIn(1) <= x"34";

    DataIn(1) <= x"34";

    WriteEnable(0) <= '1';

    WriteEnable(0) <= '1';

    WriteEnable(1) <= '1';

    WriteEnable(1) <= '1';

    wait for 10 ns;

    wait for 10 ns;

    DataIn(0) <= x"90";

    DataIn(0) <= x"90";

    WriteEnable(0) <= '0';

    WriteEnable(0) <= '0';

    WriteEnable(1) <= '0';

    WriteEnable(1) <= '0';

    wait for 10 ns;

    wait for 10 ns;

    assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;

    assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;

    -- summary of testbench

    -- summary of testbench

    assert false

    assert false

    report "Testbench of registerfile completed successfully!"

    report "Testbench of registerfile completed successfully!"

    severity note;

    severity note;

    wait;

    wait;

    -- insert stimulus here 

    -- insert stimulus here 

    wait;

    wait;

  end process;

  end process;

END;

END;