LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY top_tb IS
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ENTITY top_tb IS
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END top_tb;
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END top_tb;
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ARCHITECTURE behavior OF top_tb IS
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ARCHITECTURE behavior OF top_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component top is
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component top is
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port(
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port(
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Reset: in std_logic;
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Reset: in std_logic;
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Hold: in std_logic;
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Hold: in std_logic;
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HoldAck: out std_logic;
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HoldAck: out std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
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DMA: in std_logic; --when high, Address, WriteEnable, and Data are connected to memory
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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WriteEnable: in std_logic;
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WriteEnable: in std_logic;
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Data: inout std_logic_vector(15 downto 0);
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Data: inout std_logic_vector(15 downto 0);
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Port0: inout std_logic_vector(7 downto 0);
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Port0: inout std_logic_vector(7 downto 0);
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--debug ports
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--debug ports
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DebugR0: out std_logic_vector(7 downto 0)
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DebugR0: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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signal Reset:std_logic:='0';
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signal Reset:std_logic:='0';
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signal Hold: std_logic:='0';
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signal Hold: std_logic:='0';
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signal HoldAck: std_logic;
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signal HoldAck: std_logic;
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signal DMA: std_logic:='0'; --when high, Address, WriteEnable, and Data are connected to memory
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signal DMA: std_logic:='0'; --when high, Address, WriteEnable, and Data are connected to memory
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signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes)
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signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes)
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signal WriteEnable: std_logic:='0';
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signal WriteEnable: std_logic:='0';
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signal Data: std_logic_vector(15 downto 0):=x"0000";
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signal Data: std_logic_vector(15 downto 0):=x"0000";
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signal Port0: std_logic_vector(7 downto 0);
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signal Port0: std_logic_vector(7 downto 0);
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--debug ports
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--debug ports
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signal DebugR0: std_logic_vector(7 downto 0);
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signal DebugR0: std_logic_vector(7 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: top PORT MAP (
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uut: top PORT MAP (
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Reset => Reset,
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Reset => Reset,
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Hold => Hold,
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Hold => Hold,
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HoldAck => HoldAck,
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HoldAck => HoldAck,
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Clock => Clock,
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Clock => Clock,
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DMA => DMA,
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DMA => DMA,
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Address => Address,
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Address => Address,
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WriteEnable => WriteEnable,
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WriteEnable => WriteEnable,
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Data => Data,
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Data => Data,
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DebugR0 => DebugR0,
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DebugR0 => DebugR0,
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Port0 => Port0
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Port0 => Port0
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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Clock <= '0';
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Clock <= '0';
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wait for clock_period/2;
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wait for clock_period/2;
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Clock <= '1';
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Clock <= '1';
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wait for clock_period/2;
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wait for clock_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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variable err_cnt: integer :=0;
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variable err_cnt: integer :=0;
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begin
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begin
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Port0 <= "ZZZZZZZZ";
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-- hold reset state for 100 ns.
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-- hold reset state for 100 ns.
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Reset <= '0';
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Reset <= '0';
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wait for 10 ns;
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wait for 10 ns;
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Reset <= '1';
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Reset <= '1';
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wait for 200 ns;
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wait for 200 ns;
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Reset <= '0';
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Reset <= '0';
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wait for 50 ns;
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wait for 50 ns;
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Port0(1) <= '1';
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Port0(1) <= '1';
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wait for 100 ns;
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wait for 200 ns;
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assert(Port0(0)='1') report "Toggle app not working" severity error;
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assert(Port0(0)='1') report "Toggle app not working" severity error;
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wait for 10 ns;
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wait for 10 ns;
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Port0(0) <= '0';
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Port0(1) <= '0';
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wait for 100 ns;
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wait for 200 ns;
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assert(Port0(0)='0') report "Toggle app not working 2" severity error;
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assert(Port0(0)='0') report "Toggle app not working 2" severity error;
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Reset <= '1';
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Reset <= '1';
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wait for 100 ns;
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wait for 100 ns;
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wait for 10 ns;
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wait for 10 ns;
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Hold <= '1';
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Hold <= '1';
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wait for 10 ns;
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wait for 10 ns;
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assert (HoldAck ='1') report "HoldAck not becoming high" severity error;
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assert (HoldAck ='1') report "HoldAck not becoming high" severity error;
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--load memory image
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--load memory image
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DMA <= '1';
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DMA <= '1';
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WriteEnable <= '1';
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WriteEnable <= '1';
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Address <= x"0100";
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Address <= x"0100";
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Data <= x"0057";
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Data <= x"0057";
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"0102";
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Address <= x"0102";
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Data <= x"00F1";
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Data <= x"00F1";
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"0104";
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Address <= x"0104";
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Data <= x"00FF";
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Data <= x"00FF";
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"0106";
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Address <= x"0106";
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Data <= x"0063";
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Data <= x"0063";
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wait for 10 ns;
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wait for 10 ns;
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--Address <= x"0108";
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--Address <= x"0108";
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--wait for 10 ns;
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--wait for 10 ns;
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DMA <= '0';
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DMA <= '0';
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wait for 10 ns;
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wait for 10 ns;
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Hold <= '0';
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Hold <= '0';
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wait for 10 ns;
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wait for 10 ns;
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--start the processor
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--start the processor
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Reset <= '0';
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Reset <= '0';
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wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
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wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
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wait for 10 ns; --wait 1 clock cycle for first instruction decode
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wait for 10 ns; --wait 1 clock cycle for first instruction decode
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assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
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assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
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wait for 10 ns;
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wait for 10 ns;
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assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
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assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
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assert false
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assert false
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report "Testbench of top completed successfully!"
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report "Testbench of top completed successfully!"
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severity note;
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severity note;
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wait;
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wait;
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-- insert stimulus here
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-- insert stimulus here
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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