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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 09:44:54 03/26/2008
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-- Create Date: 09:44:54 03/26/2008
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-- Design Name: counter
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-- Design Name: counter
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-- Module Name: counter_tb.vhd
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-- Module Name: counter_tb.vhd
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-- Project Name: clk_tb
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-- Project Name: clk_tb
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: counter
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-- VHDL Test Bench Created by ISE for module: counter
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tlc2_tb IS
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ENTITY tlc2_tb IS
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END tlc2_tb;
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END tlc2_tb;
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ARCHITECTURE behavior OF tlc2_tb IS
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ARCHITECTURE behavior OF tlc2_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT tlc2
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COMPONENT tlc2
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PORT(
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PORT(
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clk : IN std_logic;
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clk : IN std_logic;
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rst, j_left, j_right : IN std_logic;
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rst, j_left, j_right : IN std_logic;
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led : OUT std_logic_vector(2 downto 0) );
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led : OUT std_logic_vector(2 downto 0) );
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL clk : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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SIGNAL rst : std_logic := '0';
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SIGNAL rst : std_logic := '0';
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SIGNAL j_right : std_logic := '1';
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SIGNAL j_right : std_logic := '1';
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SIGNAL j_left : std_logic := '1';
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SIGNAL j_left : std_logic := '1';
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--Outputs
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--Outputs
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SIGNAL led : std_logic_vector(2 downto 0);
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SIGNAL led : std_logic_vector(2 downto 0);
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: tlc2 PORT MAP(
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uut: tlc2 PORT MAP(
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clk => clk,
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clk => clk,
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rst => rst, j_left => j_left, j_right => j_right,
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rst => rst, j_left => j_left, j_right => j_right,
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led => led
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led => led
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);
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);
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tb_clk : PROCESS
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tb_clk : PROCESS
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BEGIN
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BEGIN
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-- Wait 100 ns for global reset to finish
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-- Wait 100 ns for global reset to finish
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--wait for 100 ns;
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--wait for 100 ns;
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clk <= not clk;
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clk <= not clk;
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wait for 5 ns;
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wait for 5 ns;
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-- Place stimulus here
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-- Place stimulus here
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END PROCESS;
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END PROCESS;
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tb_s: PROCESS
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tb_s: PROCESS
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BEGIN
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BEGIN
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wait for 15 ns;
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wait for 15 ns;
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rst <= '0';
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rst <= '0';
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wait for 25 ns;
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wait for 25 ns;
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rst <= '1';
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rst <= '1';
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wait for 15 ns;
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wait for 15 ns;
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j_left <= '0';
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j_left <= '0';
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wait for 30 ns;
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wait for 30 ns;
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j_left <= '1';
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j_left <= '1';
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wait for 13000 ns;
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wait for 13000 ns;
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j_right <= '0';
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j_right <= '0';
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wait for 100 ns;
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wait for 100 ns;
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j_right <= '1';
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j_right <= '1';
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-- wait for 1000 ns;
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-- wait for 1000 ns;
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-- j_left <= '0';
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-- j_left <= '0';
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-- wait for 100 ns ;
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-- wait for 100 ns ;
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-- j_left <= '1';
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-- j_left <= '1';
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-- wait for 1500 ns;
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-- wait for 1500 ns;
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-- j_right <= '0';
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-- j_right <= '0';
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-- wait for 50 ns;
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-- wait for 50 ns;
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--- j_right <= '1';
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--- j_right <= '1';
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wait;
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wait;
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END PROCESS;
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END PROCESS;
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END;
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END;
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